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Are there enough FPGA tools?

Are there enough FPGA tools?
by Luke Miller on 05-09-2013 at 9:00 pm
Categories: FPGA, Xilinx

Sometimes I send my boy to grab me a tool and hours later he comes back with the wrong one. The patient man that I am, I calmly explain what I mean and then the world is right once more. Believe that do ya?

As you know the world is flooded with tools, tools and more tools. We all have our ruts and favorite flows and such but given the huge FPGA densities here and now and the future will no doubt bring more mixed signal devices what is the right set of tools?

I had a nice phone call with an EDA company this morning and we agree with this observation. People are scared of FPGAs, and HLS is not being embraced. Why? Of all the tools out there, in my small opinion HLS is the best tool of the last decade. I’m really curious what is stopping you? My guess is big company politics. Sometimes tool flows are set by people that do not do the job. Ahhh the process police, watch out they are corrupt.

The other tool observation is that now and beyond, for FPGAs we cannot settle for spin, re-spin like a 100 times over; especially in simulation. We make our test benches, we make our test vectors for hardware, we tweak our chip scope etc… There is much time wasted on doing close to the same things over and over. We must get better at it and need to do it once or twice. The tools need to intelligently handle requirements change, as the requirements are written by women therefore we are not sure what they mean. Can you believe I just wrote that? My old job would have me in front of HR as we speak, and I would have to fake listen. So I leave this blog open ended, and here is the question?

Say I want you to design a function, a SINE function, Taylor series expansion, floating point at 100 MHz, 20 clock latency, FIFO in/out. From start to finish what is the flow you would use? I’m thinking we would have many different answers. I’ll share mine, MATLAB, then Vivado HLS in about 5 minutes. Then simulate once in ModelSim. Looking back, my tools preferences are based on what I was forced to use by the man. Being on my own is allowing me to actually find the best flow and I know that will deviate some but this I know; the way I do things and you do things is going to change if we want to stay competitive.

The upside for FPGAs is they are staying around for a while. GPUs and CPUs cannot compete with the deterministic low latency solution that the FPGA offers. We FPGA users can control every bit, so that’s good news for you control freaks. So please comment below and share what flow you use.

lang: en_US

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Places Around the Austin Convention Center

Places Around the Austin Convention Center
by Paul McLellan on 05-09-2013 at 8:05 pm
Categories: Events

Jerry Philippe used to work for me at Compass and then very briefly we worked together at VaST. Today he works for Calypto in Austin. And it is the Austin part that is important because Jerry knows where the places are in any city to get good food and drink but Austin is his home.

Austin has an extraordinary number of restaurants and bars. But let’s start with places around the convention center. The first couple are open for lunch, the others are more like bars and steakhouses for dinner (steak seems to crop up a lot in Texas restaurants, is cattle a thing there?).

Swift’s Attic: Modern American small plates, sandwiches and more. 315 Congress Avenue at 3rd, suite 200. Open 11am to 2am.

Not holding to any particular cooking genre, but creative, whimsical and delicious. Not to be outdone the bar features 14 draft beers, 24 wines by the glass and cocktails all supplemented with an ice tap with 4 liquors able to be poured ice-cold instantly.

Sullivans: Sandwiches, steaks and stuff. 300 Colorado Street. Open 11.30am to 2am, Monday to Friday (and evenings at weekends).

(10 min walk from convention center located on Colorado and 3rd St.) is a vibrant neighborhood American Steakhouse featuring the finest steaks, seafood, hand-shaken martinis and live music. Comfortable fine dining in a lively atmosphere. Whether it’s for business, pleasure or both, we look forward to quickly becoming your favorite local steakhouse.

Elephant Room: Famous jazz bar, no food. 315 Congress Avenue (underneath Swift’s Attic). Usually no cover on weeknights. Happy hour 4-8pm. Walking distance.

Flemings: Steak and wine bar. 320 East 2nd Street.

(Behind convention center) For over ten years, Fleming’s Prime Steakhouse & Wine Bar has been the place to be in Austin for great food, amazing service and spectacular wine. Serving Midwest corn-fed USDA Prime beef, fresh seafood and our award-winning wine list, Fleming’s is the perfect destination for any occasion.

Eddie V’s: Pricey steak and seafood, so somewhere to get a C-level executive to take you out. Live Jazz. Not open for lunch. 315 E. 5th Street.

(2 block walk from convention center) Enjoy a robust and varied selection of fish and shellfish hand selected from the top catches of the day. Or indulge in our critically acclaimed aged steaks, broiled to perfection and lightly brushed with butter. Complemented, of course, by the ideal wine pairing, and completed with irresistible side dishes and desserts. All presented to you by a gracious, professional staff eager to serve.

Vince Young Steak House: Err…steak. Are we detecting a theme here. He used to be a pro footballer but Jerry assures me Vince’s steaks are better than his pro football record. 301 San Jacinto Blvd

(behind convention center) Vince Young Steakhouse is a chic, inviting and local Austin, Texas fine dining restaurant. We serve the finest steaks, wines and desserts in a downtown lively atmosphere with exceptional service. No matter what the occasion; a romantic dinner for two, an important business meeting or gathering your family around the table, at Vince Young Steakhouse, we look forward to providing you with an exceptional dining experience.

Kenichi: No steak (well maybe just a little, this is Texas), just great Japanese food and lots of variations of Sake. 419 Colorado St, just off Congress and 5th. Not open for lunch.

(walking distance of Convention Center) trendy sushi house with unique Texas style food. Kenichi prides itself on having the freshest seafood available in Austin to serve in all of its dishes. In addition to receiving recurring shipments of seafood from the coasts on a regular basis, Kenichi’s Executive Chef Shane Stark has utilized his love of fishing and the sea to cultivate relationships with Texas-based fisherman.

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Design IP round #2: after road-test, time for the race

Design IP round #2: after road-test, time for the race
by Eric Esteve on 05-09-2013 at 10:58 am
Categories: Cadence, EDA

Design IP, at least Interface IP, is about 15 years old, but the market was made of one large provider – Synopsys- with many small vendors around. Chip makers were not very comfortable with this picture, especially the Tier 1 considering that the risk (to see the big one being acquired by one of their direct competitor, say Samsung or Intel) was unacceptable. This was the picture in 2010: Synopsys leader on every Interface IP segment, Cadence leader in Verification IP, but only in VIP, and many small IP vendors acting like an electron cloud around Synopsys atom… Moreover, the market value of design IP was 5X the VIP market value, and this is still the case!

You have to keep in mind that building a design IP port-folio is far to be easy: ask Mentor Graphics why they had to give up in 2007, after 10 years of engineering effort. In 2010, Cadence has passed a clear message to the market, with Denali acquisition (for $300M +), but this message has been blurred when the company spoke about “EDA 360”. Design IP is a particular piece of the equation as it goes in a Chip which, in turn, goes to a wafer-fab, when Software, as important as it can be to release a product, is not as critic as a Design IP is.

The venue of Martin Lund (from Broadcom, known to deliver chips, not only paper, to the market) in Q2 2012 to take care of the “Silicon Realization Group” within Cadence has shuffled strong energy to cadence IP strategy. Martin has probably visited many IP vendors companies during 2012, then 2013 has been the time for finalization. Tensilica, provider of customizable DSP or CPU IP cores, has been the first in the list, being acquired by cadence in March 2013. Very interesting to notice, Simon Segars was quoted in the PR mentioning this acquisition… If you want to build a successful IP strategy, it’s probably better not to directly attack the undisputed leader, ARM Ltd.

Almost at the same time came the announcement that cadence was acquiring Cosmic Circuit, India based mixed-signal IP vendor, providing DAC and ADC, and Interface IP PHY supporting MIPI M-PHY and D-PHY and SuperSpeed USB PHY. If you look at the above picture, Cosmic brings the blue-boxes, that you will find in almost every SoC today. But that was not enough! Denali acquisition allowed supporting many more protocols Verification, but only two Design IP: DDRn Memory Controller and PCI Express.

Then came the first announcement during CDN-Live, on Tuesday this week, Evatronix acquisition. Box colors have changed in the meantime, but the principle stay the same: Evatronix acquisition brings the green colored boxes, USB 2.0 and USB 3.0 controllers, some MIPI controllers , eMMC and SDCard. You may have the impression that Martin Lund, above pictured, looks tired: the acquisition contract with Evatronix was signed during Sunday night, right on time for CDN-Live! According with Wosjiech Sakowski, Evatronix co-founder and President, the signature came after long hours –days – of negotiations.

But I keep very interesting acquisition related news, which was made public during CDN-Live as well, even if it was effective a few weeks ago: Cadence has bought, not a company, but an Engineering team. This 25 Engineers Canadian based team from PMC-Sierra is 100% specialized in SerDes design, and you can guess that they don’t limit to 5 Gbps PHY. Why is this news so strategic? Because PHY is strategic, as I already claimed in Semiwiki here.

Just remember that Synopsys had to buy a PCIe 8 Gbps PHY to MoSys last year to be able to support customers. This design team is probably capable to manage 25 Gbps SerDes (my guess). In this case, half a dozen IP sales from this team could generate Evatronix per year revenue, made of multiple dozens of controller IP sales. But that’s not the most important: this who manage properly the PHY IP business will manage to get higher market share of Integrated (PHY + Controller) Interface IP sales, now and for the future; especially in the future.

Eric Esteve from IPNEST

lang: en_US

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The Morphing of Intel’s Monopoly

The Morphing of Intel’s Monopoly
by Ed McKernan on 05-09-2013 at 12:01 am
Categories: Foundries, Intel Foundry, TSMC

It was a generation ago when Intel, less than three years old, created the three fundamental building blocks of the compute era: the DRAM, the EPROM and the Microprocessor, an incredible feat of innovation by any measure. Manufacturing yield, not power or performance determined success of failure and in the first two Continue reading “The Morphing of Intel’s Monopoly”

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GSA Awards…Nominate!

GSA Awards…Nominate!
by Paul McLellan on 05-08-2013 at 4:50 pm
Categories: Global Semiconductor Alliance, Semiconductor Services

For 19 years GSA (presumably going back to the days when it was Fabless Semiconductor Association, FSA) has recognized public and private semiconductor companies. The awards are celebrated at a dinner. This year’s dinner is on Thursday December 12th at the Santa Clara Convention Center. The keynote speaker at the dinner is Cory Booker, the mayor of Newark NJ.

Nominations for the awards are now open.

  • Dr. Morris Chang Exemplary Leadership Award. The GSA’s most prestigious award recognizes individuals for their exceptional contributions to drive the development, innovation, growth and long-term opportunities for the semiconductor industry. Nominations will be accepted until June 3, 2013.
  • Best Financially Managed Semiconductor Company
  • Most Respected Private Semiconductor Company Award. Designed to identify the private company garnering the most respect from the industry . GSA’s Private Awards Committee provides a list of respectable private companies to be voted on by GSA membership. On-line voting takes place to allow GSA members to cast a ballot for the private semiconductor company that they most respect. (Nominations by June 28th)
  • Most Respected Public Semiconductor Company Awards
  • Outstanding Asia-Pacific (APAC) Semiconductor Company Award
  • Outstanding Europe, Middle-East, Africa (EMEA) Semiconductor Company Award (July 12th)
  • Start-Up to Watch Award. GSA’s Private Awards Committee, comprised of members of the Emerging Company CEO Council, venture capitalists and select serial entrepreneurs in the industry, selects up to two winners of the Start-up to Watch Award by identifying the semiconductor company(s) that demonstrates the potential to positively change its market or the semiconductor industry. (June 28th)

Public companies do not need to be nominated since they are assessed based on public financial data. But private companies and individuals do need to be nominated. Forms.

If you want to attend the dinner (either as an individual or as a company purchasing a whole table) then the details are here. The dinner is made possible by sponsor TSMC as well as some other general sponsors.

Full details of all the awards, including the small print (“must be a semiconductor company” etc) are on the GSA website here. This is also where you can find links to the nomination forms .

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IP Quality: Foundation of a Successful Ecosystem

IP Quality: Foundation of a Successful Ecosystem
by Eric Esteve on 05-08-2013 at 8:46 am
Categories: Foundries, IP, TSMC

Talking about Design IP (I mean successful Design IP) lead you to quickly pronounce the two magic key words: Quality and Ecosystem. Those who remember the IP emergence in the mid 90’s know very well why Quality has to be a prerequisite when dealing with Design IP, as they probably have paid the price of mediocre IP quality at that time. More recently, business analysts have realized that the foundation for a successful IP based business was linked to building a complete Ecosystem, just think about the 1000 ARM partners…

As a matter of fact, some of these partners are heavyweight, like Taiwan based TSMC, that any IP vendor would like to count within it IP Ecosystem. That’s why TSMC has created, back in 2000, the TSMC9000 program as one of the pillar of Open Integration Platform (OIP) ecosystem. TSMC9000 clearly defined goal is to check for, assess and audit the quality of Design IP part of OIP ecosystem. TSMC9000 is not only based on cleaver communication, but on a very rigorous process! Don’t forget that any of this Design IP function will end up into a very concrete piece of Silicon, an Integrated Circuit, and that both TSMC (who process it into Wafer Fab) and the Fabless customer who plan to sell it, expect this IC to run first time right. As an IP vendor, you submit to TSMC (in fact to “IP Portfolio, Design Infrastructure Division”) the functional IP you have developed, from USB PHY to DDR Memory Controller, LVDS I/O to DSP and many more. TSMC9000 Quality Assurance system consists to run successively:

  • DRC/LVS (if you submit Hard IP)
  • Data Consistency check
  • ESD tolerance verification
  • Design margin verification (Shmoo plot)
  • Then generate Silicon reports (on Test chips) and store production history when it’s relevant.

Your IP will hopefully be sold to customer, integrated into a design data base by this customer who will finally submit the final DB for Tape Out. At this stage, TSMC will use “IP Master” tool, running “Tape Out consistency checks” versus the previously generated data in IP9000 IP Quality.

You may wonder that TSMC9000 IP qualification process only applies to very complexes or very specific or “exotic” Design IP… In fact, if you take a look at the above picture, you realize that TSMC9000 apply to ALL the Libraries, Memories or IP, including Hard and Soft IP. How many IP would you guess? Are we talking about 500 Design IP, or 1000, maybe 2000? Just take a look at the statistics listed below…

There are no less than 8917 active IP coming from the IP Alliance for a total of almost 10, 000 IP in TSMC 9000! Another figure is surprising: almost 200 Design IP are being reviewed every month by TSMC. This means that TSMC has built a specific team 100% dedicated to run IP9000 QA Process, a 30 people team in charge of IP Port-Folio validation (and selection). As an IP vendor, you probably better understand why TSMC has to be highly selective when accepting new IP… Are you still in IP vendor shoes? Just look at the failed TSMC 9000 IP count: 1,452!!

Even if a dummy density violation or some Silicon corner out of specification can be accounted for a failure, out of these 1,452 IP, as high as 373 can generate potential fatal failure. Fatal simply means that a Tape Out including such IP would have led to a redesign. Thus, if you go now into Fabless shoes, you will just thank your foundry supplier for being so selective!

If you ever surfed on a foundry web site, you probably remember the “Bronze”, “Silver” and “Gold” denomination for Design IP. If you look at the above picture, these denominations look a little bit obsolete: before a Design Hard IP can be validated for volume production, it has to pass through no less than ten or more verification phases, before the Design IP can reach a high enough confidence level. If we consider advanced nodes, the Hard IP has to pass through 13 various checking phases, from DRC, LVS, ERC and Antenna checks up to Split Lot Silicon Assessment, testing results audits by TSMC test lab to finally go to production. In fact, Quality assessment is a never ending process, when the ASIC or ASSP is in volume production, the IC yield is continuously traced… probably up to the product End Of Life!
I didn’t know that Quality could be a fascinating topic (to be honest, I thought it was not), but we are working in such demanding industry that even Quality becomes part of the dream: I have today in my pocket a gaming station from the 2000’s, a phone from the 90’s, a color TV from the 80’s and a Supercomputer from the 70’s, all of these almost in a single chip!

Eric Esteve

lang: en_US

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Improving Design Practices for an Image Sensor IDM

Improving Design Practices for an Image Sensor IDM
by klujan on 05-07-2013 at 8:30 pm
Categories: EDA, Tanner EDA

With nearly twenty five years in business, Tanner EDA Application Engineers have seen a wide range of support requests. One consistent topic area is around design data management and design reuse. In one recent instance, our customer, an IDM who produces imaging sensors for infrared vision systems, called on Tanners AE team for onsite consulting to help drive design consistency and to create libraries of common cells that could be shared. Tanner’s AEs had previously delivered tool training for several of their design groups, but business growth led the customer to add several new designers who were less experienced with these practices.

Working onsite with the designers, I learned about the common structures they needed to create as well as the inconsistencies they experienced in the manufacturing and snap grid settings – this led to us implementing a server-based Technology Library for setup and common cell structures. Because image sensor design is fraught with redesign and resizing of common cells, we also implemented a set of T-Cell templates that designers could use to create structures quickly and efficiently. (In addition to the first-order impact on design time, this approach also greatly improved quality and reduced rework). The template T-Cells were added to the server-based Technology Library; allowing shared access for all designers. With Tanner’s v16 of L-Edit, the designers make use of the multi-user Open Access environment, allowing multiple designers to work on their respective cells within a common design. The productivity gains from this consulting engagement have already delivered tangible ROI to the customer, and they have scheduled follow-on consulting to address challenges in other parts of their workflow.

Tanner EDA will exhibit at DAC 2013, June 2-4[SUP]th[/SUP], in booth 2442 and in the ARM Connected Community® (CC) Pavilion, #921. The entire analog and mixed-signal design suite will be demonstrated:

  • Front-end design tools for schematic capture, analog SPICE and FastSPICE simulation, digital simulation, transient noise analysis, waveform analysis,
  • Back-end tools, including analog layout, SDL, routing and layout accelerators as well as static timing and synthesis, and
  • Physical verification, including DRC and LVS.

Visit www.tannereda.comto learn more. DAC demo sign-ups are HERE.

Tanner EDA provides a complete line ofsoftware solutionsthat drive innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS.Customersare creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

lang: en_US

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How To Design a TSMC 20nm Chip with Cadence Tools

How To Design a TSMC 20nm Chip with Cadence Tools
by Paul McLellan on 05-07-2013 at 8:10 pm
Categories: Cadence, EDA, Foundries, TSMC

Every process node these days has a new “gotcha” that designers need to be aware of. In some ways this has always been the case but the changes used to be gradual. But now each process node has something discontinuously different. At 20nm the big change is double patterning. At 14/16nm it is FinFET.

Rahul Deokar and John Stabenow of Cadence and Jason Chen from TSMC will present, “20nm Design Methodology: A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Encounter, Virtuoso, and Signoff tools.” Well, I think my title gets to the point a bit quicker!


Double patterning has been forced on us by limitations in lithography. We still use 193nm light even though we are now drawing features that are 20nm (actually there isn’t really anything on a 20nm chip that measures 20nm). If we try and draw all the polygons on the lower layers of the process, the features are too close to print correctly. So instead we have to separate them onto two separate masks, so the polygons in effect alternate. Not all layout can be split in this way, which is usually called coloring since it is basically a graph-coloring algorithm, so routers and designers need to be careful not to create uncolorable layout.

Sometimes, even (say for analog), the designer wants to color the polygons manually. Why would they do that? At this process node, the two masks are not self-aligning. They are aligned by the vestigials on the wafer that the stepper detects, just like any other mask (actually reticle) but the two polygon layers have some slop in their alignment. This means that there is much tighter control of parasitics between polygons on the same mask (which are automatically self-aligning) and different masks (which are not).

There are self-aligned double patterning techniques. They use a sacrificial spacer (where both sides of the spacer eventually get whatever is being created on that layer) but they are more expensive. If you want to get a few chapters ahead, we will need to use these approaches to build transistors at the 10nm node (and maybe the lower levels of interconnect) but at 20nm we are not. I’m not sure about 16nm.

The layout rules for 20nm are very much more restrictive, even without worrying about double patterning. There is a lot less flexibility about what can go where, and weird features like dummy gates that we started to see at 28nm (where an extra poly is required on the end of a gate that is not electrically significant, to ensue that the gate prints and behaves correctly). We also have layout dependent effects (LDE) where the transistor circuit level performance depends on how close the transistor is to other features on the die, especially well boundaries. And even design rules that depend on electrical details. There is also local interconnect that appears between the transistors and the lowest level of true metal, with all its own rules.


A little more detail on what you will learn:

  • How in-design double patterning technology (DPT) and design rule checking (DRC) can improve your productivity
  • How both colored and colorless methodologies are supported, and data is efficiently managed in front-to-back design flows
  • How local interconnect layers, SAMEMASK rules, and automated odd-cycle loop prevention are supported
  • How mask-shift modeling with multi-value SPEF is supported for extraction, power, and timing signoff.

The webinar is being given twice on May 23rd at 9am Pacific (early evening in Europe) and at 6.30pm Pacific (morning in Asia). Details here. Registration here.

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Bangers: the Best Beer Bar in Austin; Live Oak Brewing, the Best Beer in Austin

Bangers: the Best Beer Bar in Austin; Live Oak Brewing, the Best Beer in Austin
by Paul McLellan on 05-07-2013 at 8:10 pm
Categories: EDA, Events

OK, enough with all this semiconductor geeky stuff. The important thing about DAC is…where to go to eat to avoid standard issue convention center chicken Caesar salad.

And a 7 minute walk from the convention center is Bangers Sausage House and Beer Gardenwhere you can have the $8 “executive” lunch consisting of a beer and a sausage. That’s probably cheaper than that Caesar salad. But there is a catch, they only serve lunch Thursday to Sunday, as if to deliberately annoy many DAC attendees.


How many beers do they have? That would be 103 different taps. The full list is above, click on it if you want an almost readable version. As for those sausages, they are supplied with meat from all over the area and as a result have the biggest sausage selection in Austin.

So if you want to experience Bangers, go on Sunday for lunch or go one evening, but not Monday night because that is the big 50th Anniversary DAC Celebration Party at the home of Austin City Limits.

Bangers is at 79 & 81 Rainey Street. it’s website is here.

OK. So Bangers is great but if you are an exhibitor and you actually want a beer during the exhibit where can you go.

Well, how about Live Oak Brewing Company. How about experiencing the Live Oak Hefeweizen, the #1 ranked beer on the Beer Advocate’s list of Top Beers in the Southwest. Several more beers make the top 50: Old Treehugger Barley Wine, Primus Weizenbock, Pilz, Liberation Ale, Roggenbier and Oaktoberfest. You didn’t really need to get back for afternoon booth duty anyway, did you?

Live Oak Brewing Company is at 3301 East 5th Street. It’s website is here. Actually I just realized that this is just the brewery. To taste the beer (other than on a brewery tour) it is available all over Austin. Maybe even near the convention center. Early in the week when Bangers is not open until the evening.

Anyone from Austin or with local knowledge, please add more suggestions in the comments.

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Wireless Algorithm Validation from System to RTL to Test

Wireless Algorithm Validation from System to RTL to Test
by Daniel Nenni on 05-07-2013 at 8:05 pm
Categories: Aldec, EDA

LSK 1123

This year’s #50DAC will be chock-full of technical content because that is what attracts the masses of semiconductor professionals, like moths to a flame, or like me to a Fry’s Electronics store. Interesting note, I went to high school with Randy Fry. His Dad started the Fry’s supermarket chain which he sold then he went into electronics. That’s why Fry’s Electronics has a similar layout/business model as a grocery store.

Agilent Technologies and Aldec will co-host a technical session on how to validate a digital signal processing algorithm for both floating and fixed point levels. Attendees will gain insight on cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.

Attendees will gain valuable, practical skills with the following tools and equipment:

  • Agilent SystemVue as a programming environment to simulate and verify system performance prior to realizing a dedicated hardware implementation.
  • Co-simulation interface with Aldec Riviera-PRO for validation of functional blocks described in SystemVue hardware design library.
  • HIL (Hardware in the Loop) to accelerate both design validation and test coverage, saving additional development time.

Date: Wednesday, June 5, 2013
Time: 2:00 PM — 4:00 PM
Location: 17AB
Topic Area: System Level Design and Communication
Speakers:
Dmitry Melnik – Aldec, Inc., Henderson, NV
Sangkyo Shin – Agilent Technologies, Inc., Santa Rosa, CA

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, electronic design automation (EDA) and embedded systems and software (ESS).

Members are from a diverse worldwide community of more than 1,000 organizations that attend each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives, and researchers and academicians from leading universities.

Close to 300 technical presentations and sessions are selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies.

A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP), embedded systems and design services providers.

The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.

Some of the highlights of this year’s DAC include:

  • Keynotes by industry leaders/visionaries
  • Technical Program (panels, special sessions, Designer Track)
  • Forums, tutorials, and workshops
  • Management Day
  • Exhibition Floor
  • Colocated Conferences
  • Awards for professionals and students

About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com

See Aldec DAC demos HERE.

lang: en_US