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See Hogan’s Heroes at DAC 2013: The EDA Hunger Games!

See Hogan’s Heroes at DAC 2013: The EDA Hunger Games!
by Holly Stump on 03-31-2013 at 8:05 pm
Categories: EDA, Events

Risks and Rewards of Engaging with EDA Startups:The Hunger Games!

Doing business with EDA startups comes with both risks and rewards. The Hogan’s Heroes panel at DAC 2013 features key decision makers from fabless, startup and vc firms sharing candid opinions on this risk/reward equation, and the financial and technical issues of engaging with EDA startups.
·How often do companies “burn out” and users “get burned?”
·How can you protect yourself?
·And, how do customers sometimes contribute to the rise and fall?

Jim believes that startups are the innovation engine of EDA.“If you do not invest in small companies, you will get roadmaps from the EDA “gorillas” but not much new technology. Certainly there is risk, but without startups, we don’t see a lot of innovation.”

Hear what the panelists have to say!

Moderator: Jim Hogan, Private Investor

Jim is currently the managing partner of Vista Ventures, LLC. Jim has worked in the semiconductor design and manufacturing industry for more than 35 years gaining experience as a senior executive in electronic design automation, semiconductor intellectual property, semiconductor equipment, and fabrication companies. Mr. Hogan holds a B.A degree in mathematics, a B.S. degree in computer science and an M.B.A., all from San Jose State University.

Panelist: Atul Sharan, Artiman Ventures

Atul is currently Entrepreneur in Residence, Artiman Ventures. Previously, Investment Advisor at Darwin Venture Management; President & CEO AutoESL (acquired by Xilinx); Corporate Consultant at Cadence Design Systems; Founder, President & CEO at Clear Shape Technologies (acquired by Cadence); Resident at Mohr Davidow Ventures; Vice President – Marketing, Business Development & Applications at Synopsys; Senior VP – Worldwide Sales & Marketing at Numerical Technologies Inc. (IPO; acquired by Synopsys); Business Development & Marketing at Ambit Design Systems (acquired by Cadence); GM – India Operations at VLSI Technology Inc., Compass; Engineering Manager at Altera; and at IDT. Atul’s education spans the University of California, Berkeley – Walter A. Haas School of Business, MBA, Finance & Management; University of Houston MS, Engineering; and IIT Kanpur, BS, Engineering.

Panelist: Sanjay Lall, Board of Directors, Ausdia Inc.

Sanjay Lall is currently on the Board of Directors at Ausdia, with over 20 years of experience in the electronic design automation (EDA) and semiconductor industries. Sanjay is also chairman and managing partner at Cronox Group, on the board of advisors at Verdigris Technologies, and a director at Mobi-holdings.Previously VP of worldwide sales at Extreme DA, acquired by Synopsys in2011; President and CEO at Silicon Software; President & CEO at NION Interactive; and accelerated sales growth for EDA companies such as Sente (acquired by Frequency Technology), Triquest (acquired by Summit Design), Ultima Interconnect (acquired by Cadence), Frontline Design Automation (acquired by Avanti), CadMOS (acquired by Cadence), Plato Design (acquired by Cadence), Q Design (acquired by Cadence), Brion Technology (acquired by ASML) and Epic Design (acquired by Synopsys).He holds a B.S.in electrical engineering and computer science from Santa Clara University.

Panelist: Dave Crohn, Senior Director, Engineering, Broadcom….and DAC Party Singing Idol!

Dave currently manages all of EDA for Broadcom Corporation, a leader in the industry providing broadband communications. Dave had done design work for 24 years starting with Sperry (later Unisys) back in the ECL days; ETA Systems designing a 10 GFLOP supercomputer in liquid nitrogen; Siemens including 1 year working in Munich; ADC Telecommunications; then Motorola; and finally on to Broadcom where he’s been for the last 14 years. At Broadcom he originally managed the standard cell team and later moved into the managing EDA role at Broadcom for the last 9 years. Working for thedifferent companies gave Dave the opportunity to work with many different EDA tools as well as different technologies throughout his career. This now lends itself to working with engineering at Broadcom to determine best in class technology to pursue corporate-wide. Dave also negotiates the contracts and manages EDA supplier relationships. Dave holds a BSEE from the University of Minnesota.

Let the EDA Hunger Games Begin…

Join us Tuesday, June 4, at DAC 2013 in Austin Texas. For more information, please see www.dac.com

And, to EDA startups and their customers:

“May the odds be ever in your favor!
Ever in your favor…..”

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Samsung 28nm Still Does Not Yield?

Samsung 28nm Still Does Not Yield?
by Daniel Nenni on 03-31-2013 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC

As if Samsung didn’t have enough to worry about with their new neighbor to the North (Korea) declaring war, Samsung 28nm is still NOT yielding. In my previous blog “Can Samsung Deliver as Promised?” I wondered what will power the new Galaxy S4 phones that Samsung has been aggressively marketing. You would think it would be a 28nm version of the Exynos 5 Octa SoC that was launched at CES in January with former President Bill Clinton. As it turns out that is not the the case. I like honesty, I like transparency, I don’t like how Samsung is communicating with us on this one.


The first launch of the Galaxy S4 will be powered by 28nm silicon all right, TSMC 28nm silicon in the form of a QCOM Snapdragon 600. That must really hurt the Samsung foundry folks since they are negative selling TSMC and others at the top fabless semiconductor companies in an effort to win 14nm business. At first it was rumored that it was an LTE issue with Exynos but Samsung denied that recently on Twitter of all places. The people I asked here in Silicon Valley, one of which is a Samsung customer, said it was in fact a 28nm manufacturing problem.

Remember, Samsung went Gate-First HKMG instead of Gate-Last like TSMC:

Gate-first HKMG is easier to implement as a transition from a traditional poly/SION structure, she explained. The construction of the gate and transistor remain the same, though the materials are different (i.e., a high-k gate oxide instead of oxynitride); a metal gate is inserted, and then poly on top of that—and the rest of the flow is “basically the same as previous generation structures.” Gate-first also is “much simpler” to implement from a process migration standpoint in terms of IP implementation, and fewer restrictive design rules (gate-last requires CMP around the gate structure). “We can maintain 50% shrink from 45nm to 32nm because there’s not as many restrictive design rules,”Ana Hunter (VP foundry at Samsung Semiconductors)said. This makes the process particularly good for mobile applications, as it’s cost-effective and “very good on gate leakage—a >100× improvement from 45nm to 32nm.”


During one of my Taiwan trips in 2010 I asked Dr. Shang-yi Chiang why TSMC decided on Gate-last versus Gate-first. Shang-yi is TSMC’s Executive Vice President and Co-Chief Operating Officer, he joined TSMC in July 1997 as Vice President of Research and Development (R&D) and has successfully delivered many new process technologies including 28nm. Shang-yi told me quite honestly that TSMC had both Gate-first and Gate-last 28nm HKMG architectures under consideration but concluded that yes Gate-first is simpler (less manufacturing steps) and would be easier to design to (less restrictive) but it was much harder to yield, especially for complex SoCs. The rest is history, TSMC successfully implemented Gate-last 28nm and they have 100% market share as a result.

This all goes to credibility which is the cornerstone of collaboration and the fabless semiconductor ecosystem. Let’s not forget how all this fabless stuff got started. The traditional semiconductor companies (IDMs) were not doing their jobs. They rented out their excess capacity allowing former employees to innovate and bring us companies such as QCOM, BCOM, NVDA, XLNX, and the resulting fabless semiconductor ecosystem.

Now, Intel and Samsung (both IDMs) are trying to get back control of the semiconductor industry and will spend whatever it takes to do so. According to IC Insights, their combined capital expenditures now represent more than 40% of the total semiconductor capital spending. To me this is a great cause for concern for the fabless semiconductor ecosystem. Just my opinion of course.

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Circuit Analysis & Debugging

Circuit Analysis & Debugging
by Daniel Payne on 03-30-2013 at 3:18 pm
Categories: Concept Engineering, EDA

Spice Debugger

In EDA we often talk about how fast a SPICE circuit simulator is, or about capacity and accuracy compared to silicon measurements. Yes, speed, capacity and accuracy are important, however when talking to actual transistor-level circuit designers you discover something quite different, most of their time is spent doing debugging, looking at waveforms, reading tables of text results, and trying to understand why the circuit is acting differently than intended. In order to really understand what is happening with your newest IP block or re-used IP, you need some automation help in looking at the netlist or interconnect in a visual way.

Fortunately there is help and it comes in the form of an EDA tool that lets you visualize any SPICE netlist so that you can quickly traverse it. Talking about it doesn’t do much justice, so instead I invite you to attend an online webinarhosted by Concept Engineering and EDA Direct, scheduled for Tuesday, April 9th from 10AM to 11AM, PDT.

Webinar
Here’s what will be covered during the webinar:

  • Understand the topology and function of the circuit without having schematics
  • Automatic Schematic generation from Spice, DSPF, LVS Spice, Spectre
  • Traverse hierarchy, search nets/instances very fast
  • Cross probing with GDS for highlighting nets
  • Verify connectivity especially for multi fanin and fanout nets
  • ERC Checking: Floating input and output nets, heavy connected nets, etc.
  • Generate design statistic & reports: Instance & primitive counts
  • Turn on/off Parasitics from extracted netlist to debug designs quickly
  • Debug power/ground connectivity issues
  • Analyze results of LVS runs and use the automatically generated schematics from the extracted SPICE netlists with RC network
  • Full chip netlist tracing (top level integration and block level)

EDA Tools
The German-based engineers from Concept Engineering have a range of tools to help you analyze and debug your IC designs:

  • Transistor-level debugging
  • Gate-level debugging
  • RTL-level debugging
  • Mixed-signal debugging (Transistor, Gate and RTL)

Further Reading

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Dan Niles Economic Review: Q1 is the Bottom

Dan Niles Economic Review: Q1 is the Bottom
by Paul McLellan on 03-29-2013 at 7:38 pm
Categories: Global Semiconductor Alliance, Semiconductor Services

Every quarter GSA runs a webinar with Dan Niles of Alpha One Capital Partners on what the semiconductor outlook is. He doesn’t actually focus on the semiconductor industry itself, demand for chips is really driven by economic conditions in the major markets around the world. People who are unemployed, or in Cyprus, don’t buy so many chips as people in booming economies.

I actually think that some micro-techy things are important too. Windows 8 is not receiving rave acceptance either in the home or business markets. But iPad (and similar tablets) are exploding. I admit that when I heard about the iPad announcement I was “meh” and figured I’d never want one. After all I have a smartphone and a laptop already. But I was completely wrong (along with most of the punditry). I did do better than many on predicting that x86 compatibility in the sub-notebook market would not be an issue and whatever-they-were would turn out to be more like an overgrown phone than a shrunk PC. Here is what I wrote in 2009, back when MID stood for “Mobile Internet Device” because we weren’t sure what they were yet:”My gut feel is that a MID will be more like a souped up smartphone than a dumbed down PC, and so Atom will lose to ARM. In fact I think the smartphone and MID markets will converge. Microsoft will lose unless they port to ARM. There will be no overall operating system winner (like with smartphones).”


So one of the big worries is that BRIC (Brazil, Russia, India, China) growth has slowed and Europe is in a recession with unemployment (especially among the young) ridiculously high in several countries including some large ones like Spain.


European debt levels are high, and due to problems with the Euro we hear about them a lot. But two other big markets, Japan and the US, actually have higher debt levels. The United States at 103% of GDP is not just higher than Europe, it is almost the same as the PIIGS, the sick countries (Portugal, Italy, Ireland, Greece and Spain) who are only at 104%. Japan at 230% is in a league of its own, and with fertility not that much above 1 child per female and essentially no immigration, they are on a “going out of business” trajectory.


Dan’s view is that in 2013 the semiconductor market will bottom out in Q1 and grow more strongly in the second half of the year. The biggest issue is probably deleveraging, reducing the amount of debt. There are two problems with this. Individuals in most countries are aggressively deleveraging and this means they are paying down debt rather than buying electronic goodies, new cars, new TVs etc. But government is still not delveraging, in general, they are going the opposite way.

But IT spend should outpace GDP growth, which is obviously good. And future customer interest looks good:

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Design Automation Conference: Go For It!

Design Automation Conference: Go For It!
by Paul McLellan on 03-29-2013 at 5:35 pm
Categories: EDA, Events

The conference program for DAC is now live here including the conference itself, keynotes, some other special tracks, the pavilion panels and more. And the must-see panel is on emulation at 4pm on Tuesday afternoon moderated by…well, that would be me so I’m a bit biased.

Registration is now open here for both attendees and exhibitors.

Hotel reservations are here (they have been live for some time).

As I’m sure you already know, DAC is in Austin for the first time this year. It is also the 50th DAC. There are many special events at DAC both looking back over the past 50 years and looking at the contribution of the Austin area to electronics. I’ll have a more detailed review nearer the time but for now, go and register.

And there is great Texas barbecue and more live music than you can imagine.

Bringing DAC to Austin
Major Employers of Design Engineers in Austin
 [TABLE] style=”width: 600px”
|-
| align=”left” valign=”top” |

  • 3M Co. (1000)
  • Advanced Micro Devices (2933)
  • Agere,Inc.
  • Alereon
  • Altera (50)
  • Analog Devices
  • Aperian
  • Apple (3000)
  • Applied Materials (2250)
  • Applied Micro
  • Applied Science Fiction
  • ARM (100)
  • ASI (Advanced System Integration)
  • BAE Systems (675)
  • Centaur (40)
  • Cirrus Logic
  • Cisco Systems (800)
  • Cypress
  • Dell (10,000)
  • DuPont Photomasks Inc.
  • Flextronics (1875)
  • Freescale Semiconductor (5000)
  • Hewlett-Packard (550)
  • IBM Corp. (6239)
  • Image Microsystems (500)

| align=”left” valign=”top” |

  • Intel Corp. (1000)
  • InterSil (40)
  • LSI (30)
  • Microsemi (40)
  • Motorola
  • National Instruments (2200)
  • Oracle (515)
  • Photronics
  • PulsewaveRF
  • Qualcomm
  • Rocket Chips
  • Samsung (1100)
  • SGI
  • Silicon Group Inc., The
  • Silicon Hills Design Inc.
  • Silicon Laboratories (500)
  • SMSC
  • Spansion (900)
  • Stellar Micro Devices
  • TI (100)
  • Tokyo Electron America Inc.
  • Vitesse Semiconductor
  • WindRiver Systems

|-

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA). Members of a diverse worldwide community from more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives, and researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.

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Mentor at TSMC Technology Symposium

Mentor at TSMC Technology Symposium
by glforte on 03-29-2013 at 11:41 am
Categories: EDA, Foundries, Siemens EDA, TSMC

TSMC will host their annual technology symposium at several locations in the U.S. on April 9th in San Jose, April 16th in Austin, and April 23rd in Boston. TSMC will discuss the market outlook, design enablement, and technology for high-speed computing, mobile communications, connectivity and storage, CIS, embedded flash, power ICs, and MEMS.

Mentor Graphics will host a booth at the conference where you can learn more about Mentor’s reference flows, and tools for IC physical design, verification, DFM, silicon testing and yield improvement. Experts will be available to discuss special topics such as advanced fill requirements, double patterning, design for reliability, cell-aware testing and IJTAG.

To learn more and register,click here.

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Signal integrity: more than just SerDes analysis

Signal integrity: more than just SerDes analysis
by Don Dingee on 03-29-2013 at 1:00 am
Categories: Cadence, EDA

When Cadence acquired Sigrity in 2012, two motives were involved: get more competitive in state of the art signal integrity analysis, and grab a foothold into the other vendor’s PCB flows in an area that is developing as a real sore spot for digital designers.

Just as the days where PCB tape-out meant actually using tape are over, so are the days where design teams can blithely make a gigantic ground plane, place parts around a board, and toss a few decoupling caps around until it feels good. Operational frequencies are routinely in the GHz range, with some interfaces at 10Gbps and rising. Margins are dropping as supply voltages get lower and lower in advanced process nodes.

The need goes even deeper now. FPGAs and SoCs, which on the one hand consolidate logic and simplify I/O routing, now need to be analyzed for possible rerouting pre-silicon to solve potential PCB layout issues. In even darker arts, IC packages are now significant contributors to signaling issues, and simplistic rules and fixes for electromagnetic interference (EMI) stop working with higher frequencies and reduced geometries involved.

There are many Sigrity tools now in the Cadence fold, and the functionality has been brought into the Cadence Allegro suite as add-ons, with tighter integration and more features on the way. One tool designers should look at very carefully is Sigrity PowerSI.

Most designers equate signal integrity analysis with high-speed SerDes designs, and are programmed to stare at eye patterns until blue in the face. Important, yes, but analyzing a SerDes is only one of many different signal integrity issues. Other issues that crop up frequently are simultaneous switching noise (SSN), coupling between geometries, power and ground bounce, and more. These are inherently dynamic issues that aren’t exposed in a DC analysis, and have to be looked at frequency domain to gain a complete understanding.

Sigrity PowerSI is not a magic wand that will cure all issues once given a set of constraints, but it is a tool that will guide designers into problematic areas of a design quickly before committing to board prototypes.

For instance, decoupling capacitors are always a fight between engineering and manufacturing, right? Too few and the design wobbles like a Weeble and isn’t stable enough to yield well in production test. Too many and people start complaining about overdesign and added material cost, even when there aren’t problems in production. Most designers set up rules like X caps per square inch, and bend those around higher current draw parts and difficult place/route packages. With Sigrity PowerSI, you know if you have too few, too many, or improperly placed decoupling caps, with quantitative results.

Designers can also model things like the processor to high speed memory interface, including connectors and packaging effects. For something like a DDR3 interface, the effects of various loading and bus frequency options can be evaluated, in frequency domain using S-parameter data extracted from the specifics of the layout.

More capability for analyzing distributed voltage and ground planes and EMI coupling between planes, traces, and vias exists in Sigrity PowerSI. IMO, the tool could potentially pay for itself in layer reduction, EMI testing, and production yield – plus helping designers visualize areas of a design that are working or problematic, removing the guess factor.

Is signal integrity as big a problem as we think in PCB design today? Have you used Sigrity PowerSI, and in what PCB flow? How does its capability compare to that of other tool sets for signal integrity analysis? What other problem areas need better analysis tools? Share your thoughts.

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TSMC on Collaboration: JIT Ecosystem Development

TSMC on Collaboration: JIT Ecosystem Development
by Paul McLellan on 03-27-2013 at 2:02 pm
Categories: EDA, Foundries, Synopsys, TSMC

Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry’s Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.

This doesn’t work any more. Since then each process generation has a major discontinuity:

  • 45nm: power must be addressed
  • 28nm: high-K metal gate
  • 20nm: double patterning
  • 16nm: FinFET
  • 10nm: multiple patterning and spacer

These discontinuities mean that foundries such as TSMC have to work closely with EDA suppliers such as Synopsys to ensure that the tools are ready when the process is ready. Otherwise they face the problem of building a $5B fab and not having any designs ready to run in it for a year. For example, without double patterning aware place & route, and layout editors, DRCs etc it is not possible to do a 20nm design.

This is happening in an environment where the number of tapeouts is not increasing, and is probably declining. But the number of wafers needed in production is increasing exponentially. This makes it critically important to hit the volume and yield-learning ramps for a new process. Wafers that are not manufactured don’t really come back, the end-user will have purchased another product. TSMC is increasing its capacity at a 31% CAGR. That’s a lot of wafer starts. Better make sure there are really wafers to start.

Another factor that has been growing in importance is the increasing use of IP in SoC designs. This means that not only do EDA tools need to be ready to go when the process is ready, but IP needs to be ready too. It is hard to do an SoC design without DDRx, PCIe, USB and so on.


So TSMC needs to have 3 parallel collaboration tracks:

  • working with EDA suppliers to ensure that the gotcha new features such as double patterning or FinFETs in the new process have full support in the tools
  • working with IP suppliers to ensure that IP is ready in a timely manner. It may not be possible to have all IP available when the process is ready, for both technical (IP suppliers need the tools and the process to be reasonably stable to get work done) and economic (there is a lot of IP and it can’t all be created in parallel
  • working with lead design groups to ensure that the process matches their needs, that they have the PDKs and design kits they require and so on

The goal is to have everything come together so that when the process is ready and the fab is ready to ramp to volume, that the designs are there. In turn that requires IP and tools to be there to get the designs done.


The next process, 16nm, is a FinFET process so the new challenges largely are around the transistors (the metal fabric is basically unchanged from 20nm). Although FinFETs are wonderful from some points of view (low leakage, high current, lower voltage) they have some disadvantages too (higher parasitic capacitance, higher parasitic resistance due to the MEOL local interconnect, quantized device widths). The biggest challenge has probably been RC extraction accuracy, although that seems to be as good with FinFET as at 28nm now.

The goal for future processes is:

  • around 2X increase in gate-density per node. With no EUV at 10nm this will get challenging
  • 15% speedup with 25% power reduction per node. This should be easier than the area reduction
  • And although Cliff didn’t mention it, another major challenge is to keep the cost per wafer in line so that the 2X increase in gate-density also shows up as a cost reduction

So collaboration within the TSMC Open Innovation Platform (OIP) is the only way to address these types of challenge and get everyone to the finish line at the same time.

And with that, Cliff Hou went to get on a plane back to Taiwan having only flown in yesterday!

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Apple and Google Turn Towards Enterprise

Apple and Google Turn Towards Enterprise
by Ed McKernan on 03-27-2013 at 9:00 am
Categories: Arm, Foundries, Intel Foundry

As a calm settles over the mobile market, post the overhyped Samsung Galaxy S4 launch, many analysts are at a loss as to describe a way forward with Apple that is understandable and positive. The dozens of reports that focus on the summer launches of the iPhone 5S and cheap iphone miss the side of the barn on the true strategy being put in place. Apple is at the center of solar system with Samsung, Intel, Google, Microsoft, Qualcomm, TSMC and others orbiting as partners and former partners turned competitors. The term Co-opetition does not survive in a market heading to 5BU while offering seemingly endless profits. For its next encore, Apple they say must innovate on the product side of the house. I see a realignment in their partnerships that could lead to a successful march through the unserved developing countries and more importantly the less competitive enterprise world.

It was Samsung who provided the low cost processors, DRAM, NAND and LCDs that vaulted the iPhone into volume and profitability as a USconsumer play. And it is Samsung, with the help of Google who has crushed the non-Amazon Android suppliers and seeks to commoditize Apple in an expensive CapEx end game. Apple has migrated all but the CPU to various suppliers with an emphasis on the Yen depreciating Japan Inc. Soon TSMC will free Apple, but not at a cost orperformance level that enables the outflanking of Samsung. A bulked up 14nm monster called Intel, sans Paul Otellini, is now ready to accept sub 40% margins in order to shrink the playing field by the time 10nm rolls around. Samsung is their #1 mortal enemy. Apple would concur and thus the reason to partner.

Apple’s plan to roll out a low cost iphone is a play on the middle 40% of the mobile market that contains the last 30% of the profits currently registering with Samsung. A squeeze play between Apple and China smartphone vendors is in the cards later this year. With Apple about to open up China Mobile, India and Japan’s DoCoMo, Samsung will lose their sole refuge in the other 3BU TAM. Every mobile vendor is dialing in 50% growth for 2013 for a market that is more like 30%. If history holds true, the bottom half of the market will be lucky to be breakeven as the rising tide creates a serious undertow driven by excess capacity.

Apple’s plan in the developing world would seem to point to growth but not too much growth. I expect a fortress wall to be built around what is initially not much more than 40% of the market or until the excesses are wrung out. In the near term, greater riches are to be had in the corporate PC market that is 90% Wintel and has so far hesitated to make a dramatic move until Window 8 had entered the fray. Legions of Microsoft and Intel sales folks call on CIOs regularly to sell the benefits of the latest O/S and x86 processors. Although the Apple MAC line uses both Intel and Microsoft Office, it has not been attractive enough to crack the market. Legacy is a long tail in the corporate world but the timing is right for Apple to adjust its partnerships in a Complex Divide and Conquer Strategy.

Since 2011, I have believed that Apple will end up in Intel’s Fabs for two reasons. One is based on the advanced, ultra low power Trigate Process technology combined with the massive capacity build out. Intel’s $13B capex in 2013 is a bet that either Apple or Qualcomm is coming. The second reason is the belief that they would be far better off promoting their products into corporate if Intel was at their side and not as a roadblock and dishing out FUD. Analysts and the press have assumed Intel will never build an ARM based processor. This is foolish, Intel may never develop anything but x86, however, the 5BU mobile market demands that fabs be filled or risk losing the long war. ARM be damned, fill the fabs.

If Apple builds its A7 at Intel, they can be guaranteed the highest performing, lowest power and lowest cost processor for its smartphones and tablets. Apple will leverage this into higher end iPADs and iPADs in MAC Air formfactors that run a multitasking iOS. Then the pitch will be made that Apple offers the broadest product line that corporations can buy without the >$100 Microsoft O/S tax. Intel will play a two handed strategy of supporting Wintel tablets as well as the Apple iPADs based on A7 silicon coming off the 14nm lines. The strategy offers the opportunity to crush the non-Apple based ARM market before it gains speed. Perhaps Qualcomm will feel it necessary to partner with the Intel Foundry.

In Intel’s long-term game plan, TSMC and Samsung need to be lowered. Google can be a potential partner, but only if they center their future O/S, application and cloud ecosystem around x86 processors. Google’s announcement of Andy Rubin stepping down as head of Android appears to be a sign that the company has lost control of the Android mobile market to Samsung with little in the way of compensation. In comparison, iOS is a profit center, though at risk of being displaced. Look for a refocusing in the enterprise space as a better bet for growth.

In the near term, analysts will be concerned that the Intel margin model that includes servicing Apple’s ARM chips is a threat to the long term viability. However, in reality Intel is trying to build a parallel vertical silicon supply model that is more extensive and profitable than what Samsung can offer today because it will not only include cheap ARM mobile processors and baseband chips but also the legacy x86 PC processors all the way to $4,000 Xeon Server chips for the cloud build out that Apple, Google, Amazon, Microsoft and others will rely on to proliferate their ecosystems. A new metric of server chips per mobile devices will be devised to monitor Intel’s health.

In two to three years we may look back at today and understand that the mobile market endured a small blip that in reality was a quick transition from feature phones to smart phones with only a very small percentage actually leveraging the cloud. The $50 white box internet phone and cheap tablets that are widely available in China are being driven by an excess of chips built on n-1 process based chips and older versions of Android, thus leading analysts to focus on the commoditization downside driven by Moore’s Law and not on the productivity enhancement upsides that are soon to be driven with the Cloud. And this is why an Enterprise push makes the most sense.

Full Disclosure: I am Long AAPL, INTC, ALTR, QCOM