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Mary Meeker’s Annual Internet Trends is Out

Mary Meeker’s Annual Internet Trends is Out
by Paul McLellan on 04-23-2013 at 8:05 pm
Categories: General

Every year, analyst Mary Meeker produces a large presentation (88 slides this year) about internet trends. This year’s oneis just out. So much of the semiconductor industry is driven by trends in mobile and PCs. Increasingly, just by mobile since it has already overtaken PCs in terms of units and will soon overtake in terms of semiconductor content. I covered last year’s presentation here.


In the graph below, the orange and blue bars are the PC (desktop and notebook) and the green and yellow bars are smartphones and tablets. Q4 2010 was the inflection point when mobile device shipments surpassed PC shipments and you can see the enormous growth out into the future.

The middle part of the presentation is about how the internet is disrupting various businesses from the obvious ones (payment: square, paypal; hotels: airbnb, couchsurfing; taxis: uber etc) to many I haven’t heard of.

She ends with some cautionary notes. “Lots to be excited in tech, lots to be worried about in other areas.”

Two big ones. First student loans:

Second, general US government spending, which is at the biggest gap above revenue since the middle of the first and second world wars.

Mary Meeker is a general partner at Kleiner Perkins Caufield & Byers and joined the firm in January 2011. She focuses on investments in the firm’s digital practice and helps lead KPCB’s Digital Growth Fund, targeting high-growth Internet companies that have achieved rapid adoption and scale. Mary serves on the boards of Square, Lending Club, DocuSign and Quirky and is also actively involved in KPCB’s investments in Twitter, LegalZoom, Spotify, 360buy.com, Waze, Jawbone, SoundCloud and Affectiva.

A prolific writer, Mary is the co-author of the industry-defining books The Internet Report (1995) and The Internet Advertising Report (1996). She is also the co-author of The Internet Retailing Report (1997), The Online Classified Advertising Report: It’s About Search/Find/Obtain (SFO) (2002), The China Internet Report (2004), The Mobile Internet Report (2009), and The Technology IPO Yearbooks. Beyond technology, Mary (and Liang Wu) created USA, Inc. (2011), an award winning, non-partisan report / video that looks at the U.S. government (and its financials) from a business perspective. Mary’s reports (including her annual Internet Trends presentations) are widely read around the world.

Once again, this year’s presentation is here.

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Mentor Graphics’ Best User2User Ever

Mentor Graphics’ Best User2User Ever
by Beth Martin on 04-23-2013 at 5:45 pm
Categories: EDA, Siemens EDA

Calling all Mentor users! Don’t forget to register for the U2U in San Jose on Thursday, April 25.

In addition to three worthy keynotes, you will find a more interactive and solution-focused day than in the past. There are sessions on place & route, custom/AMS, emulation, test and yield analysis, functional verification, Calibre signoff, and PCB. You will have time enough between sessions to ask questions and get answers from the veritable army of Mentor technical experts who will be available. These technical experts will be armed with lots of product demos. If you’d like a preview of some very useful ‘how-to’ demos, check out this collection of short videosthat show how to do specific tasks in several Calibre tools.

The first presentations after the morning keynotes are product roadmap updates from Mentor. After the lunchtime keynote by Dr. Chenming Hu, father of FinFETs, the sessions are mostly case studies from other Mentor users. The whole schedule is available here.

As always, the event is free and includes lunch and a happy hour. I’ll be there, learning and mingling. If you see me, tell me what you found useful, surprising, or interesting!

Register for the Mentor User2User meeting here.

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Forte Rises

Forte Rises
by Randy Smith on 04-23-2013 at 3:00 am
Categories: EDA

Over the past few months there has been a bit of back-and-forth concerning the 2012 market data indicating that Forte Designs Systems had taken over the top spot (by revenue) in the high-level synthesis (HLS) market (see stories hereand here). Having worked in this segment for Synfora as VP of Marketing, and as a consultant to AutoESL, I feel I know this segment well enough to take a deeper dive.

If we go back only five years, Mentor’s Catapult-C was the clear market leader in the high-level synthesis market. My own market research (a privately sold report sent to two vendors in 2009) had them at nearly half the market (by revenue) at that time. What was less clear, was the split of revenue for Mentor between ASIC and FPGA designers in this market. At that time other market participants included Forte, Synfora, Bluespec, Impulse C, Cadence, and AutoESL. A crowded market indeed, and my projected growth rate at that time for the segment was a healthy 19% per year.

My how that market segment has changed! In August 2011, Mentor sold Catapult C to Calypto, reportedly in exchange for a large piece of equity of Calypto (perhaps controlling interest, per multiple sources). If Mentor was so committed to ESL did this make sense? Others pointed to a perceived need for Mentor to somewhat exit the HLS market in order to be more vendor-neutral in adjacent markets. That is not a move Synopsys or Cadence would ever make, but Mentor does play more product-centric than the other major vendors who are more interested in a complete front-to-back flow. In any event, it created an opportunity for others.

AutoESL was a fast rising star in the HLS segment, at least at the technology level. Xilinx snapped themup at a hefty premium a bit more than 2 years ago. This was a smart move for Xilinx, but it also effectively diverted the AutoPilot product team to focus on the FPGA market rather than the ASIC market. It was a very different scenario when Synopsys acquired the assets of Synfora in June of 2010. Synfora had been struggling for a long time and Synopsys acquired the assets for very little. In fact, the Synfora CTO/Founder, Vinod Kathail, whom I have a tremendous amount of respect for, ended up at Xilinx, not at Synopsys.

Now, fast forward to 2013 and we have a new HLS market leader, Forte Design Systems. Forte’s HLS revenue now exceeds Mentor/Calypto’s. Synopsys, as expected, has earned little revenue from its Synfora acquisition. Cadence’s internally developed HLS tool has received little market traction, just like most tools developed rather than acquired by the major EDA companies. However, it appears that Cadence was doing better than first thought as they have recently indicated that they mistakenly had failed to report HLS revenues to analysts. One thing is abundantly clear, no one is growing as quickly in the ASIC HLS segment as Forte.

Forte has been focused on HLS for ASIC design since its inception. This focus has contributed to seven consecutive years of increasing revenue. Significantly, Forte has had several close Japanese customers for many years. In its most explosive growth years, Cadence had paid partnerships with as many as five Japanese semiconductor companies at a time. The management style of Japanese companies leads to iterative improvement in their suppliers offerings. But this benefit is only gained if the relationships are effectively managed, and Forte has clearly done that. Forte KK will celebrate its tenth anniversary next year, a strong testament of its commitment to its Japanese customers. Forte continues to add new customers worldwide as well.

Is it possible that Calpyto’s figures are understated due to the way it recognizes revenue compared to how Mentor recognized revenue? Perhaps. We simply will not know until 2013, or maybe even 2014, figures are reported. I would not expect Mentor to open its books for this type of analysis. I also have not seen the details of the transaction between Mentor and Calypto. Did Mentor really take all the revenue and cash for multiyear deals for itself and dump the support costs of that on Calypto without paying for it? If they would have paid for it, then wouldn’t that be in Calypto’s revenue now already? There are many factors to this and we are just not going to get to see them all to analyze this thoroughly.

Two conclusions are clear: (1) Based on reported 2012 revenue, Forte is the current market leader in High-Level Synthesis; and (2) Forte is the fastest growing company in this segment as well. The second part of this bears repeating. Forte grew faster than Calypto in this segment in 2012, after having done so in 2011 as well. Forte has a mature product offering, and it is building strong momentum. HLS will become more mainstream as we inevitably create designs with more content. Forte is beginning to emerge as one of the most prominent private EDA companies, and the leader in their market segment. The stage is set for a fun year to watch the High-Level Synthesis market.

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FinFET Day Presentations at EDPS Monterey!

FinFET Day Presentations at EDPS Monterey!
by Daniel Nenni on 04-22-2013 at 10:00 am
Categories: EDA, Events

If you are ever asked to organize a conference session do not hesitate, accept immediately and jump right in. When John Swan, EDPS General Chair, asked me to organize a day I hesitated. Fortunately he is not one to take no for an answer. It was an unforgettable experience on many levels and I hope to be involved with EDPS again next year. Yes it was that good.

First the location, Monetery is absolutely the best place for a conference. The hotel was right on the beach with the most amazing views. The weather was excellent, the hotel food was excellent, it was one of the most relaxing and informative weekends I have had in a long time. I have always pushed for more convenient conference locations to get the highest attendance but I was wrong. Quality over quantity, location, location, location and Monterey is a great place.

Picking the topic and presenters for a conference should probably be a stressful thing but it was what I enjoyed the most. FinFET was the most written about subject and top trending search term on SemiWiki in 2012 so that was easy. The presenters were people I know and respect so that was also easy. Organizing and coordinating the day took much more time than I had imagined but it was well worth the effort.

Here’s how the day played out:

I did a quick 15 minute keynote to set the day up with my FinFET experiences and SemiWiki analytics. My good friend Tom Dillinger finished the keynote with a Primer on FinFETswhich was a perfect set-up for the rest of the day. Tom has been a great technical back-up on FinFETs including the FinFET Wikion SemiWiki. Tom is also a great speaker, the author of VSLI Engineering circa 1987, and an expert in this field.

After the break Tom did his presentation on FinFET parasitics, which as it turns out, is one of the biggest challenges facing FinFET designers today and tomorrow. Thank you Tom, you hit this one out of the park.

Next up was Rob Aitken. I first met Rob at Artisan many years ago and he is now an R&D Fellow at ARM. Rob presented FinFET SoC Design Challenges which included a Silicon Device Roadmap down to .35nm which may not have any actual silicon content. What!?!?!?!?!

Next up was Raymond Leung. I first met Raymond when he was VP of Engineering at Virage Logic. We met up again when he was VP of Memory Development at UMC and now he is VP of Engineering at Synopsys. Raymond presented on FinFETs and SRAM Design. Since SRAMs are the pipe cleaners for new semiconductor processes and Synopsys is the top SRAM provider, Raymond has seen the most 16/14nm silicon thus far. He presented FinFET design challenges in great detail and who would know better than Raymond.

Tom Quan finished the session with FinFET Design Ecosystem Challenges and Solutions. Tom is a great presenter and clearly distinguishes between marketing and silicon correlated data. According to Tom the value proposition of FinFETs versus Planar at 20nm is up to 20% performance at the same power consumption, 35% savings in power at the same speed, and 1.1X density. Those my friends are great numbers!

As I mentioned before, FinFETs are the most interesting technology we will see this decade so it was a day well spent. My wife and I stayed on an extra day to enjoy Monterey, which was where we spent our second wedding anniversary many years ago.

Please post your EDPS 2013 Monterey questions, comments, and trip reports HERE!

EVENT PRESENTATIONS

EVENT PICTURES

lang: en_US

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Happy Birthday to Synopsys VIP

Happy Birthday to Synopsys VIP
by Paul McLellan on 04-22-2013 at 3:25 am
Categories: IP, Synopsys

I met Mike Sanie around DVCon time and planned to write a blog about the one year anniversary of Synopsys Discovery VIP which was announced during Aart’s keynote at DVCon in 2012. Eric covered it for SemiWiki here. But Synopsys had other stuff they wanted me to blog about and so it is a couple of months late. The 14th month anniversary isn’t quite so compelling and anniversary.

At DVCon this year they actually had a VIP anniversary party, with Don McMillan (who I knew back when used to be a designer at VLSI Technology back before he became a full-time comedian) and Scott Meltzer and Katrine (and my claim to fame there is that I was the first person to hire Scott for DAC when I was at VaST; he has a degree in computer science from Berkeley before/during he became a full-time performer, so he could actually run the demos himself).

Synopsys created their VIP portfolio since their previous generation was running out of steam and wasn’t written to any sort of uniform standards and so had challenges with performance, debug and coverage. The new generation was all written in SystemVerilog with native-compiled (no wrappers) UVM/VMM/OVM and is much higher performance, 3-6X faster than the old stuff.

There was additional innovation in protocol-aware debug and coverage which I wrote about last year here when it was integrated with SpringSoft’s Verdi. Of course since then, Synopsys acquired SpringSoft.


The release was generally received by both the press (Eric’s blog is very positive, for example) and the verification experts in customer companies. This has resulted in several technical wins at major accounts against entrenched competition. There are lots of press releases announcing some of these on the Synopsys website if you are into that sort of thing. Personally, I’m not. I’ve been in marketing and know how to turn the meat-grinder handle to get quotes to come out the other end and so I pretty much ignore most of any press release other than the basic facts of the announcement. But AMD, Cavium, Freescale, Qualcomm, Broadcom and more are using it.

It is now 14 months later and with a broad portfolio of verification IP this is one of the (if not ‘the’) fastest growing product lines in Synopsys.

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Mentor’s New Embedded Strategy

Mentor’s New Embedded Strategy
by Paul McLellan on 04-22-2013 at 2:01 am
Categories: EDA, Siemens EDA

If there is a trend I can detect in verification in 2013, it is taking verification environments and making the user interface, scripts, and tools work uniformly across the whole spectrum of possible verification “substrates” from virtual platforms, FPGA boards, emulation, actual chips, RTL simulation and so on. Mentor is taking this basic idea up another level to the embedded software developer. Today they have announced the Mentor Embedded Sourcery CodeBench Virtual Edition (try saying that 3 times after a few beers).

Mentor acquired Code Sourcery in 2010, a major player in open-source software development and supplier of the most popular software development environment (or IDE, the I stands for ‘integrated’) used inside major semiconductor companies by their software engineers. It is downloaded 15,000 times a month. It is free, so Mentor doesn’t make any money directly from that.


What Mentor have done is made it so that software engineers can use the CodeBench that they are used to using. But under the hood, they can actually be running on a QEMU-based virtual platform, or on one of Mentors Veloce emulators, or on an FPGA prototype, or on the real silicon, or on a reference design board. RTL is far too slow for software development, but for all I know that might work too.

From the software engineers point of view, all the details of the hardware such as RTL or signal traces, are hidden and he or she only needs to worry about software-like stuff. If a problem is detected that might be a hardware issue, the design engineer can pick up signal traces and dig down into the details without requiring understanding all the software or how to work inside CodeBench.

The basic idea is to give the software engineer just enough information from the hardware that they can get their job done and not have to worry about the hardware or learn lots of alien stuff. And similarly, for the hardware engineer, to let them work in their environments without needing to become an expert on the embedded software environment or code.

I worked for VLSI Technology for years and I like to say that I have silicon in my veins, although by background I’m a programmer. But when I worked at VaST and Virtutech I started to see things from the embedded software developers point of view. For instance, I was at a Cisco supplier conference and the CTO spoke at a keynote. IOS, Cisco’s router operating system, is 25M lines of code and another 30M lines of code to test it (I suppose what we’d call VIP in EDA). The developers of that code neither know nor care what SystemC is, or how you synthesize a chip. It is just a big register map to them. When I did a computer science degree in a galaxy far far away I actually learned some hardware design. Nowadays, I don’t think they teach that stuff. They probably don’t even teach assembly code. If you can do C++, Java and Python you are good. The point I’m making is that the abstraction level the software people work on is so far removed from what the hardware people are doing that it is hard to communicate.


This looks very good to me. Not in the sense that it is rocket science breakthrough technology. But it addresses the social aspects of software/hardware co-design and doesn’t take as a fundamental assumption that the software developers and the hardware developers are in adjacent cubes and speak a common language. Especially, it doesn’t assume that taking hardware design tools and interfacing them to some software environment with a “software engineer” skin is going to work.

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A Brief History of Methodics

A Brief History of Methodics
by Daniel Nenni on 04-21-2013 at 8:15 pm
Categories: EDA, Perforce

Methodics was founded in 2006 by 2 ex-Cadence experts in the Custom IC design tools space, Simon Butler and Fergus Slorach. They had a consulting company called IC Methods, active in Silicon Valley from 2000-2006, and when they needed to create a new company to service a consulting engagement that had turned into a product, they inverted the name and Methodics was born!


Simon Butler, CEO…..Fergus Slorach, CTO

Goals
The original goal was to provide DM interfaces to the Cadence design tools suite to allow the more liberal use of software methodologies in a hardware design environment. Software developers have traditionally been more sophisticated in areas like data management. There are orders of magnitude more users on tools like Subversion, Perforce, Git and others. By building on top of these industry standard solutions Methodics can leverage the much larger software developer space with all the associated benefits of scalability and an extended ecosystem.

First Customer
The first customer was Netlogic Microsystems. Methodics provided Perforce/Cadence data management for 6 design centers across the US and India.

Markets
The markets for IC data management tools are growing – Custom IC design is seeing some major growth with the popularity of smart phones. SoC’s in general are becoming more complex and require better management processes to scale.

The alternative to using data management tools are making manual design copies and manually assembling SoC’s, however these approaches don’t really scale and are not practical with todays designs

Products
Today Methodics has 3 main areas of development. Design data management tools for layout and schematic designers, SoC IP management and IP reuse/integration, and RTL design data management, test/regression and release management

VersIC™ – Design Data Management for layout/schematic designers. VersIC was the first Methodics product and integrates Subversion or Perforce in the Cadence Virtuoso and Synopsys Custom Designer tools-suites. VersIC allows a user to version control their data from within the design environment without any required knowledge of the underlying DM tools. Multi-site teams are supported using the underlying proxy mechanisms available in Subversion/Perforce which yield fast, scaleable data distribution for large IC project data-sets.


Fig.1 VersIC overview

ProjectIC™ – SoC/IP management for designers and integrators. ProjectIC is an enterprise solution for releasing IP’s and cataloging them for reuse, SoC integration, tracking bugs across IP’s and managing permissions. ProjectIC also allows comprehensive auditing of IP usage and user workspaces. With ProjectIC managers can assemble configurations of qualified releases as part of the larger SoC and make this available for designers to build their workspaces. Workspace management is a key technology within ProjectIC and data is populated in minimal time using IP caching and parallel syncs.

Fig.2 ProjectIC Overview

Evolve™ – RTL test, regression and release management. In 2012 Methodics acquired Missing Link Tools, the developers of Evolve – a test/regressions and release management tool focused on the digital space. Evolve supports Subversion, Perforce and CVS DM systems with a Evolve tracks the entire design test history and provides audit capabilities on what tests were run, when and by whom. These are associated with DM releases and provide a way to gate releases based on the required quality for that point in the designs schedule.

Fig.3 Evolve Overview


With these 3 established areas of technology Methodics is uniquely placed to deliver the industries first complete solution for analog/digital design.

Tool Users

IC layout and schematic designers can use the standalone VersIC tool. IP designers, SoC integrators and project managers would use ProjectIC, finally digital designers would use Evolve.

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ISCUG – Excellent Indian Conference, needs to grow

ISCUG – Excellent Indian Conference, needs to grow
by Pawan Fangaria on 04-21-2013 at 8:05 pm
Categories: EDA, Events

Promoted by Accellera, SystemC User Groups are in work worldwide; NASCUGin North America, ESCUGin Europe and ISCUG in India. While I was shuffling between my day-to-day work and strategy management course/exams, I received an invitation from my long time colleague, President and CEO of Circuitsutra Technologies, Mr. Umesh Sisodia to attend the ISCUGconference on 14[SUP]th[/SUP] and 15[SUP]th[/SUP] April. I was delighted as I found the conference quite interesting, enhancing my knowledge and knowing about some good work being done in this part of the world. Also there were important messages about SystemC initiative, related technologies and about progress in semiconductor and electronics industry in this developing country.

Umesh Sisodia
First day was filled with several tutorials on SystemC, TLM, HLS, SystemC based verification, advanced modelling and the like. I could not attend all, but tried to gain insight from these as much as I could by switching between these sessions; can talk about a few some other times when my schedule allows. An important meeting of ISCUG steering committee was scheduled in the evening, in which again Umesh invited me, my pleasure! I will talk about the message from that meeting at the end of this article.

Dennis Brophy
So coming into the 2[SUP]nd[/SUP] day, in the morning we had keynote speeches from Industry leaders which were eye openers. Right after the introduction & background about ISCUG by Saurabh Tiwari from Technical Review Committee, Dennis Brophy, Vice Chairman, Accellera Systems Initiative and Director of Strategic Business Development at Mentor gave a very nice presentation about various activities Accellera is supporting and promoting; from formation of SystemC user groups in different parts of the geography to various working groups such as Language WG, Synthesis WG, Verification WG, TLM WG, SystemRDL WG, CCI (Configuration, Control and Inspection) WG, the latest being SystemC AMS WG and Multi-language WG and various subcommittees. There is open invitation for experts to join these working groups and strengthen the standards around SystemC for greater productivity, performance and interoperability of the systems built with these. It was a great informative speech.

Jaswinder Ahuja
Jaswinder Ahuja, Founder Member of IESA(formerly India Semiconductor Association) and Corporate VP & Managing Director at Cadence presented a detailed update about the rapid developments in semiconductor space and electronics in general in India. A key eye popping message was that the overall electronics market in India will grow to $400B by 2020. That’s amazing news! Another message was the great demographic dividend India has in terms of young population. Here I am a little disappointed and purposely I have omitted ‘working’ from population. Employment has been a major objective since 2[SUP]nd[/SUP] five year plan of India after its independence and has been repeated in most of the subsequent plans. Still major portions of Indian population do not have meaningful employment. In my opinion, demographic dividend can be obtained only if the young population is educated and vocationally trained and more than 90% are employed. Government, business institutions and people need to work together to achieve this.

Sri Chandra
Sri Chandra, Standards Manager at IEEEprovided update about India IEEE activities to promote technical education activities among professionals and students. The community is growing with local chapters in cities like Delhi, Bangalore, Hyderabad etc. IEEE standards and publications are there in most of the areas and that greatly helps in growing the knowledge and skills.

Mike Meredith
Mike Meredith, Past President of OSCI (Open SystemC Initiative) and now Vice Chairman of Accellera Synthesis WG and Technical Marketing VP at Forte talked at length about SystemC from its origin, various developments, how it helps the SoC design community and the future insight. It was interesting to note that SystemC came into existence in 1999-2000 and is evolving since then into multiple applications as is evident from various working groups around it. I am willing to talk about it in detail in a separate article.

At the end of the keynote lectures, Umesh Sisodia, Organizing Committee Chairman talked about future roadmap of ISCUG. This is where; a summary of what was discussed on the previous day evening in the steering committee meeting was disclosed. Although the conference is being attended by world class people (130 people attended this conference) and specialized focus is given to SystemC and which should be considering SystemC’s versatility as well as exclusiveness, there was a need felt to increase participation in this conference in order to make it more outreaching and economically viable. More sponsorship is needed and a non-profit organization needs to be formed to support it. So, how can it be done? More ideas are welcome, but a few of them are – open it up to wider areas, even associate it IEEE, Embedded Systems Conference and so on. Another idea was to start DVCon India which can include all standards of Accellera and not just SystemC. In that case SystemC must be co-located event along with DVCon India such that it retains its exclusivity as it is attended and used by involved and dedicated experts.

So what do you think? Considering the growth potential in India as elucidated in Jaswinder’s presentation, shouldn’t the ISCUG conference expand and build its brand?

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FPGA + MATLAB = FATLAB

FPGA + MATLAB = FATLAB
by Luke Miller on 04-21-2013 at 7:00 pm
Categories: FPGA, Xilinx

Now Michael Bloomberg probably wouldn’t want FATLAB but let’s face it, to think like him you need a lot of education, alot. He may be banning 14nm because it will increase FPGAs densities and thus the consumer as well. Stay tuned. After some comments from my dear readers, one who said to watch it with respect to my harshness about AccelDSP; I needed to address this issue immediately. I actually woke up with a Virtex-II in my bed missing some pins. Yes, this is serious.


The idea behind AccelDSP was good. As a system developer, like the rest of the world, I use MATLAB or Octave. (Now don’t tell anyone about the Octave, as I’m frugal and wise, but not cheap!) MATLAB is the best systems modeling tool, period. Rhapsody, SysML, UML and the likes to model some grandiose system is never going to replace MATLAB and frankly it is another thing to do on the ever growing design checklist. The disconnect as you know is how to get that great system you have modeled in MATLAB into silicon, in particular an FPGA. Well AccelDSP tried doing that but had limitations. For me the big limitation is the one that it needed to work. You know click that magic button and bingo VHDL. True it would work for a FIR filter but for larger more nested loop structures, no worky. No floating point either and I like floating point, who doesn’t? I also enjoyed the tool hanging up for hours on end, then just going away. It had a way of making me feel productive and of course I would just sit and stare at the screen until it finished. The other issue was cost; it was like a billion dollars. ($100k+)

My earlier article about HLS being Real is true but there is still a disconnect from the modeling realm into the Silicon. MATLAB does have C Coder, which takes your MATLAB and converts to C and then Vivado HLS can work on that. I have used that path and it works but it is not ideal for obvious reasons. The major one is the penalty for abstracting a level higher. So can I make a plea with the FPGA companies? Would you consider partnering with MATLAB (besides Simulink, I know all about that, and that is not the solution either) or maybe buying MATLAB?

Every DSP house, Medical, RADAR, Automotive, Wall Street etc… USE MATLAB. I’ll share a secret with you. I cast my C from MATLAB by hand. I know, you’re saying how inefficient, how error prone Luke! What are you thinking? I know, it’s terrible and I am ashamed.If we think about it, system engineers model the design and flow down / partition the requirements to hardware (FPGAs) and software (CPU). The Modeling tool is MATLAB (Have I said that enough?). It would be orders of magnitude more efficient to flow down the model to the FPGA guys to work the ‘FATLAB’ tool instead of writing the VHDL by hand. One thing is true; the idea that we are going to hand code a 6.8 Billion transistor FPGA is totally absurd. Try it and your competition is going to blow your doors off using HLS.

But FPGAs have inherent frustrations on the programming language. CPU’s have C; FPGAs well now have C, C++, SystemC, Verilog, VHDL, (Zync) EDKs, etc… And now I want a MATLAB HLS, Again? Perhaps the group is smaller than I think but the programming of the FPGAs cannot be bird shot and MATLAB is where most start; why not leverage that correctly to synthesize, again? Ok, time to dust of AccelDSP and create FATLAB? If it existed, most I know would use it and would probably pay for it, I know I would.

lang: en_US

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A bird told me the EDPS Monterey Conference was a great success

A bird told me the EDPS Monterey Conference was a great success
by Camille Kokozaki on 04-20-2013 at 8:10 pm
Categories: EDA, Events

The 20th annual Electronic Design Process Symposium (EDPS) held April 18-19 at the Monterey Beach Hotel in Monterey California was an unqualified success. I know this because a bird (seagull?) sitting on the window sill of the conference room was so captivated by the fascinating insight provided by a number of luminaries that it joined in the conversation and could not wait to tweet about it. OK, you know I am making up stories here but the truth is that it was a great conference full of technical content, lively debate, deep dives, great perspectives, geeky humor, clever one-liners and wonderful settings. I was there and I must admit I enjoyed the event a great deal.

The event program consisted of five modules as follows:

  • ESL & Platform
  • Design Collaboration
  • 3D–IC System Design
  • FinFET: Design Challenges
  • FinFET: Foundry Design Enablement Challenges

The last 2 modules occurred on the 19th, a day designated as Foundry Day: FinFET Design Enablement. The first day opening keynote was given by Ivo Bolsens, Xilinx CTO and was entitled: “The All Programmable SoC – at the Heart of Next-Generation Embedded Systems”. Gary Smith, of Gary Smith EDA delivered a dinner keynote entitled: “Silicon Platforms + Virtual Platforms = An explosion in SoC design” and Semiwiki’s Daniel Nenni had a keynote on Foundry Day entitled “The FinFET Value Proposition”. Three panels were held those 2 days as well.

The sheer number of content calls for a multi-part series of posts to follow this one describing the insight and interaction of the sessions. In this post, I will only summarize Ivo Bolsens’ presentationand its key takeaways. All the event presentations are posted here.

Ivo made the case for the new FPGA age of All-Programmable SoC. He outlined the unstoppable march down the technology curve with a pipeline of ever shrinking technology nodes from 32/28nm to 5nm where novel materials and esoteric technologies will kick in at the end of this pipeline. This lead to highlighting the ever increasing cost of implementing chip design as process nodes shrink, reaching more than $170M in 28nm. He showed an interesting Infographic slide entitled “What Happens in an Internet Minute?” depicting the staggering data growth.

An interesting factoid was that Google changes/refreshes data centers every 2 years. Facebook does that every 8 months. The Data Center is integral to business success now and is no longer viewed as a cost center.
Security is more important. People these days talk more about latency than server capacity.

We have reached the age of All Programmable in One. Zynq’s programmable I/Os, logic, CPUs, with different granularity allowing you to tailor your application to what you need. FPGAs and CPUs have grown much closer. FPGA was a slave to the CPU, now the new FPGA is more of a peer. FPGAs can now program a function, like FPGA at CPU bus, but right on the CPU bus, not further away.

Ivo added that we are moving from dumb pipes to smart networks. The wired infrastructure is evolving to software defined networks. The Data Center infrastructure is moving to the cloud. Ivo also discussed Vivado IP integrator , and Zynq in wireless digital front-end.

Ivo’s take-aways were that the FPGA is Entering the Era of the All Programmable SoC:

  • Modern FPGA is an All Programmable SoC
  • Software Centric Design Flow
  • Unmatched Performance/Watt
  • Towards Heterogeneous Multi-Core
  • Targeted Teaching Platform

I could not agree more. In fact I see us soon talking about All Programmable SoS (System of Systems), software defined, hardware realized with programmable everything: CPU, GPU, FPGA, Memory, I/Os. If the SoS term takes off, you heard it here first. If not, you heard it here last..

Fair disclosure: All transcription errors are mine, I was part of the EDPS organizing committee, and I was a presenter.

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