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5 Rules of Power Management Using NoCs

5 Rules of Power Management Using NoCs
by Paul McLellan on 11-18-2013 at 4:30 pm
Categories: IP, Sonics

If it has escaped your notice that power management on SoCs is important then you need to get out more. Increasingly, the complexity of the interconnect between the various processors, memories, offload processors, devices, interfaces and other blocks means that the best way to implement it is to use a network on chip (NoC). But without using the NoC optimally, the power dissipated will be much higher than it need to be. The NoC has a level of intelligence within itself, and this can be used, for example, to aggressively power down blocks safe in the knowledge that the NoC will never attempt to deliver data to a sleeping block without waking it.

So here are the five rules of power management using NoCs:

Rule 1: The NoC must be fast.

  • A well designed network that is also very fast allows the synthesis tool to use high V[SUB]t[/SUB] transistors. Designs with a high percentage of high V[SUB]t[/SUB] transistors can achieve reductions of as much as 75% leakage power compared to the faster but leakier low V[SUB]t[/SUB]
  • A fast NoC means that the synthesis constraints are less tight and so fewer and smaller buffers are required inside blocks resulting in further power saving

Rule 2: The NoC must support both coarse-grain and fine-grain clock gating

  • Careful clock gating that is architected into the design will produce a much better result than simply relying on the synthesis tools. Results that clock gate more than 99.9% of the design can be achieved.
  • Coarse grained clock gating gates entire branches of the clock tree, saving not just the energy suppressed in the unclocked flops but the power needed to drive the clock network itself. When the clock network can consume up to 30% of the power on a chip, this can lead to big savings.

Rule 3: The NoC must allow clock and power “domain boundaries” within the NoC

  • Different clocks for different parts of the network.
  • Different voltage supplies for different parts of the network.
  • Portions of the network that can be idled or even powered off.
  • Sensibly group blocks that are on the same clocks and power to minimize components required on each domain crossing (and the CDC checks required)

Rule 4: The NoC must be aware of the power state of network components.

  • Catch traffic early that accesses powered down parts of the SoC.
  • Allows network interfaces to tell the power manager when it is safe to remove power from a block.
  • Two alternatives are available when a transaction is received for a component in the system that is powered off: a) reject the traffic (preferably at the source) or b) signal the system power manager that a power domain must be powered up.

Rule 5: Integrate auto-wake-up features into NoC.

  • Network requests wake-up of necessary power domains, without software intervention.
  • The alternative to rejecting the traffic is to use a high performance Wake-on-Demand system that can operate without SW intervention. Many SoCs have SW controlled system power management schemes that suffer from high latency. A HW based Wake-on-Demand mechanism operates in a few clock cycles and allows the initiator agent to signal for a wake-up and hold the transaction until it can be completed.


Following these rules means that the power can be significantly reduced compared to using alternative interconnect technologies. In particular, a sophisticated approach to powering down blocks can be undertaken without requiring the embedded software engineers to explicitly handle it. The NoC can take care of it, ensuring that no errors occur due to trying to communicate with a powered down block, something very difficult to guarantee with approaches where power down and power up is completely under software control. And another major power saving versus software control is that the (fairly power-hungry) processor does not need to be powered up all the time.

In April, ARM licensed 138 Sonics patents, some of them in these power areas. ARM has its own proprietary NoC technology Amba 4 AXI and ACE but coming relatively late to the NoC game, Sonics had already developed many of the fundamental technologies required for an effective NoC. They are also working with Sonics on their next generation NoC technology.

More information on Sonics’s 4th generation GHz NoC technology is here.

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Design Methodology and its Impact on the Future of Electronics

Design Methodology and its Impact on the Future of Electronics
by Paul McLellan on 11-18-2013 at 3:20 pm
Categories: EDA

Today at the Semisrael Expo 2013 (in Israel of course) Ajoy Bose gave a keynote on how design methodology will impact electronics. The big pictures is that microelectronics is driven by some major disruptive forces and, as a result, technology and industry are evolving dramatically, which creates a need for research and innovation and also new business opportunities.

What are these disruptive forces?

  • Business: industry is now being driven by consumer and mobile
  • Design: designing from scratch is being replaced by assembling blocks
  • Technology: smaller technology nodes are creating new challenges for power, timing, test, routing congestion and more
  • The conventional methods are being fractured


Of course the cost and complexity of designs has been rising fast in recent years. At 45nm an SoC design cost was about $68M and the SoC would contain about 81 blocks. By 22/20nm the cost has risen to $164M and the block count to 190. The probability of a re-spin is about 40% and, of course, is a disaster in terms of time-to-market.

And most of these are consumer markets: if your phone is not available in time for Christmas, you don’t get to sell it next March for less money since everyone will have bought a different phone. The speed of adoption of smartphones compared to older technologies such as television is astounding.

The methodologies to support block assembly type designs are not fully in place. One key is to move as much of design methodology up to the RTL level. It is possible to do a lot with signoff confidence at this level: test, power, congestion, clocks. The advantage of working at this level is that issues are discovered and fixed close to the source. Complexity is a lot reduced (a little RTL can generate a lot of gates and layout). And it is easier to do design exploration at this level. Of course, signoff still needs to be done after layout when all the details are in place. The purpose of the RTL-based approach is to ensure that very few problems remain to be dealt with.

High quality IPs are the starting foundation for an SoC. By using tools such as Atrenta’s IP Kit which is based on SpyGlass then problems in the IP can be detected and fixed early, resulting in SpyGlass Clean IP. The big guys such as TSMC are using this approach. They make most of their money when chips go into volume production. So they have a strong incentive to reduce the delay from availability of IP and processes until production.

The volume of data is overwhelming. An approach based on hierarchical abstraction models is needed, retaining just enough of the internals to be able to assemble models and verify them against each other. This requires two sets of tools: at the IP level to create the models and at the SoC level to put them together and debug and fix any issues. With this approach run times and memory requirements can be reduced by 10x to 100x.

In the new mobile driven world, fast accurate SoC design is the key factor for success.


More articles by Paul McLellan…

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Raptor Image Signal Processor

Raptor Image Signal Processor
by Paul McLellan on 11-18-2013 at 9:00 am
Categories: Imagination Technologies, IP

This fall there seems to be a bumper harvest of cores. Today Imagination Technologies announced their latest core for image signal processing. Like all of their cores, it is designed to be part of an SoC and is designed to work with other Imagination cores to build a complete image processing system. In particular, it is designed to work directly with the CMOS sensor(s) in cameras instead of having a separate external ISP (often stacked on the sensor itself), with the obvious cost and power reduction. Bringing the ISP onto the main application processor has many advantages such as higher performance due to the advanced process node typically used, access to main system memory, reduced cost and increased flexibility in sensor choice and, as just stated, the ability to leverage other Imagination IP to create optimized subsystems.


In 2012 Imagination acquired Nethra, who built standalone image processors, and this is the next generation as a core. They combined the high performance Nethra camera SoC with 5MP, 1080P, 12 bit, full functionality, already proven in the market by volume shipments along with Nethra’s expertise in lens and sensor tuning. Adding Imagination’s expertise in IP creation and delivery and their existing image quality and image technology and the PowerVR Raptor ISP was born.

The core is a low-power imaging pipeline developed specifically to enable:

  • ultra HD video
  • high pixel count photography
  • high performance vision systems
  • low power wearables and mobile
  • augmented reality
  • computer vision

This ties into the trend for everything to go mobile. Standalone HD video and still cameras are converging onto smartphones and tablets and, in the future, wearables (think Google Glass). This is a challenge since the functionality and quality of the specialist solutions now needs to be achieved in the size, cost and power envelope of a smartphone.


But consumer is not the only place for vision. Raptor supports up to 16 pixel depth which gives access to demanding markets requiring high dynamic range like auto (self-driving cars etc) and industrial. With support for 10 bit imaging they have what is needed for 4K pixel Ultra-HD TV. They also support multiple sensors so can handle front and back cameras with a single core, and can handle stereo and multi-camera arrays.

As I said earlier, the core is not designed to be an entire camera system on its own, but is intended to work with a CPU (I’m sure Imagination would love you to pick MIPS but you don’t have to) and a GPU. This allows for optimization between blocks to keep the power down. Raptor even has a re-entrant streaming port to allow image data to be streamed to custom processors and then reinserted back into the ISP pipe.

The core is available for licensing to lead partners today with delivery starting in Q1 2014.

There is an Imagination blog with greater detail about Raptor here.


More articles by Paul McLellan…

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Cadence Design Systems’ Shares Are Surprisingly Cheap

Cadence Design Systems’ Shares Are Surprisingly Cheap
by Ashraf Eassa on 11-17-2013 at 10:00 pm
Categories: Cadence, EDA

In the third and final (for now) part of this series on the EDA design tool vendors, I’d like to take a closer look at Cadence Design Systems. This is probably the most interesting of the three from both an industry perspective as well as an investment perspective for a variety of reasons. With that said I’d like to first provide some background on the company and its management and then take a closer look at the company’s financials and stock.

Some Rough Times
Rewinding back a bit to around the time of the financial crisis, it’s interesting to see the kind of mess that Cadence (and its shareholders) got into at the time. As it turns out, Cadence – not unlike other software companies – had faced some trouble with respect to the timing of revenue recognition. This wasn’t anything too egregious, particularly as the restatement was only for about $24 million worth of revenues against a revenue base that at the time was nearly $1 billion, but it definitely served to put off some investors. Couple that with the global economy melting down (which took its toll on the financial results of just about every tech company on the planet) and you have a recipe for disaster.

That wasn’t the extent of it, however. On Oct. 15, the company’s president and CEO and Michael Fister, along with four other top level executives, left the company. At the time, the growth in the EDA space was sputtering, Cadence’s customers (and in particular NXP and Freescale) were seeing significant business pressures, and Cadence itself was seeing rather fierce competition from both Magma Design Automation as well as Synopsys in analog and mixed signal design. Times were truly tough, and it seemed that Fister decided that it would be best to hand the company off to somebody else.

A new era of prosperity
Cadence landed itself a new president and CEO, Lip-Bu Tan, in January 2009. Prior to taking the helm in 2009, he had been on the board of Cadence since 2004. Additionally, he is the chairman of Walden International (a venture capital firm he founded in 1987) and sits on the boards of Ambarella, SINA, and Semiconductor Manufacturing International. Under his leadership, Cadence entered a new era of prosperity.

A quick look at Cadence’s stock price today suggests that the company is much healthier than it was in the 2008/2009 period with shares having roughly tripled from their lows. However, while Synopsys trades at all-time highs, and while Mentor Graphics is quickly approaching its all-time highs, Cadence trades at just under half of its pre-crash 2007 highs and about a third of its 1999/2000 Nasdaq bubble highs (it would be unreasonable to expect many tech companies to reach their 1999/2000 valuations, though, as this was a period of near insanity).

What’s more important to look at, though, is the underlying businessperformance. Here is a plot of Cadence’s revenue base and its net income over the last ten years:

Notice something interesting? The company is earning more money today than it has over the last ten years, having fully recovered from its 2008/2009 slump. Its revenue base is still a bit off of its 2007 highs, but overall, the company is in good shape. That being said, when you look at how the market actually values the company (that is, what multiple of the company’s earnings investors are willing to pay for the shares), it’s, frankly, not much. While investors are willing to pay 23.5 times earnings for Mentor Graphics and 25.9 times earnings for Synopsys, they’re only willing to cough up 8.30 times earnings for Cadence. Hmm!

Typically speaking, Wall Street (that is, the investment community as a whole) is more willing to pay a premium for today’searnings as long as they expect tomorrow’sto be significantly more robust. So what this would suggest is that Mentor and Synopsys are likely to grow at a faster pace and/or have more robust businesses than Cadence. However, what do the professionals think?

What gives?
The analysts covering Cadence believe that it will grow its net income per share by about 14% next year while at the same time growing its top line by about 7%. What’s really intriguing is that Wall Street expects Mentor Graphics to grow its bottom line by 10% and its top line by 6%, and it expects Synopsys to grow its bottom line by just 4.5% and its top line by 6.6%. This is actually pretty interesting – all of the EDA players are expected to grow at just about the same rate, but Cadence is by far the cheapest. Why could this be?

Well, while the financials are an important part of valuing any stock – tech or not – tech is unique in that investors care a lot about the perceived barriers to entry. Synopsys, for instance, is not only the leading EDA tool vendor, but it is also the second largest provider of semiconductor IP – an enviable position to be in. However, what’s peculiar is that Cadence is probably in a better position for, say, FinFET designs than Mentor Graphics is, if the design enablement readiness charts given by TSMC about the readiness of tools from the various vendors (found here) still hold true.

Indeed, while it’s always important to do your own due diligence before following the recommendations of any analysts, it’s interesting to note that the vast majority of the sell-side analysts think that Cadence is either a “buy” or an “outperform”. My impressions thus far is that Cadence is probably the best deal in the EDA space today for investors, although I do plan to do much more work on the stock and report back.


More articles by Ashraf Eassa…

Also Read: A Brief History of Cadence

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A Brief History of eSilicon

A Brief History of eSilicon
by Daniel Nenni on 11-16-2013 at 10:00 pm
Categories: EDA

eSilicon Corporation was founded in 2000 with Jack Harding as the founding CEO and Seth Neiman of Crosspoint Venture Partners as the first venture investor and outside Board member. They both remain involved in the company today, with Jack continuing as CEO and Seth now serving as Chairman of the Board.

Both Harding and Neiman brought important and complementary skills to eSilicon that helped the company maneuver through some very challenging times. Prior to eSilicon, Jack was President and CEO of Cadence Design Systems, at the time the largest EDA supplier in the industry. He assumed the leadership role at Cadence after its acquisition of Cooper and Chyan Technology (CCT), where Jack was CEO. Prior to CCT, Jack served as Executive Vice President of Zycad Corporation, a specialty EDA hardware supplier. He began his career at IBM.

Seth Neiman is Co-Managing Partner at Crosspoint Venture Partners, where he has been an active investor since 1994. Seth’s investments include Brocade, Foundry, Juniper and Avanex among many others. Prior to joining Crosspoint, Seth was an engineering and strategic product executive at a number of successful startups including Dahlgren Control Systems, Coactive Computing, and the TOPS division of Sun Microsystems. Seth was the lead investor in eSilicon, and incubated the company with Jack at the dawn of the Pleistocene epoch.

THEEARLYYEARS
eSilicon’s original vision was to develop an online environment where members of the globally disaggregated fabless semiconductor supply chain could collaborate with end customers looking to re-aggregate their services. The idea was straight-forward – bring semiconductor suppliers and consumers together and use the global reach of the Internet to facilitate a marketplace where consumers could configure a supply chain online. The resultant offering would simplify access to complex technology and reduce the risk associated with complex design decisions.

Many fabless enterprises had struggled with these issues, taking weeks to months to develop a complete plan for the implementation of a new custom chip. Chip die size and cost estimates were difficult to develop, technology choices were varied and somewhat confusing, and contractual commitments from supply chain members took many iterations and often required a team of lawyers to complete.

The original vision was simple, elegant and sorely needed. However, it proved to be anything but simple to implement. In the very early days of the company’s existence, two things happened that caused a shift in strategy. First, a close look at the technical solutions required to create a truly automated marketplace yielded significant challenges. Soon after formation of the company, eSilicon hired a group of very talented individuals who did their original research and development work at Bell Labs. This team had broad knowledge of all aspects of semiconductor design. It was this team’s detailed analysis that lead to a better understanding of the challenges that were ahead.

Second, a worldwide collapse of the Internet economy occurred soon after the company was founded. The “bursting” of the Internet bubble created substantial chaos for many companies. For eSilicon, it meant that a reliable way to monetize its vision would be challenging, even if the company could solve the substantial technical issues it faced. As a result, most of the original vision was put on the shelf. The complete realization of the “e” in eSilicon would have to wait for another day. All was not lost in the transition, however. Business process automation and worldwide supply chain relationships did foster the development of a unique information backbone that the company leverages even today. More on that later.

THEFABLESSASIC MODEL
Mounting technical challenges and an economic collapse of the target market have killed many companies. Things didn’t turn out that way at eSilicon. Thanks to a very strong early team, visionary leadership and a little luck, the company was able to redirect its efforts into a new, mainstream business model. It was clear from the beginning that re-aggregating the worldwide semiconductor supply chain was going to require a broad range of skills. Certainly design skills would be needed. But back-end manufacturing knowledge was also going to be critical. Everything from package design, test program development, early prototype validation, volume manufacturing ramp, yield optimization, life testing and failure analysis would be needed to deliver a complete solution. Relationships with all the supply chain members would be required and that took a special kind of person with a special kind of network.

eSilicon assembled all these skill sets. That deep domain expertise and broad supply chain network allowed the company to pioneer the fabless ASIC model. The concept was simple – provide the complete, design-to-manufacturing services provided by the current conventional ASIC suppliers, such as LSI Logic, but do it by leveraging a global and outsourced supply chain. Customers would no longer be limited to the fab that their ASIC supplier owned, or their cell libraries and design methodology.

Instead, a supply chain could be configured that optimally served the customer’s needs. And eSilicon’s design and manufacturing skills and supply chain network would deliver the final chip. The volume purchasing leverage that eSilicon would build, coupled with the significant learning eSilicon would achieve by addressing advanced design and manufacturing problems on a daily basis would create a best-in-class experience for eSilicon’s customers.

As the company launched in the fall of 2000, the fabless ASIC segment of the semiconductor market was born. Gartner/Dataquest began coverage of this new and growing business segment. Many new fabless ASIC companies followed. Antara.net was eSilicon’s first customer. The company produced a custom chip that would generate real-world network traffic to allow stress-testing of ebusiness sites before they went live. Technology nodes were in the 180nm to 130nm range and between eSilicon’s launch in 2000 and 2004, 37 designs were taped out and over 14 million chips were shipped.

Fabless ASIC was an adequate description for the business model as everyone knew what an ASIC was, but the description fell short. A managed outsourced model could be applied to many chip projects, both standard and custom. As a result, eSilicon coined the term Vertical Service Provider (VSP), and that term was used during the company’s initial public exposure at the Design Automation Conference (DAC) in 2000.

eSilicon’s positioning, DAC 2000

The model worked. eSilicon achieved a fair amount of notoriety in the early days as the supplier of the system chip that powered the original iPod for Apple Computer. The company also provided silicon for 2Wire, a company that delivered residential Internet gateways and associated services for providers such as AT&T. But it wasn’t only the delivery of “rock star” silicon that set the company apart. Some of the original ebusiness vision of eSilicon did survive.

eSilicon’s first logo. The squares symbolize the end product – the chip

The company launched a work-in-process (WIP) management and logistics tracking system dubbed eSilicon Access[SUP]®[/SUP] during its first few years. The company received a total of four patents for this technology between 2004 and 2010. eSilicon Access, for the first time, put the worldwide supply chain on the desktop of all eSilicon’s customers. Using this system, any customer could determine the status of its orders in the manufacturing process and receive alerts when the status changed. eSilicon uses this same technology to automate its internal business operations today.

GROWINGTHEBUSINESS
During the next phase of growth for the company, from 2005 to 2009, an additional 135 designs were taped out and an additional 30 million chips were shipped. Technology nodes now ranged mainly from 90nm down to 40nm. It was during this time that the company began expanding beyond US operations. Through the acquisition of Sycon Design, Inc., the company established a design center in Bucharest, Romania. A production operations center was also opened shortly thereafter in Shanghai, China.

Recognizing the growing popularity of outsourcing, eSilicon expanded the VSP model to include semiconductor manufacturing services (SMS). SMS allowed fabless chip and OEM companies to transition the management of existing chip production or the ramp-up and management of new chip production to eSilicon. The traditional design handoff of the ASIC model was now expanded to support manufacturing handoff. The benefits of SMS included a reduction in overhead for the customer as well as the ability to focus more resources on advanced product development.

Extensions such as SMS caused the Vertical Service Provider model to expand, creating the Value Chain Producer (VCP) model. The Global Semiconductor Alliance (GSA) recognized the significance of this new model and elected Jack Harding to their Board to represent the VCP segment of the fabless industry.

In the years that followed, up to the present day, eSilicon has grown substantially. The number of tape-outs the company has achieved is now approaching 300 and the number of chips shipped is on its way to 200 million. The company has also expanded into the semiconductor IP space. While its worldwide relationships for third-party semiconductor IP are critical to eSilicon’s success, the company recognized that the ability to deliver specific, targeted forms of differentiating IP could significantly improve the customer experience.

Since so many of today’s advanced chip designs contain substantial amounts of on-board memory, this is the area that was chosen for eSilicon’s initial IP focus. The company acquired Silicon Design Solutions, a custom memory IP provider with operations in Ho Chi Minh City and Da Nang, Vietnam. This acquisition added 150 engineers to focus on custom memory solutions for eSilicon’s customers.

As of June 30, 2013, eSilicon employs over 420 full-time people worldwide, of which over 350 are dedicated to engineering. Headquartered in San Jose, California, the company maintains operations in New Providence, New Jersey and Allentown, Pennsylvania; Shanghai, China; Seoul, South Korea; Bucharest, Romania; Singapore and Ho Chi Minh City and Da Nang, Vietnam. The company’s diverse global customer base consists of fabless semiconductor companies, integrated device manufacturers, original equipment manufacturers and wafer foundries. eSilicon sells through both an internal sales force and a network of representatives.

THEEVOLVINGMODEL
The eSilicon business model has evolved further. VSP and VCP are now SDMS (semiconductor design and manufacturing services). Arguably the longest, but perhaps the most intuitive name. Through the years, eSilicon has allowed a broad range of companies to reap the benefits of the fabless semiconductor model, many of which couldn’t have done it on their own.

This ability to bring a worldwide supply chain within reach to smaller companies gave eSilicon its start, but the model has worked well for eSilicon beyond these boundaries. Today, eSilicon serves customers that are much larger than eSilicon itself; customers that could “do what eSilicon does.” In the early days, the company discounted its chances of winning business at an enterprise big enough to maintain an “eSilicon inside.”

Time has proven this early thinking to be too limiting. Many of eSilicon’s customers today can clearly maintain an “eSilicon inside,” but they still rely on eSilicon to deliver their chips. Why? In two words, opportunity cost. It has been proven over time that for any enterprise the winning strategy is to focus on the organization’s core competence and invest in that. All other functions should be outsourced in the most reliable and cost-effective manner possible. Simply put, eSilicon’s core competency fits in the outsourcing sweet spot for many, many organizations. This trend has created new value in the fabless semiconductor sector and facilitated many new design starts.

WHAT’SNEXT
As the fabless model grows, there are new horizons emerging. During its early days, the vision of using the Internet to facilitate fabless technology access and reduce risk was largely put on the shelf. The reasons included the challenges of solving complex design and manufacturing problems and the lack of a clear delivery mechanism over the Web.

Today, these parameters are changing. The Internet is now an accepted delivery vehicle for a wide array of complex business-to-business solutions. eSilicon’s talented engineering team has also developed a substantial cloud-enabled environment that is used to automate its internal design and manufacturing operations every day. This team consists of many of the same people who highlighted the challenges of addressing these issues in the company’s early years. What a difference a decade can make.

What if that automated environment could be made available to end users in a simple, intuitive way? New work at eSilicon is taking the company in this direction. The recent announcement of an easy-to-use multi-project wafer quote system is an example. What once could take two weeks or more, consisting of many inquiries and legal agreement reviews, is now done in as little as five minutes with an extension to eSilicon Access. With availability on both the customer’s desktop and smartphone, this is clearly the beginning of a new path. eSilicon changed the landscape of fabless semiconductor in 2000 with the introduction of the fabless ASIC model. It’s time to do it again and bring back the “e” in eSilicon.

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Social Media at Synopsys

Social Media at Synopsys
by Daniel Payne on 11-15-2013 at 4:35 pm
Categories: EDA, Synopsys

When I talk about social media and mention Synopsys you may quickly think of Karen Bartleson, the Senior Director of Community Marketing, because she:


Karen Bartleson
Continue reading “Social Media at Synopsys”

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TowerJazz and Silvaco BFF

TowerJazz and Silvaco BFF
by admin on 11-15-2013 at 1:04 pm
Categories: EDA

Last week was the TowerJazz Technology Fair 2013. TowerJazz is the fourth biggest foundry in the world after TSMC, GF and UMC. They have fabs in Newport Beach (the old Jazz, itself with roots in Rockwell), two in Israel (the old Tower, with roots in National Semiconductor) and one in Japan (acquired from Micron). The technology fair has two days, the first focused on aerospace and defense and the second on consumer. Silvaco seemed to be a theme running through the day with so many customers using Silvaco tools.

The aerospace and defense often require specialized processes or, at least, specialized analysis for things like single event upsets. This plays to Silvaco’s strengths where they can use their TCAD tools to analyze/develop the process and seamlessly tie that back into their circuit simulation technology to analyze actual designs.


This, in turn, is driven by the availability of a wide range of PDKs for TowerJazz’s processes:

  • TS18SL (0.18u CMOS 5V)
  • TS18IS (0.18um CMOS 5V +CIS)
  • BCD25MB – 0.25um CMOS
  • CA13HC (0.13um CMOS)
  • CA18HA – 0.18um CMOS
  • CA18HD – 0.18um CMOS
  • CA18HR – 0.18um CMOS
  • CA18HG – 0.18um CMOS
  • CA25QFS – 0.25um CMOS
  • SBC18H3 – 0.18um BiCMOS SiGe
  • SBC18H2 – 0.18um BiCMOS SiGe
  • SBC18HX – 0.18um BiCMOS SiGe
  • SBC18HA – 0.18um BiCMOS SiGe
  • SBC18HK – 0.18um BiCMOS SiGe
  • SBC35QTA – 0.35um BiCMOS SiGe
  • SBC35QTS – 0.35um BiCMOS SiGe
  • plus some legacy PDKs
  • and if your PDK is not here they can build it

What counts as a state-of-the-art process depends on the application. For RF and analog the leading edge is 0.18um and 0.13um, nobody is trying to do those sorts of designs in 16nm FinFET.


As an example, Ultra Comm have developed advanced fiber optic transceiver chips that operate from 10Mbps to 12.5GBps per channel in a 4Tx 4Rx format incorporated in Ultra Comm’s X80-QFN transceivers. It is build in Jazz 0.18um SiGe and designed with Silvaco tools.

Ultra Comm also developed the world’s first integrated Fiber Fault Detection integrated circuit which performs on-demand Optical Time Domain Reflectometry measurements to 1cm resolution embedded in Ultra Comm X80-QFN transceivers. Again, in 0.18um SiGe designed with Silvaco tools. And there are more designs in the funnel.

When I said they used Silvaco tools, they actually use Silvaco CAD tools exclusively for all integration functions due to ease of use, accuracy of the models and the cost structure. Not to mention the fact that they have had 100% first pass success on all chips designed using the Silvaco toolsuite on Jazz process technologies.

Another even sexier project is Chronicle Technology who are making the sensor for the Naval Research Laboratory’s Solar Orbiter Heliospheric Imager (SoloHI) program design using Silvaco EDA tools and TowerJazz manufacturing. They are building a 4Kx4K advanced pixel sensor array using CMOS technology. This is used to image the sun from the spacecraft that flies between the orbits of Mercury and Venus. It is covered in heat shields to keep everything cool enough to function. It’s antenna has to be hidden behind the spacecraft too, to keep it from becoming too hot.

A full list of all Silvaco PDKs (not just for TowerJazz) is here.


More articles by Paul McLellan…

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Android Kit Kat Openly Preaching for DSP offloading

Android Kit Kat Openly Preaching for DSP offloading
by Eric Esteve on 11-15-2013 at 10:04 am
Categories: Arm, Ceva, IP

In fact KitKat advocates low-power always-on functionality, and this is essential for contextual-awareness. Always-on functionality is saving battery life, which seems to be weird at first: if your phone is always-on you would expect it to consume much power… But always-on goes together with screen-off (the screen is a high source of power consumption) and means that the Application Processor is off or on idle state, but real time location tracking and contextual awareness functions run in the background, thanks to DSP offloading. If we compare the power consumption linked with three different architectures:

  • Voice activation on ARM Application Processor takes about 20 mA
  • Using a dedicated chip for handling always-on voice processing, like MOTO X using TI C55, the consumption goes down to 4.5 mA, which is already better, but not as good as when doing:
  • Voice activation on CEVA TL410, the Teak Lite DSP core consuming less than 2 mA

CEVA has developed Android Multimedia Framework (AMF), and we have described in this blog how AMF can be useful to minimize power consumption in smartphones, simply by helping the OS to be aware that a DSP core, even deeply embedded, can be available to run certain tasks. In this case, these tasks are screen-off functionalities, including voice-trigger, audio playback, and sensor-fusion in general. Being able to run always-on functionality at the lowest possible power, in fact without involving the AP as we have seen when comparing the power consumption figures, is an essential condition to keep battery life as long as possible.

We all love listening to music on our phones. In fact, listening to music, audiobooks, or podcasts regularly on our smartphones is probably one of the few things we all really share in terms of our usage patterns. The problem with listening to audio for extended periods, though, is that it can really put the hammer down on your battery life. Google has introduced audio tunneling to DSP in Android 4.4. The premise is simple – instead of using the application processor to decode audio or respond to audio output requests, this responsibility is offloaded to the onboard DSP (digital signal processor). The DSP is much more efficient at such tasks than the CPU, and as such, Google estimates that the amount of power used playing back audio on your phone could decrease in excess of 50%!

AMF is a system level software solution and allows offloading of multimedia tasks from CPU/GPU to most efficient application-specific DSP platforms. When running Android OS, you need either to develop such a solution by yourself, either to benefit from a ready to use framework, allowing using deeply embedded programmable hardware engines, and software modules optimized for them. Due to its OS agnostic standard API, CEVA’s AMF would comply with any Android endorsed mechanism for multimedia offloading (e.g. KLP).

In summary, AMF features:

  • AMF provides a seamless method for Android programmers to access Multimedia DSPs (audio, and also imaging) in the AP chip or CODEC chip, using high-level language or API, there is no need to directly program the DSP,
  • AMF enables computing intensive multimedia tasks execution on “deeply-embedded” DSPs, resulting in lower power compared to same tasks on main CPU: as we have seen when comparing the power consumption figures, AMF allows down to 8x lower power for audio/voice applications
  • AMF uses standard API and includes HAL drivers, Host-DSP communication modules, RTOS, and debug capability, offering a full reference design.

We can see on the right side of the above picture an AMF based architecture where the API run on the CPU, within the Stagefright Framework, and the SW run on DSP, when the mobile device is normally on. To run Always-on functionality, only the yellowed bottom right tasks essentials for contextual-awareness could run on the Teak Lite 410 DSP core, saving battery life, which is good for your smartphone, and for your end-user experience.

Eric Esteve from IPNEST –

More Articles by Eric Esteve …..

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Signoff Summit: The Fastest Path to Design Signoff

Signoff Summit: The Fastest Path to Design Signoff
by Daniel Nenni on 11-13-2013 at 8:00 pm
Categories: Cadence, EDA

Cadence’s Signoff Summit will be held next week, November 21 at Cadence in San Jose.

This is the first of a series of all-day Signoff Summits from Cadence that focus on the multiple facets of design signoff. This first summit will include keynote addresses plus sessions covering the multiple solution components that comprise a comprehensive signoff solution:

  • Power analysis and signoff
  • Parasitic extraction
  • Digital timing closure and signoff
  • Physical verification
  • Design for Manufacturing (DFM)

There will be extended focus on the new Cadence® timing and power signoff solutions: Tempus™ and Voltus™. The Tempus Timing Signoff solution, announced in May 2013, generated huge attention at DAC. Voltus is a new Power Signoff solution that raises the bar for power analysis and signoff.

In each session, you will learn more details about the solutions and hear experiences directly from customers. For timing and power signoff, there will also be on-stage demos to show you in detail how these solutions perform.

To close the summit, there will be a cocktail hour from 5pm to 6pm. Silicon Signoff and Verification R&D technical staff will be on-hand to answer your detailed questions, plus additional demos will be shown.

Who should attend?

  • Design engineers responsible for timing closure and signoff
  • Design engineers responsible for power analysis and signoff
  • Design/CAD engineers interested in learning about advancements in signoff solutions
  • Project managers interested in learning how the latest Cadence signoff solutions can be used to improve their design methodology

What you will learn

  • The latest information on each of the signoff component solutions
  • How each of the solutions can improve your design flows and methodology
  • Practical usage of the signoff solutions directly from customers
  • Live demos of all solutions

Agenda
[TABLE] cellpadding=”5″ style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; margin-top: 5px; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid”
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; width: 100px; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Time
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Title
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Speaker
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 8:30 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Breakfast/Registration
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:00 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Cadence Welcome, Overview and Keynote
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Anirudh Devgan, Corp VP & Chief Technology Advisor
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:30 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Defining Signoff amidst the EDA-Foundry-Design Vortex
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Richard Trihy, Golbalfoundries
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:50 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Break
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
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| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 10:00 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Power Analysis & Signoff Challenges
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Jerry Zhao, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | High Performance, multi-CPU Scalable Power Signoff for Mega Designs
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Patrick Sproule, NVIDIA
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| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 11:30 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Fast and Accurate Signoff Extraction for Advanced Node Designs
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Kyle Peavy, Texas Instruments
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Incremental Signoff Metal Fill Flow Using Encounter, PVS & QRC
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Takeyoshi Ikeda, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 12:15 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Lunch
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 1:10 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Teething Signoff – You have to own it
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Jim Hogan, EDA Visionary & Investor
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| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 1:30 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Breaking the High Performance Barrier in Timing Analysis & Signoff – The Tempus[SUP]TM[/SUP] Timing Signoff Solution
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Ruben Molina, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Advanced Timing Solutions & Challenges – Statistical OCV, Path-Based Analysis, & Low Voltage FinFET modeling
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | R&D, Cadence
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 3:00 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Break
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
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| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 3:15 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Transitioning to PVS
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Marie Luo, Conexant Systems
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Physical Verification Signoff for DDR IP using PVS
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Tobing Soebroto, Cadence IP Design
|-
| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 4:00 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Macro Modeling based Layout Dependent Effect-Aware Custom Design Flow
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Pei Yao, Globalfoundries
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Foundry-certified DFM services: A alternative to meet mandatory DFM requirements
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Cadence DFM Services
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 5:00 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Close and Reception
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Lip-Bu Tan, Cadence President & CEO
|-

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Full Chip ESD Sign-off – Necessary

Full Chip ESD Sign-off – Necessary
by Pawan Fangaria on 11-13-2013 at 7:00 pm
Categories: Ansys, Inc., EDA

As Moore’s law keeps going, semiconductor design density on a chip keeps increasing. The real concern today is that the shrinkage in technology node has rendered the small wire geometry and gate oxide thickness (although fine in all other perspectives) extremely vulnerable to ESD (Electrostatic Discharge) effects. More than 1/3[SUP]rd[/SUP] of chip failures happen due to ESD. An IC can be exposed to ESD either from transfer of charge from external sources such as human interaction (tested by HBM, i.e. Human Body Model) and machine handling (tested by MM, i.e. Machine Model) or from internal built up of charge leaving through the package (tested by CDM, i.e. Charged Device Model). While I/O interface is most vulnerable to ESD, entire internal circuit of IC in under risk. Major damages such as gate oxide breakdown can lead to immediate failure whereas wires and vias can wear out over time.

It’s important and essential to protect the circuitry inside an IC from dielectric breakdown. Typically clamp circuits are placed at the I/O and P/G pads which can handle large transient current, provide efficient discharge path to ESD current and prevent any pin voltage from exceeding the oxide breakdown voltage.

In the I-V characteristic of a typical ESD protection circuit, the dotted line curve represents the response of a turn-on device and the solid line curve represents the snap-back characteristic of a NMOS ESD device. It’s important to note that with technology migration the oxide breakdown voltage continues to move towards left while the thermal failure limit continues to move down, thus imposing severe constraint on the protection (clamp) circuit to operate in that compressed region.

With increasing design size and complexity at lower nodes, design of ESD protection circuit is becoming increasingly complex requiring planning and verification at full chip level for all P/G nets along with ESD clamp cells and the package. The pin-to-pin paths that do not meet the defined limits should be highlighted and connectivity or routing issues must be identified with accurate resistance or impedance calculations. Current density in wires from any ESD event must be accurately estimated to ensure that the wires will not fail from such high levels of current flow.

Apache’sPathFinder provides a robust comprehensive planning and verification for ESD at full chip level which ensures that connectivity between any two pins meets design guidelines. It performs connectivity analysis for HBM, MM and CDM discharge events and predicts the current density in all wires and vias. By leveraging Apache’s RedHawk (for digital designs) and Totem (for analog designs) tools, PathFinder provides unprecedented capacity and performance for simulating large SoCs and custom designs.

During HBM or MM check, PathFinder estimates the effective resistance between any two pins in the circuit by traversing the network through one or more clamp cells placed between these pins. This is done very accurately by taking into account the clamps which pass the loop resistance threshold between two pins and can effectively provide discharge pathway; parallel R is considered between the two pins.

In case of CDM check, PathFinder calculates the resistance of the path between any device to VSS or VDD to device and also loop resistance between device VDD pin to clamp cell VDD pin, clamp cell VSS pin to device VSS pin and the resistance of clamp cell itself.


Current Density Checks are very important to save wires and vias from electro migration. PathFinder identifies clamp cells between pin pairs that are effective in conducting current and then calculates the current through the wires and vias connected to these pins or pads by injecting the current into the pads as per ESD standard definition. In then highlights the wires and vias that fail the current density limits prescribed by the technology process.


[Textual and Graphical reporting of issues – VDD route from a logic cell to a clamp cell fails defined resistance limit]

PathFinder reports the analysis results in text as well as graphical form. It highlights weak areas and resistance bottlenecks in the design and helps designers in fixing those without leaving PathFinder environment. An interactive ‘what-if’ analysis can be carried out before committing to layout. There is a whitepaperon Apache website which provides great level of details about ESD and the solution for full-chip ESD integrity analysis, verification and fixes. After reading this paper, I could gain more insight into ESD phenomenon which I did not have earlier. Interesting read!!

More Articles by Pawan Fangaria…..

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