John Heinleinfrom ARM briefed me at DAC exactly one week ago. I love to use my mobile devices (MacBook Pro, iPad and Samsung Galaxy Note II) every day, and many mobile devices are ARM-powered because of the low power consumption, and pervasive eco-system around the architecture. Apple with the MacBook Pro is still Intel-powered, but who knows if Apple will switch one day to an ARM processor in both the MacBook Pro and MacBook Lite product lines.
Last year at DAC we didn’t really know the circuit simulation roadmap for Synopsys because of all the EDA company acquisitions, however this year it’s clear to me that:
Continue reading “AMS IC Simulation Update from Synopsys at DAC”
In a typical analog IC design team, multiple engineers and layout professionals work on cells and libraries. At various points during the design process they will commit changes to their designs into the Design Management (DM) system that manages their files – be it Subversion, Perforce or some other commercial tool.
Using the VersICAnalog Verification flow from Methodics, designers now have a way to run scripted tests and regressions from within their Cadence environments. These tests can be launched, tracked and analyzed right from the Cadence GUI. Once a designer is satisfied with her changes – say with a combination of visual checks and scripted regressions – she can commit these changes to the DM.
Committing changes to the DM system achieves two goals – it allows designers to save their work, and to communicate their changes to peers and integrators. However, there is no real check to ensure that a particular design change committed to the DM works within the context of the overall design. Often, individuals may commit changes that may work in their context, but break the design as a whole. At the integration level, it is usually hard to pick up a set of commits from the design team and try to integrate them, particularly for larger designs.
The VersIC release flow is designed address this particular problem – ensure that check-ins that are visible to other team members adhere to a minimum quality level. The quality level itself can be dialed in by the team – it can be as strict or as loose as the team chooses it to be.
The VersIC Release Server is a process that runs qualifying scripted regression in the background on release candidates to ensure that they meet this minimum quality requirement. A release candidate is created when a designer reaches some logical point in the design cycle – and submits her recent changes for release. These changes can be a single change set, or multiple change sets accumulated across multiple days of work. Release candidates are submitted to the Release Server by VersIC and they are added to the tail of a queue of candidates.
Release Server Flow
The Release Server pulls candidates out of the queue in FIFO order, creates a special workspace with the last known good release, applies the changes in the candidate to that workspace and runs a qualifying regression. If the regression passes, the team is informed of a new release. The next time any user updates her workspace, VersIC will update it to this new release. If the release fails, the user that submitted the candidate is informed of the cause for the failure, along with logs to look at and then debug the failure mode.
The advantage of this flow is that users can continue to check-in changes into the DM system as before. However, every time that they reach a small or large internal goal, they can attempt a release, which allows them to fix problems in an incremental fashion. Also, other users do not see their changes until it passes through a quality check.
VersIC Release Management Console
The VersIC Release Server has many advanced features to optimize for both run time and resource usage. The key run time optimization feature is Pipelining – the release server can handle multiple releases from different users simultaneously, building workspaces and running them in true pipelined fashion so that it can scale dynamically with the load. Another key feature is the ability to split designs up into self-contained ‘blocks’ (say a Cadence library can be designated as a ‘block’), which allows users to release changes to cells within a block without impacting other blocks. VersIC also automatically picks up the right qualifying regression to run based on the current context so that relevant qualification is applied to the release candidate.
VersIC implements a well thought-out release management system right within the Cadence environment which makes collaboration, integration and tracking seamless and effective for both large and small IC design teams.
Further Reading
Bringing Sanity to Analog IC Design Verification using RegressionsMethodics CEO on Managing Design Quality!
Analog IC Verification – A Different ApproachA Brief History of Methodics
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If you have attended DAC in Austin (June 2-5), you probably have missed the first TSMC Technology Symposium. It was held on June 6 in Shanghai. Considering my own experience of a 29 hours trip to come back home (in France), I doubt that it was any possible to leave Austin on June 5 to attend TSMC Technology Symposium in Shanghai on June 6, even flying a 2X supersonic airplane (the trap is the 13 hours time difference between both cities – in the wrong direction, leaving only a couple of hours to make it!).
But, if you want to meet with Sidense at TSMC Technology Symposium, you still can make it if you live close to:
On a map, Yokohama looks far from Tokyo by car, but if you take the Shinkensen (Japanese High Speed train), you will be surprised how fast you arrive. The point is just to read Japanese characters in Tokyo station to find the right platform, or ask your way, that I did successfully!
Just remember that Sidense is the OTP NVM IP vendor who has recently won an interesting case as I blogged here: The decision made by United States Court of Appeals for the Federal Circuit, “Affirming” the District Court for the Northern District of California’s summary judgment of non-infringement on Kilopass’ patent claims and its dismissal, with prejudice, of all remaining claims against Sidense, is certainly a good news for IP and EDA vendors playing a fair sales and marketing game in the field. Let’s make the assumption that you have not infringed anybody else rights, but developed innovative product (IP function or EDA tool), be clever enough in marketing the product and generate numerous design win, so your sales revenue start growing fast, leading your direct competitor to prefer using the legal field instead of fair market competition… We have seen many legal cases in the recent years in the EDA and IP ecosystem, and I am almost sure that some of these cases have been initiated to compensate for a marketing weakness.
To go to TSMC Technology Symposium, just register here, and you could visit Sidense and discuss about OTP NVM IP, much more interesting topic than legal battle.
Eric Esteve from IPNEST –
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GSA’s next event is the annual Entrepreneurship Conference to be held at the Computer History Museum on July 18th. The event runs from 3pm to 8pm. Attendance is free but you must register here.
The event consists of 5 panel sessions followed by a reception. The full roster of who will be on each panel is not completely finalized yet, but here is the current status:
Full details of the panels including the panelists as they get signed up are on the GSA website here. The event wraps up with a reception at 7.30pm.
While eyes remain fixated on the architectural battle between Intel and ARM, a second front is soon about to open up that will determine mobile supremacy for the rest of the decade. Whereas yesterday’s story on the collapse of Wintel and the anointing of Google and Samsung are repeated endlessly, now tables are being set for a significant turning. Thanks to Intel introducing a very competitive Silvermont architecture and the reality that a process gap is growing vis-à-vis Samsung’s Foundry, a new hierarchy is forming that will allow the x86 monopoly to extend its power by pulling in DRAM and NAND into an extended SOC family of solutions. Shortages and rising prices Continue reading “…And Now Intel Will Make a Turn Towards Memories as it Plans to Capture Samsung”
I just don’t understand it? My kids love surprises but I have yet to find management that does, go figure but boy during a review they can really spring them on ya! What surprises me is the absurdness of my title, GPU vs. FPGA. FPGAs are not GPUs and likewise but none the less there is the push to make a fit where nature does not allow. I liken the FPGA to the Ferrari and the GPU to Big Foot. Remember that, going to the Aud in your town and watching that monster truck crush them cars. I never regained my hearing. Vinny Boombots is still saying the suit will close any day now.
The GPU back in the day was just a Graphical Processing Unit. Today thanks to CUDA and OpenCL, they can be programmed to be massively parallel. Why does the word parallel always proceed with massively nowadays? Anyways, we see the benchmarks, take a NVIDIA Fermi and all its cores and unroll your 262k point FFT and get er done in 9us. Not really, we forgot the memory overhead, which is roughly another 60ms. An Old Virtex-5 does the same FFT in 2.6ms. The FPGA used about 15 Watts and the GPU roughly 130 watts. Not that I’m a green fella and all that; but for heavy DSP processing where perhaps these things have a SWaP requirement, the GPU is a tough cooling challenge and awfully hungry.
Who’s in control? That’s like telling someone to settle down when they are spun up. Try it; you’ll be in for some laughs. Unless you are using the Intel Sandy Bridge, and I’m not sure you can run GPGPU there but let’s just say you could, other GPUs need to be controlled by a CPU. More watts and overhead. Now the one die CPU/GPU is a great idea but the FPGA performing DSP processing does not need a CPU per say to control it. Even if it did, the Xilinx Zynq is a nice fit with the dual ARMs to handle the out of band calculations right into the same FPGA. What about IO, the FPGA can support anything you can think of, as for real-time data processing we are not using TCP/IP or even UDP, think low latency here.
The take away is that they really are two different beasts and it is complicated to make a fit where it does not belong. What has happened though is the open community thanks to CUDA has allowed the littlest of nerds to play with GPU processing and the community has come to this conclusion, it is cool. And it really is, but when you have requirements to meet and processing that needs low latency and the answer at the same time every time (deterministic) the FPGA will be your choice. Now perhaps you have a non-real time system and need to play back lots, and lots of data for hardware in the loop acceleration, then the GPU may be your answer. My point is get your head out of the buzz word bingo and sift through all the marketing propaganda. Make the right decision and design the best system for your customer and make your stockholders happy…. Have fun…
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Monday morning at DAC I met with Real Intent to get an update on their SoC sign-off tools:
Years ago Prakash was at IBM the only two years that they attended DAC, in an attempt to offer their internal EDA tools to the EDA marketplace. Graham worked at Nassda marketing the HSIM hierarchical FastSPICE simulator, competing against me with Mentor’s Mach TA simulator (HSIM won, big time).
Dr. Prakash Narain, Graham Bell
Continue reading “SoC Sign-off, Real Intent at DAC”
I’m utterly amazed at how IC-based products are improving our quality of life by implantable devices. The modern day pacemaker has given people added years of life by electrically stimulating the heart. A privately-held company called NeuroPace was founded in Mountain View, California to treat epilepsy by using responsive neurostimulation. Their first product is called the RNS System (Responsive NeuroStimulation), and it is a programmable, battery-powered, microprocessor-controlled device that delivers a short train of electrical pulses to the brain through implanted leads.
I spoke with Dean Anderson, engineering manager at NeuroPace about their IC design approach.
Dean Anderson, NeuroPace
Interview
Q: What is your role at NeuroPace?
I’m an IC design manager working on the next generation of neuro-stimulators. We have mostly system and front-end engineers and contract the IC layout efforts.
Q: How did you get interested in IC design?
I’ve always been interested in DSP and bio-medical applications. Out of grad school I worked at a pace maker company, and then 12-14 years on very low-power embedded devices. Small size and low power are the big design challenges, along with FDA approval using clinical trials proving efficacy on patients. Once you submit data to the FDA then you have to await their decision, then it’s OK to sell into the American market.
Q: What is the IC design flow approach at NeuroPace?
All of our chips are mixed signal designs. We just taped out in December an AMS SoC. Our approach is more bottom-up, where we partition our design into sub-blocks, then implement each sub-block. Design follows the partitioning and system specification.
For the digital portion we prototype in an FPGA. We use Verilog for our digital design and verification of test-benches, and use both ModelSim (Mentor) and Incisive (Cadence).
Analog designs are simulated and may be placed into a test chip before the final AMS chip. Spectre (Cadence) is our SPICE simulator.
Schematic capture is with Cadence Virtuoso.
Integration adds the Analog and Digital blocks together. We need to do more simulation of the Analog and Digital blocks together. Interfaces between the blocks are made as simple as possible.
Q: What were your latest Chip specs?
It was about 8 million transistors, running at 5MHz to achieve nA levels. An idle chip consumes maybe 2 uA, while peak usage is 20 uA, turning on the radio raises us to mA levels. We are totally power-centric because of the long battery life we need for 5 years of operation, but the longevity depends on the needs of the patient. Our power supply is a lithium-based battery specially designed for implants. Our device is curved and is installed inside of a patient’s skull.
Our patients can go swimming because our device is sealed against the elements.
Q: When did you first start using EDA tools from Concept Engineering?
I started using their tools a few years ago at the pace maker company, GateVision Pro. It was the quickest way to navigate through large Verilog netlists. We continue to use this tool here at NeuroPace to navigate our digital and analog netlists.
StarVision PRO lets us visualize our AMS designs, and it’s more efficient to use this tool compared to Virtuoso.
Q: If you didn’t have StarVision, then what would you do instead?
We would have to manually look at netlists or buy something very expensive like Encounter, which is overkill. Encounter only shows gates and blocks, there’s no transistor-level to visualize, so it’s not as easy for us to use compared with StarVision.
Q: What about IP re-use?
A large part of our designs do re-use our own IP blocks. Some blocks we do buy IP for are memories. Microcontrollers are another IP block that we buy, and then integrate into our SoC.
Q: What foundries do you work with?
A: For the lowest-power applications we are restricted to foundries like On Semiconductor which is well-know for this industry.
Summary
NeuroPace has an AMS design tool flow for the implantable electronics market, and uses a variety of EDA tools from multiple vendors. Their very low-power requirements make for a very interesting design challenge.
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This was my 30[SUP]th[/SUP] DAC and the second most memorable. The most memorable was my second DAC (1985) in Las Vegas with my new bride. We had a romantic evening ending with ice cream sundaes at midnight that we still talk about. This year SemiWiki had Dr. Paul McLellan, Dr. Eric Esteve, Daniel Payne, Don Dingee, Randy Smith, and myself in attendance so expect the best live #50DAC coverage right here, right now.
This year, for the first time, I was a DAC Speaker with my beautiful wife in the audience. I did the introduction to the Winning in Monte Carlo: Managing Simulations Under Variability and Reliabilitytutorial. My slides are HEREin case you are interested. Solido generously gave away the book: Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide to the attendees who stopped by their booth for a demo. Solido is a very clever company, believe it.
Speaking of Solido, by far the best booth promotion this year was the Solido 3D replicator manufacturing FinFETs. Hundreds of them were given away and now the engineers at Solido headquarters in Saskatoon have a new toy to play with:
On the show floor I talked to the majority of the exhibitors and found them to be pleasantly surprised at the turn out in regards to quality and quantity. I even took a look at the meeting room schedules of the companies I work with as foundry liaison and found them to be not just full but overbooked. They were doubling and tripling up demos and the customer names were very familiar to me, including my favorite fruit company. I’m a little sad that DAC is in San Francisco (my backyard) the next two years because it is good to see new places and eat new foods. The BBQ in Austin is legendary!
As I predicted the best new product at DAC was iDRM from Sage DA. People lined up to see it with two demo stations and two meeting rooms running non-stop all three days. The post DAC evaluation list for iDRM is the best (quantity and quality) I have seen in a long time.
The only DAC downside I saw was the lack of IP companies and the ones that did attend were not as busy as the EDA folks (except for ARM of course). To me this is a DAC organization problem. Semiconductor IP is critical to modern semiconductor design so let’s come up with a better IP strategy for next year.
The parties were also great this year. The venues all had good stories to tell. Monday night was the DAC party at Austin City Limits. We had VIP bracelets from Atrenta and Cadence which included great food, SpyGlass Margaritas, and perfect seats for the three band concert. You would have to pay $1k for this kind of outing so thank you Atrenta! Later we migrated upstairs to the Cadence party and my wife got an “I love DAC” tattoo on her back. Yes, my wife got a tramp stamp which was immediately texted to our kids to their horror. Tuesday night was the Synopsys press dinner at Malverde and the Denali party at Maggie Mae’s.
Sunday night we had dinner at the Driskill Hotel which is an incredible piece of history. While I worked the conference my wife had a spa day at the Hilton on Monday, a walking tour of Austin on Tuesday, and then joined me at the conference on Wednesday to meet SemiWiki subscribing companies. It was nice for her to put faces to the names she has had the pleasure to work with over the last two years. Wednesday we had a BBQ lunch at Iron Works and buffalo meatloaf for dinner at the Moonshine Bar and Grill. Our second best DAC in 30 years, believe it!
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