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Handel Jones Predicts Process Roadmap Slips

Handel Jones Predicts Process Roadmap Slips
by Paul McLellan on 01-15-2014 at 11:51 pm

At the SEMI ISS conference earlier this week, the last speaker in the technology challenges section was Handel Jones of IBS. I’ve known Handel since the mid-1980s when he came to VLSI Technology and told us we were losing money on 90% of the designs we were doing but our cost model was not good enough and so we didn’t even realize. And he was right.

Since SEMI is focused on capital equipment and consumables (wafers, chemicals, sputter targets etc) Handel focused on what he thought the capital budgets were likely to be in the coming years. But one of the things I have learned is that if you really want to know what is going on in the fabs then ask the equipment and consumables guys. Nobody orders a $100M piece of equipment they don’t need, they postpone it. Nobody orders 50,000 wafer blanks if they only need 10,000 this month. We in the semiconductor pundit segment can wonder but these guys know.

Handel has a pretty good track record of knowing too, since he talks to everyone, they are all clients of IBS.

Handel predicted higher growth in 2014. In 2013 most of the growth came from a doubling in memory prices. Unfortunately for the equipment industry, this was mostly because they didn’t overbuild capacity and have a price war, so less equipment went in. In DRAM 3 companies have 90% of the market but the technology is mature due to difficulty in plan scaling meaning that most equipment will be transitioning older fabs to 20nm. Unless there is a new breakthrough memory technology of course. In NAND flash five companies have 90% of supply. Samsung is in the strongest position and are also building a big new fab in Xi’An (China).

The area where Handel was more pessimistic than most reports is on processes coming online in the foundry industry. In particular, there is major uncertainty in the timing of 20nm, 16/14nm FinFETs and then 10nm.

The challenge is that demand for 16/14nm technology is concentrated within a small number of companies in 2016 and potentially 2017 too. Qualcomm and Apple being the two giants (and Samsung in their own fab). Below 32nm, nearly 3/4 of the demand in 2016 comes from mobile application processors and modems (or combined AP and modems) with demand for low power and low cost. High performance is only about 20% of the market.

And even more challenging, the industry is trying to adopt 3 technologies in 3 years, with 28nm HKMG in Q2/2013, 20nm HKMG in Q2/2014 and 16/14nm in Q2/2016. I actually would count that as 4 years but it is aggressive either way. Even if fabs are ready, library, IP and design implementation takes 12-24 months which the design ecosystem probably cannot support.

In processors, the market is obviously dominated by Intel who are now ramping 14nm although behind schedule. On the very day of the presentation, Intel announced they were putting fab 42 on hold and would run 14nm in the same fab as 22nm in Arizona.

TSMC is in high volume at 28nm HKMG gate last. Revenues in Q3 2013 in 28nm were $1.8B. TSMC plans to ramp 20nm in 2014 and 16nm in 2015.

Samsung is now in high volume with HKMG 28nm gate first with Apple as a large customer, as is Samsung themselves. They plan to ramp 20nm in 2014 and 14nm in 2015.

GlobalFoundries is ramping fab 8 in New York with plans to ramp 20nm and 14nm where no timing has really been announced. SMIC is getting stronger and is building a new fab in Beijing. Obviously, China’s wafer demand will continue to grow as mobile in particular expands dramatically. UMC is continuing with a follower strategy.


Handel had the latest version of his cost per gate trends which continues to show them going in the wrong direction. The only way to get costs down is to invest much more, perhaps $1B, in additional architectural and design work to get the design sizes down. So expect slowing of scaling to smaller feature dimensions. The key driver (or un-driver) is the difficulty in reducing cost per gate and cost per bit. Increasing capacity beyond a certain point does not give any economies of scale and will not give lower cost per bit, but will increase losses if fabs are not full.


Handel’s big conclusions:

  • 28nm will have a long lifetimes with opportunities for equipment vendors to expand capacity inside China
  • 20nm parametric yield will improve and it will be a high volume technology node in 2015 but mostly 2016.
  • 16/14nm will provide low cost gates with volume production only in 2017.
  • 10nm will be postponed. Cost per gate will be prohibitive and unclear where demand will come from outside high-speed processors and FPGAs.


More articles by Paul McLellan…


Positive Semiconductor Job Outlook in 2014!

Positive Semiconductor Job Outlook in 2014!
by Daniel Nenni on 01-15-2014 at 5:00 pm

Based on local traffic patterns and my experience in Silicon Valley over the last 30 years we are looking at a much higher employment rate inside the fabless semiconductor ecosystem, absolutely. Jobs are being filled more so than I have seen in the past ten years. The challenge of course is finding the right people for the right job and properly motivating them. This is critical if we want to thrive and innovate in the coming years. While LinkedIn is currently the defacto employment tool, in my mind there has got to be a better way to fill those jobs with qualified people.

“The December jobs report was an ugly mix of slowing employment growth and disappointing labor supply.” J.P. Morgan economist Michael Feroli.

Unfortunately the Bureau of Labor Statistics December jobs report does not agree with my assessment. For all of 2013, the economy added 2.2 million jobs which was on par with 2012’s gains but in December payrolls only grew by 74,000, the lowest total since January 2011. Meanwhile, the unemployment rate fell to 6.7% in December but the drop came mainly from people leaving the labor force. Hopefully this is a fluke due to the freezing weather and overly conservative holiday spending. The United States lost 8.7 million jobs in the aftermath of the 2007 financial crisis. As of January 1[SUP]st[/SUP] 2014 we have gained about 7.5 million of those jobs back.

“The Conference Board’s Leading Economic Indicators and the results from the latest survey of purchasing managers are two economic readings that suggest employment gains will rebound in the New Year.” Kathy Bostjancic, director of macroeconomic analysis.

Moving forward SemiWiki will focus efforts on a Jobs Forum in hopes of making a difference with the employment issues the fabless semiconductor ecosystem is currently facing. Just a quick survey of our 40+ subscribing companies revealed hundreds of jobs available and hundreds more opening up in the coming months. The challenge is attracting new qualified candidates and to do that we must get better at telling our story.

Joining SemiWiki in this effort is Rich Goldstein, a good friend and experienced employment professional. Recently Rich has been a contract Personnel Director of an Intellectual Property startup (Kilopass Technology), a sourcer for firmware engineers (PMC Sierra), as well as Software Developers (Xilinx), corporate EDA recruiter (Magma Design Automation), and for the better part of 2013 Rich was with AMD.

Rich and I will be writing in more detail about employment opportunities within the fabless semiconductor ecosystem in hopes of driving qualified traffic to targeted career website pages. Your feedback would be greatly appreciated as this project evolves over the next few months. Crowdsourcing wins every time, absolutely.

More Articles by Daniel Nenni…..

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International CES Wrapup

International CES Wrapup
by Bill Jewell on 01-15-2014 at 4:00 pm

Semiconductor Intelligence attended the International CES last week in Las Vegas, Nevada. A wide variety of consumer electronics devices were displayed at the conference. These ranged from:

· Fascinating – but is it practical? (personal robots, drones)
· Exciting – but when will it be cheap enough for the mass market? (UHD TV, glasses-free 3D TV)
· Potential hit – devices with near term growth prospects (wearable fitness/health devices)
· Mundane – incremental improvements in established devices (tablets, smartphones)
· Questionable – does anyone really want or need this? (Internet control of lights & appliances)

Despite the wealth of new technology introduced, the near term prospects of the consumer electronics market are weak. Steve Koenig, Director of Industry Analysis of the Consumer Electronics Association (CEA) presented the 2014 forecast by CEA and market research company GfK. The presentation is available at:

http://www.ce.org/Blog/Articles/2014/January/RESEARCH-What-Do-We-Expect-2014.aspx

CEA & GfK expect the worldwide consumer electronics market to decline 1% in 2014 measured in U.S. dollars. This follows a moderate 3% growth in 2014. The only product categories expected to show any significant growth in 2014 are smartphones (+6% vs. 27% in 2013), tablets (+9% vs. 30% in 2013) and video game consoles (+21% vs. -9% in 2013). Smartphones have been a strong growth category for the last few years, but have led to a decline in non-smart or feature mobile phones. The strong growth of tablets has contributed to a decline in PC sales. Video game console growth in 2014 is due to the introduction of the Sony PlayStation 4 and Microsoft Xbox One in late 2013. Despite the advances in LCD TVs such as Ultra High Definition (UHD or 4K) and glasses-free 3D, overall LCD TVs are expected to decline 2% in 2014 after 3% growth in 2013.

In terms of regions, developed countries (U.S., Western Europe, Japan, South Korea, Taiwan, etc.) are forecast by CEA/GfK to see a 4% decline in consumer electronics sales in 2014 after a 2% decline in 2013. Developing countries (China, India, Latin America, Eastern & Central Europe, Russia, Middle East, Africa, etc.) should grow 2% in 2014, a significant slowing from 9% in 2013. According to CEA, developed countries accounted for 60% of consumer electronics sales in 2010. The percentage is expected to decline to 50% in 2014 and continue to decline in future years.

Two of the emerging consumer electronics devices we focused on at CES were Ultra High Definition (UHD) TV and wearable devices for health and fitness. Although these two categories have potential to drive growth in consumer electronics in the future, what is the near term outlook?


All of the major TV suppliers displayed UHD TVs with screen sizes of 85 inches (diagonally) and up. Several UHD TVs are available on the market.
Bestbuy.com lists major brand UHD TVs at about $5,000 for 65 inches and $3,000 for 55 inches. By comparison, HDTVs sell for about $1,500 for 65 inches and $750 for 55 inches. The high prices and limited UHD content will limit sales to early adopters for several years. IHS Inc. expects UHD TV sales to hit 10 million units in 2014, up from 1.5 million in 2013. Sales are forecast to hit 38.5 million units in 2018, but will be only 16% of the total LCD TV market.

Wearable devices should have near term impact on the consumer electronics market. Fitness and health are the major drivers of wearable devices. The 2014 market for wearable devices is expected to be about $5 billion. Forecasts for the 2018 market size range from $13 billion from
BI Intelligence to $35 billion from the Industrial Economics and Knowledge Research Center (IEK). Wearable devices are a new area of consumer electronics and should drive growth without displacing sales of other electronic devices.

More Articles by Bill Jewell …..


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MIPI Alliance Specifications Adoption Status in 2013

MIPI Alliance Specifications Adoption Status in 2013
by Eric Esteve on 01-15-2014 at 11:00 am

At the beginning of December in Paris I had the opportunity to make a presentation to a very impressive audience, technical gurus from companies contributing to MIPI Alliance specification were here, including ST-Microelectronics, Intel, Qualcomm, TI, Toshiba, Nokia, Samsung, to name a few.


Continue reading “MIPI Alliance Specifications Adoption Status in 2013”


Is Intel the Concorde of Semiconductor Companies?

Is Intel the Concorde of Semiconductor Companies?
by Daniel Nenni on 01-15-2014 at 8:00 am

An Intel executive recently told me that my Intel articles on SemiWiki are used to motivate employees to work hard and prove me wrong. The converse is also true. The senseless Intel fabless ecosystem bashing motivates me to continue to write so it is a win-win scenario, absolutely. In fact, I should credit Intel’s Mark Bohr for motivating me to write a book chronicling the great and powerful fabless semiconductor ecosystem, but I won’t.

At the SEMI ISS conference this week there were some excellent presentations filled with important market data. Most of which I already knew but seeing it all in one place with a historical perspective was well worth the price of admission. And networking with industry executives from around the world is priceless. I had lunch with David K. Lam, founder of famed semiconductor equipment manufacturer LAM Research. How cool is that!?!?!

Unfortunately, I do not have permission to post the slides so I will summarize the best I can:

The Concorde reference is from the keynote by Rick Wallace, President and CEO of KLA-Tencor. The point being that the Concorde failed not because of technology, it failed because of economics and lack of competition, adding that Moore’s law is much more likely to die in the board room than the manufacturing floor. This is absolutely true.

In my biased opinion, that is Intel’s problem exactly. The laws of physics will not defeat Intel, the natural laws of economics and inflated egos from lack of competition will. BK (Intel’s CEO) said it all with his latest quote, “We will not get into a price war with TSMC”. News flash: TSMC is not your competitor, Samsung is and they are going to eat your economic lunch, absolutely. Just ask Apple.

Bill McClean, President of IC Insights, had the most informative slides which I will use to support my anti Intel bias:

World Wide Semiconductor Sales in 2013:

[LIST=1]

  • Intel $48.3B
  • Samsung $33.6B
  • TSMC $19.8B
  • QCOM $17.1B
  • Micron $14.1B

    It is interesting to note that TSMC revenue surpasses Intel if you do an apple to apple comparison using the final market value of the chips TSMC manufactures. That would be the price TSMC customers sell their chips for.

    Top 10 IC Foundries in 2013:

    [LIST=1]

  • TSMC $19.9B
  • GLOBALFOUNDRIES $4.3B
  • Samsung $4.0B
  • UMC $3.9B
  • SMIC $2.0B
  • PowerChip $805M
  • Vanguard $712M
  • Grace $710M
  • Dongbu $570M
  • Tower Jazz $509M

    TSMC again posted double digit gains as did Samsung. SMIC is the real winner in 2013 with a 28% gain. I would attribute this to home court advantage in the China semiconductor market. Notice the 4.6x gap between #1 and #2 and the 39X gap between #1 and #10. TSMC’s lead will continue to grow in 2014, definitely.

    Top 10 CAPEX Spenders in 2013:

    [LIST=1]

  • Samsung $12B
  • TSMC $11.2B
  • Intel $10.5B
  • GF $5.5B
  • SK Hynix $3.7B
  • Micron $3B
  • Toshiba $2.9B
  • UMC $1.5B
  • Infineon $880M
  • ASE (OSAT) $770M

    Yes, Samsung and TSMC both outspent Intel. Just wait until you see the capacity numbers and you will know why.

    Top 10 IC Wafer Capacity Leaders in 2013:

    [LIST=1]

  • Samsung 12.6%
  • TSMC %10%
  • Micron 9.3%
  • Toshiba 8%
  • SK Hynix 7%
  • Intel 6.5%
  • ST 3.5%
  • UMC 3.5%
  • GF 3.3%
  • TI 3.0%

    The majority of Samsung’s capacity is memory. Intel also has memory in there so if you only look at logic capacity (SoCs) TSMC is the clear leader by a very large margin.

    The question I most commonly get asked (other than people asking for my autograph): Is Intel serious about the foundry business? My answer unfortunately has not changed in the last year. No, Intel is not serious about the foundry business. It is a head fake to appease investors and make waves in the industry, just my opinion of course. Let’s hope the Intel Foundry team proves me wrong.

    More Articles by Daniel Nenni…..


  • The State of 450mm Wafers. And Intel Gossip

    The State of 450mm Wafers. And Intel Gossip
    by Paul McLellan on 01-14-2014 at 11:55 pm

    Paul Farrar, the General Manager of the Global 450mm Consortium (G450C) presented at the SEMI ISS conference today. What is G450C, it is a public-private consortium to develop a cost-effective 450mm wafer fabrication infrastructure, develop equipment prototypes and coordinate the industry move to 450mm. It is located in Albany New York and its main partners are Intel, TSMC, Samsung, GlobalFoundries, IBM and the state of New York. The current plans call for work to take place over the next 3 or 4 years and be ready for volume manufacturing in 2018 or 2019. At the end of last year they had 41 450mm tools either in Albany or at partner companies or at suppliers (tools just means pieces of equipment like a stepper). They have a 45,000 square foot clean room.

    Paul reported on the detailed status of various steps in wafer fabrication. Mostly things are going well for this stage in development. One area that is a challenge is lithography where performance and cost are key. Since a stepper only exposes one die at a time, there is less of a direct gain from 450mm than for other tools such as CVD that work a whole wafer at a time. There is a little saving in wafer handling. By way of an example Paul pointed out that normalizing to 1 at 200mm in 2003 when 300mm was finally introduced, initial introduction had lithography at 1.32 times as fast and 5 years later at 2.15 times as fast. So there is learning to be done. G450C has access to a prototype immersion stepper at Nikon and will get their own in the first half of 2015.

    One thing that was not planned originally for 450C is notchless wafers. But it makes handling those big wafers a lot easier if they are not unbalanced when they are spun and generally processed. Instead, fiducial marks are put on the back of the wafer and used to align to all the equipment. This also has the advantage of giving an extra 1.5mm at the edge of the wafer, which on a big wafer like that is worth having. One questioner suggested that getting an extra 1-2% yield on 300mm wafers would make retrofitting current 300mm lines attractive.

    During dinner I sat next to a guy who supplies wafer blanks. They had a 450mm program a couple of years ago but they canceled it since they don’t think 450mm is going to be real and for them, in any case, it is impossible to make money. Just 3 years ago a 300mm blank wafer sold for $280 but today it is just $60-70 and foundries expect the same price per square inch for 450mm. Since there are only a handful of fabs that will make the 450mm transition, they have very strong bargaining power. He reckoned that only now are equipment manufacturers finally in the black on 300mm having started development in about 1990, it took 20 years. The return for 450mm is also expected to take over 20 years. But nobody knows what 450mm equipment will be needed in 20 years time since we don’t know the basic technology. Depending on what happens with EUV there is also a race: manufacturing will not introduce EUV and 450mm at the same time, or probably even a new process. EUV or 450mm will be retrofitted to an existing process already ramped to volume.

    Other pieces of gossip from people at my table at dinner. Intel isn’t worried about 450mm right now, they have bigger problems. They have apparently said that they will not use EUV for manufacturing until there is technology to put a pellicle on the mask (to keep it clean and keep contaminant out of the focal plane, but almost all pellicle materials absorb EUV). Intel’s fabs are 70% utilized. Their big challenge in mobile is that the price point for tablets and smartphone chips is below Intel’s variable cost, so the more they make the more money they lose.

    And not a piece of gossip, Intel announced today that they are putting fab 42 in Chandler Arizona on hold and will use it for future technology. They will still run 14nm in Arizona but sharing the 22nm fab to save cost.


    More articles by Paul McLellan…


    Technology Challenges: Intel, IBM, Xilinx, GlobalFoundries, IMEC

    Technology Challenges: Intel, IBM, Xilinx, GlobalFoundries, IMEC
    by Paul McLellan on 01-14-2014 at 7:00 pm

    I spent the day at the SEMI Industry Strategy Symposium in Half Moon Bay. The early part of the day was devoted to technology challenges. Obviously everyone did not say exactly the same things, and had a little bit of a different spin depending on what business they are in. But there was a lot of commonality between Intel, IBM, Xilinx and GlobalFoundries. There were also presentations by the Global450mm Consortium and from Handel Jones of IBS. I will cover what they said in separate blogs later in the week.

    Firstly, everyone pretty much agrees that there are no insurmountable technical challenges getting to 7nm. We know how to do it. Or at least we know what we have to do to get there, and it is engineering rather than basic research.

    However, everyone agrees there are economic challenges in the sense that the costs of wafers are going up so fast that they overwhelm the savings that we get from increased scaling and as a result the cost per transistor is at best flat or at worse rising. Of course we get lots of other good things from the new process generations, such as reduced power, increased circuit complexity, increased performance. But, as I’ve said many times before, we don’t get a reduction in cost. If you are cost sensitive then 28nm still looks like the best process if you can get away without needing the features that only come from 20nm and below. Many of the speakers expressed confidence that the cost challenges would be addressed and we would get back on the nirvana of Moore’s Law but there was little hard data to back this up.

    There was a healthy skepticism about EUV lithography. The source light is currently around 50W and 250W is required for it to be economic to use. Defect density on masks (remember these are actually multi-layer mirrors) is about 100 per mask and needs to be under 10 to make it feasible to take corrective measures.

    Everyone agreed that stacking technologies of all kinds that allow us to get into the 3rd dimension will be increasingly important. Memory stacks, organic interposers, glass interposers, silicon interposers, and true 3D SoC (where a whole design is partitioned onto multiple die).

    Michael Mayberry of Intel talked about Delivering Complexity to the Leading Edge. His basic premise was that we have to suck up the complexity in order to deliver simple user experiences. For example, a modern process (I think he was talking about 14nm) there are a billion transistors per square centimete (or 100 billion memory bits) and that requires 60 billion features across the design process and, in turn, with the complex RET needed for lithography, that is a trillion mask features across the mask set.

    The big challenges are:

    • granularity (when you can count the atoms everything is granular)
    • size is limited by electrical behavior
    • voltage scaling limited by mobility
    • interconnect limits performance

    Bryan Rice of GlobalFoundries talked about The Foundry Answer to Technology, Cost and Moore Scaling. His list of challenges was:

    • device architectures and scaling: FDSOI, FinFETs, nanowires, III-V materials
    • litho/EUV: cost, multipattern immersion, EUV power source, tool availability
    • packaging: normal economics are dead, value proposition moving to PPC, alternatives
    • 450mm: G450 Consortium, driven by immersion initally, EUV later

    Ivo Bolsen discussed Programmable Platforms Essential to Leverage Further Logic Scaling. He talked less about process details but did talk a lot about 3D packaging where Xilinx is one of the leaders with a family of interposer-based parts already in production. But his bigger point was that the building blocks need to get bigger and, increasingly systems need to be designed in a hardware/software neutral way and automatically put into the fabric. His bet is OpenCL which allows designs to be compiled into code that runs in the normal software eocsystem (ARM etc) and accelerators that are automatically created in the FPGA fabric to handle the algorithms where power or performance mean that it cannot simply be implemented in software.

    An Steegen of IMEC talked about Scalling Beyond 10nm. She ran through so many technologies where IMEC is doing research, some of which I had never heard of such as spin wave devices. But her big point was that there are three types of scaling going on: lithography enabled scaling, materials and device architecture scaling, and 3D enabled scaling.

    Jon Casey of IBM focused on big data, System Scaling Technologies and Opportunities for Future IT Workloads and Systems. His big point was that a huge amount of power is dissipated just moving data around. Systems needed to get smaller so that less power was wasted and data could move faster and this means stacking chips, interposers and memory stacks (IBM is partner with Micron on the HMC). This is what he termed volumetric scaling.

    So a huge amount of overlap. I’m still not convinced that we have any idea how to get back on the cost curve, or that EUV is going to work. But I’m pretty certain that 2014 and 2015 is going to be the year of 3D.


    More articles by Paul McLellan…


    Things to do in Denver when you’re 64-bit

    Things to do in Denver when you’re 64-bit
    by Don Dingee on 01-14-2014 at 4:45 pm

    When Apple announced last September their A7 chip had gone 64-bit, the congregation immediately swooned, but analysts reacted skeptically: “So what? Phones don’t need more memory, and there are no 64-bit apps.” Even pundits miss once in a while, and now the topic is how the chip industry is headed for 64-bit.

    Continue reading “Things to do in Denver when you’re 64-bit”


    Why SOI is the Future Technology of Semiconductor

    Why SOI is the Future Technology of Semiconductor
    by Eric Esteve on 01-14-2014 at 8:34 am

    No doubt that FDSOI generate high interest these days and I found a very interesting contribution from Zvi Or-Bach, President and CEO of MonolithIC 3D, Inc. Zvi has accepted to share his wrap-up from IEDM, in a blog for Semiwiki readers. If you remember the long discussion we had in Semiwiki about cost comparison, some comments were posted Continue reading “Why SOI is the Future Technology of Semiconductor”


    Xilinx, the University of FPGA

    Xilinx, the University of FPGA
    by Luke Miller on 01-13-2014 at 8:00 pm

    More than ever, FPGA training is the key to success. Which is why Xilinx, provides free, no charge video’s that can speak to the seasoned FPGA designer or to the interested community. These Videos are not like your high school graduation taped by Uncle Frank. These are detailed, professionally edited Xilinx Videos that will give you an education and a taste for Xilinx FPGAs that you would have thought would eat into expensive training budgets. Something in the engineer’s soul lights up when the word free is spoken!

    Do not let me confuse you with the facts, but these videos are to supplement training. But you know as well as I do, in this day in age, training unfortunately is getting fickle. Usually after the coffee club, and water cooler budget, the training budgets are the next in line to be challenged. In the meantime, it is up to you to stay current, which means, even going to a ‘lunch and learn’, I know. The other name for that is you train on your own time. My friend, I therefore would like to point you into this direction, to this valuable link on Xilinx:

    While there is no shortage of Xilinx FPGA hacker videos (you can find me building a 1953 Nixie Tube Speedometer) they do not always have the correct foundation that Xilinx is going to provide. This is obvious but Xilinx as the designer of World Class Programmable Devices is going to have the best and most accurate content. Once you have watched the videos, start poking around for more videos from other sources and then learn the tricks of the trade after the foundation is laid.

    So I suggest, Mr. Dad or Mrs. Mom, Grab the family and it’s time for family movie night! What engineer would not want to share this time with his or her family? The kids are always asking, ‘What do you do at work?’ We’ll now’s your chance to wow them! OK, this is a bit of fiction, but may I recommend some of my favorite Videos from the Xilinx Video Library, and they are… Wait, know what would really be cool, is if Xilinx used its own technology to stream and compress these videos and then up covert the stream to a 4k display. Anyways the video list, drum roll…

    The heart of most Xilinx FPGA Designs, the DSP and how to get your design done and signed off faster than ever!
    Accelerating DSP design productivity with Xilinx

    Ever wonder how Xilinx FPGAs support the automotive industry? This is an Oscar Contender.
    Automotive market segment overview

    Zynq, is nothing short of a huge success. This video answers the following question:
    Why Zynq?

    This short video highlights the overall challenges faced by the industry and how traditional solutions are addressing them, and why a new category of devices such as Zynq is needed. It will also briefly review the overall Zynq-7000 platform offering and the values that these devices bring to designers.

    In the time to come we can expect videos featuring 20nm UltraScale and then 16nm. Go make your popcorn, extra butter and get ready!

    More articles by Luke Miller…

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