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IC Implementation Tool Gets a Rewrite, Now 10X Faster

IC Implementation Tool Gets a Rewrite, Now 10X Faster
by Daniel Payne on 03-24-2014 at 10:05 am
Categories: EDA, Synopsys

EDA start-up companies often have the advantage over established vendors by being able to start from scratch, instead of having to maintain some legacy code that no longer is competitive. But what happens when the established vendor decides to rewrite their IC implementation tools from scratch? In this case it’s good news, because Synopsys has just announced a rewrite of their popular IC Compilerand have dubbed it IC Compiler II. I talked with Saleem Haider of Synopsys earlier this month by phone to get briefed about it.


Continue reading “IC Implementation Tool Gets a Rewrite, Now 10X Faster”

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How Students Can Attend DAC for Free

How Students Can Attend DAC for Free
by Daniel Payne on 03-23-2014 at 11:29 am
Categories: EDA, Events

The annual Design Automation Conference (DAC) is a big deal and should be of interest to students considering a career in developing software to help automate some of the toughest design and verification challenges in SoC design. Maybe the cost of attending and traveling to DAC is an issue for you. The organizers of DAC are continuing their Young Student Fellow Program, where students thinking about joining the EDA field or taking graduate studies can apply to attend DAC for free.

Dr. A. Richard Newton was the dean of the University of California, Berkeley College of Engineering and was very involved in the history of EDA, so the program has been named in his honor: Richard Newton Young Student Fellow Program. In 2013 some 56 students were sponsored as part of this program to attend DAC.

At DAC

Should you be selected, then at DAC you will participate in the following six events:

[LIST=1]

  • A kickoff meeting on Tuesday at the first speaker’s breakfast.
  • Attend several conference sessions, plus the sessions for Best Paper Award nominations.
  • A poster presentation to introduce each Fellow, part of the DAC student event.
  • Awards session.
  • The closing session, part of the Thursday evening reception.
  • Tell your social network what’s happening at DAC.

    Am I Eligible?

    What’s the catch? Since there are a limited number of awards, there is a preference for this program:

    • Working towards a Masters Thesis in Engineering, junior or senior undergraduate.
    • Women and minorities.
    • PhD students in the first two years of a doctoral program.

    How to Apply

    Visit the DAC web pageto apply by April 4th, 2014 and then wait for your notification. You’ll have to write a 1-2 page description about your interest in EDA, describe your courses or projects, share a link to your website, and provide a travel expense estimate.

    I hope to see you at DAC, June 1-5 in San Francisco.

    lang: en_US

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    The CAD Team – Unsung Heroes in a Successful Tapeout

    The CAD Team – Unsung Heroes in a Successful Tapeout
    by Daniel Nenni on 03-23-2014 at 11:00 am
    Categories: Cliosoft, EDA

    For most of my career, I worked as a CAD and design flow engineer. In the fall of 2012, I moved to a different role, as an applications and support manager at ClioSoft Inc. In my opinion, this was a very good opportunity for me to work with other CAD engineers and teams.

    Having worked with different CAD teams in my career, I have often felt that the CAD engineers do not get the credit that they richly deserve for the effort they put in. Most CAD engineers did not plan on being CAD engineers when they graduated from college. What moved them in the direction of CAD is the “discovery” that they had an excellent understanding of UNIX, design methodology and programming and also had good communication skills.
    In the semiconductor industry, the CAD/EDA engineers wear a number of hats during the course of a project. Sometimes they don the role of a system administrator, where they predict and provision compute resources for a project or, depending on the size of a company, even help in tasks such as setting up simulation farms for the project. With the growing number of geographically dispersed design centers, and the ever-increasing size of the design data, good network access speed and efficient utilization of disk space becomes a top priority for designers working remotely. In addition, there is growing concern about controlling access to sensitive data when it crosses national boundaries. CAD teams often work very closely with IT solution providers to provide the best-suited solution.

    The CAD team also interfaces between the design teams and EDA vendors to evaluate the design tools that ensure that correct tools are set up for the design project. Their deep understanding of design flows and scripting capabilities help them set up and automate the flows for the design project to ensure that the tapeout happens smoothly. And at times CAD engineers have also stepped into the trenches to help with design implementation.

    If you think of the design team as the offence, the CAD engineers are the defense. No matter how good the offence is, it needs to be backed by a good defense to win the game. CAD engineers rarely get the glory, but as the Super Bowl recently proved yet again: defense wins championships. So the next time you bump into a CAD engineer, remember to give him a pat on the back.

    Author: Amit Varde, Applications and Support Manager, ClioSoft

    About ClioSoft:
    ClioSoft is the premier developer of hardware configuration management (HCM) solutions. The company’s SOS Design Collaboration platform is built from the ground up to handle the requirements of hardware design flows. The SOS platform provides a sophisticated multi-site development environment that enables global team collaboration, design and IP reuse, and efficient management of design data from concept through tape-out. Custom engineered adaptors seamlessly integrate SOS with leading design flows – Agilent’s Advanced Design System (ADS), Cadence’s Virtuoso® Custom IC, Mentor’s Pyxis Custom IC Design, Synopsys’ Galaxy Custom Designer and Laker™ Custom Design. The Visual Design Diff (VDD) engine enables designers to easily identify changes between two versions of a schematic or layout or the entire design hierarchy below by graphically highlighting the differences directly in the editors.

    Also Read

    Cliosoft Grows Again!

    High Quality PHY IPs Require Careful Management of Design Data and Processes

    ClioSoft at Arasan

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    Synchronizer Reliability Metrics

    Synchronizer Reliability Metrics
    by Daniel Nenni on 03-23-2014 at 10:00 am
    Categories: EDA

    As an example of the need for real-world reliability metrics, consider a modern automobile. We can already buy a car with parking assistance, collision avoidance, autonomous braking and adaptive cruise control features. These new features depend on video image processing that requires high-performance SoC components where multiple clock domains are certain to be required. How will the synchronizers used in the clock domain crossings (CDC) be qualified for this safety-critical service? Will it be MTBF (Mean Time Between Failures) and if so, what is the minimum MTBF required for an SoC that is installed in a million automobiles? If not MTBF, exactly what metric is appropriate to insure the safety


    As we have seen in a previous blog post, data or control that passes between two clock domains having incoherent phase or frequency cannot be accomplished in a way that completely avoids synchronizer failures. Thus, it is essential to determine the probability of failure of a system to ensure it is low enough to be an acceptable risk to the user. MTBF does not explicitly take into account the number of units in the field or the length of time a unit is in service. Another common reliability metric, FIT (Failures In Time) is the inverse of MTBF (when both have consistent units). Hence, FIT – a metric that is usually measured in failures in a billion hours – is also inadequate.

    A measure that determines the probability that all units in the field perform safely throughout the unit’s lifetime seems more prudent for safety-critical applications. Such a metric can be called Pr(safe). In the case of N units in the field with an average lifetime of L we can say

    where the MTBF is calculated for all CDCs in the SoC. This seems simple enough and is an improvement over MTBF or FIT.

    There are, however, other considerations that must be discussed for high-volume, consumer products such as automobiles. Does the variability in settling time-constants both within a chip and between chips need to be considered? What about the variation in the lifetime of an automobile? To a first order the mean settling time-constant and mean lifetime produce good estimates of Pr(safe) so long as the number of units is large. In contrast, for low-volume products, some safety margin must be included to allow for unfortunate sampling of the random distribution of transistor threshold voltages, an important determinant of synchronizer reliability. It is important to remember that CDC errors due to metastability can occur at anytime, immediately after fab or not until the end of a product’s life. Simulation is the only way to anticipate these rare occurrences.

    Since it is not possible to eliminate all synchronizer failures, it is essential to mitigate the effects of such failures. There are well-known techniques to accommodate the one-clock-cycle uncertainty that accompanies synchronization in a CDC. On the other hand, the uncertainty that occurs when an invalid logic level is delivered to more than one destination is much more problematic. Such a situation can lead to invalid sequences or states with unpredictable consequences. As the fan- out of the invalid logic level grows, the complexity of anticipating all possible cases grows exponentially. Thus, it is best to reduce CDC errors by careful synchronizer design. To do so it is important to have accurate characterization of the synchronizers to understand how well, or poorly, they perform. After good synchronizer design is complete, one can then work on ways to mitigate the effects of CDC errors that are known and understood. In these cases and on those extremely rare occasions when these errors do occur, there will be no risk of bodily harm.

    In verification and before sign-off the reliability metric, Pr(safe), can be revisited to estimate how the well the final design will perform in real-world production circumstances.

    By Jerry Cox, CEO Blendics

    lang: en_US

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    Top 10 Reasons to Use Vivado Design Suite

    Top 10 Reasons to Use Vivado Design Suite
    by Paul McLellan on 03-23-2014 at 7:05 am
    Categories: FPGA, Xilinx

    Here are the top 10 reasons to use the Xilinx Vivado Design Suite to design your All Programmable Devices:

    Reason number 10: Accelerate verification by over 100XThe Vivado Design Suite System Edition lets you do design at the C, C++ or systemC level. But a side-benefit is that you can use these languages for verification at performances much higher than using raw RTL. Maybe 10,000X faster.


    Reason number 9: Comprehensive hardware debugVivado Design Suite’s probing methodologies are intuitive and flexible. Designers can choose a strategy that best suits their design flow using RTL design files, synthesized design and XDC constraint file. Or netlist insertion. Or interactive Tcl or scripts to automate probing.

    Reason number 8: Vivado IDE for design and simulationThere is a complete, fully-integrated set of tools for design entry, timing analysis, hardware debug and simulation encapsulated in a state of the art integrated design environment (IDE).

    Reason number 7: Block based IP integrationVivado IP integrator is the industry’s first plug-and-play IP integration design environment. This provides a graphical and Tcl based correct-by-construction design flow.

    Reason number 6: Model-based DSP design integrationUsing System Generator for DSP, the industry’s leading high-level design tool for converting DSP algorithms into production quality hardware. It interfaces to the industry’s quasi-standard modeling tools, MATLAB and Simulink (from Mathworks).

    Reason number 5: High level synthesisVivado High Level Synthesis takes C, C++ and SystemC and automatically converts it into Verilog or VHDL for further synthesis. This previously somewhat esoteric technology is now completely mainstream with hundreds of users.

    Reason number 4: Performance, performance, performanceMuch faster run-time than the competition. Multiple compilations per day even on huge designs. Much smaller memory footprint than the competition.


    Reason number 3: Robust performance and low powerInterconnect is now the performance bottleneck in modern programmable-logic devices. The place & route algorithms in Vivado break this performance bottleneck to deliver high performance results at the push of a button. Higher performance than the competition. It also delivers lower system power.

    Reason number 2: Fit more into the device, fasterA tool’s ability to fit more functions into an All Programmable device directly translates into savings in system-level cost and power by letting you select the smallest device for your design. The advanced fitting algorithms combined with the architecture of the Xilinx 7 devices allow nearly 100% utilization to be achieved whereas competing devices on the same benchmark top out at 67%, meaning a larger and more expensive device would be required.


    And the number 1 reason for using Vivado Design Suite:That is how you get your hands on Xilinx’s All Programmable devices. Because like in those old Visa ads, they don’t take American Express.

    A full white-paper that dives deeper into each of these reasons is available here.


    More articles by Paul McLellan…

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    Mentor Acquires BDA!

    Mentor Acquires BDA!
    by Daniel Nenni on 03-23-2014 at 7:00 am
    Categories: EDA, Siemens EDA

    Mentor Graphics acquired Berkeley Design Automation this morning. The details of the deal were unannounced. This is a strong move by Mentor to challenge Cadence and Synopsys in the nanometer analog/mixed-signal market and nanometer memory characterization market, respectively. Mentor not only acquires the technology and team, but BDA’s list of blue-chip leading-edge customer engagements including the likes of Qualcomm, Samsung, Sony, Fujitsu, Broadcom, TSMC, and NXP.

    BDA established itself in the mid-2000’s by solving circuit verification problems that no other EDA company could solve—problems like silicon-accurate device noise analysis on an entire post-layout closed-loop integer-N and fractional-N PLLs, high-speed I/O, and ADCs—while co-simulating with a standard Verilog simulator. (It hurts to even think of problems like this). (See Silicon Correlation)

    BDA built its business by literally asking leading-edge analog/mixed-signal (A/MS) design teams for the problems that no other simulator can handle and providing the solution. BDA would then move “downstream” to run circuit simulations that other simulators could run, but BDA’s Analog FastSPICE simulator would run them 5x-10x faster than any other foundry-certified simulator. They take the same approach to this day. (See BDA History)

    Customers and industry pundits alike give BDA credit for sending a loud-and-clear wakeup call to Cadence and Synopsys. Cadence responded with APS, which AFS continues to beats by over 2x in runtime and 10x in capacity. Synopsys tried XA with little success, and later bought Magma for FineSim. While FineSim is fast, it’s not nearly accurate, robust, or feature-rich enough for advanced A/MS circuits. Moreover, FineSim is not well integrated into Cadence’s Analog Design Environment, which is a must-have to compete with Cadence for “real” A/MS design team. Meanwhile BDA recently announced AFS Mega which brings SPICE accuracy memory application, and announced TSMC has adopted it for all of their 16nm FinFET SRAM characterization. (See TSMC and BDA)

    In apparent effort to slow or stop BDA, last spring Cadence hit them with a lawsuit regarding AFS integration into ADE. (See Cadence vs. BDA) There was immediate overwhelming customer support for BDA, and the case was dismissed with prejudice earlier this year. The undisclosed settlement agreement gives BDA a multi-year ADE integration with ADE, where standard Cadence Connections members have to renew annually.

    With this move Mentor is suddenly not just on the map, but arguably takes a substantial technical lead nanometer-scale circuit verification. Mentor removes the small-EDA company barriers that BDA continuously faced and get them immediate access to the broad semiconductor market. Look for Mentor to couple AFS with Questa in the front end to take on AMS Designer and to couple AFS with Calibre in the back-end to create highly-differentiated flow to silicon.

    Congratulations to everybody at BDA on the great exit. It was a pleasure working with you!

    More Articles by Daniel Nenni…..

    lang: en_US

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    DAC: Automotive, IP and Security

    DAC: Automotive, IP and Security
    by Paul McLellan on 03-21-2014 at 5:18 pm
    Categories: EDA, Events, IP

    DAC is in the first week of June in San Francisco as I’m sure you already know if you are reading this. Historically DAC has focused on electronic design automation (EDA) and embedded software and systems (ESS). This year there are three new areas: automotive, Intellectual Property (IP) and security.

    Automotive
    Ever increasing feature content enabled by electronics and software and the associated complexity has made development of automotive electronics and software amongst the largest challenges for the automotive industry. Today, the functionality, efficiency, time-to-market, cost, quality, safety, and security of a new vehicle are determined more by embedded systems and software than by any other factor. The Automotive Track is a new, unique forum addressing design automation and design methodologies to enable automotive designers and integrators to meet their unprecedented challenges.

    There is a dual keynote Automating the Automobileby Henry Buczkowski, the Henry Ford Technical Fellow at (surprise) Ford Motor Company and Jim Tung, Mathworks fellow at (surprise again) Mathworks.

    IP
    This year DAC introduces the IP Track on Monday, focused on semiconductor IP. This track includes six sessions running in two rooms adjoining the exhibit floor, and provides creators and users of IP with an open forum to exchange information on state-of-art IP products and the tools and methodology to create, incorporate and validate IP in SoCs. Supporting the IP technical track is the exhibition floor which includes over 20 leading IP suppliers suppliers and providers.

    The associated keynote is The Great SoC Challenge (IP to the Rescue!)is by Sir Hossein Yassaie, CEO of Imagination Technologies.

    Security
    As design of integrated circuits (ICs) and embedded systems is increasingly global, designers and users of ICs, intellectual property (IP) and embedded systems are increasingly facing trust issues. These systems are vulnerable to a variety of hardware-centric attacks, such as side channel analysis, reverse engineering, IP piracy, hardware Trojans and counterfeiting. The Security Track at DAC highlights the emergence of security and trust as important dimensions of hardware and embedded systems design, dimensions that must be considered side-by-side with power, performance, and reliability.

    The security keynote The Intel Security Architecture Visionis by Ernie Brickell, Chief Security Architect at Intel.

    The technical program for DAC will be announced on March 27th, next Thursday. Details about DAC are on the (all new) DAC website at dac.com.


    More articles by Paul McLellan…

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    SEMI Breakfast Forums: the Internet of Things

    SEMI Breakfast Forums: the Internet of Things
    by Paul McLellan on 03-21-2014 at 4:29 pm
    Categories: ESD Alliance, Semiconductor Services

    Coming up on April 10th is the SEMI Silicon Valley Breakfast Forum Internet of Things—Driving the Microelectronics Revolution. It runs from 7am to 10.45am and will be held at SEMI Headquarters which is at 3081 Zanker Road in San Jose.

    Widespread adoption of the Internet of Things will take time, but the movement is advancing thanks to improvements in underlying technologies. New processor architectures, interfaces, and memory structure are improving efficiency and density while enabling smaller and lower-power applications.

    With the potential to impact all aspects of society and our lives, now is the time for executives across all industries to think strategically about the opportunities likely to emerge from an intelligent and connected world.

    There is no such thing as a free lunch at the forum but at least there is free continental breakfast from 7-8am. I love that phrase since we are on the continent of North America but continent referred to in the breakfast is Europe.

    Denny McGuirk, President of SEMI will welcome everyone at 8am.

    The main speakers are:

    • At 8.05 Karen Bartleson who, in addition to working at Synopsys (and beating my EDAgraffitti blog in 2009 in Denali’s America’s Next Top Blogger grrr), is also President of the IEEE Standards Association
    • At 8.40 Alfonso Velosa, a research director at Gartner where he focuses on ecosystem relationships for IoT, smart cities and electronics.At 8.05
    • At 9.00 Mike Rosa, who works within the 200mm systems group at Applied Materials. He focuses on new and emerging technologies, especially MEMS (which is an important component of IoT)
    • At 9.20 there will be a 20 minute networking break
    • At 9.40 Kerry McGuire Balanze, who is vice-president of strategy for the IoT business unit of ARM
    • At 10.00 there will be a panel discussion until 10.45 when the meeting will wrap-up

    Details, including links for registration, are here. Early bird registration ends on March 27th so hurry.

    The Arizona Breakfast Forum, also Internet of Things, is on April 17th at Intel’s Ocotillo Campus building OC2 at 4500 South Dobson Road. It starts at 7.30am. Speakers are from TIRIAS research, Semico Research, Medtronic, Freescale and Intel. Full details and registration (early bird for this one ends on April 4th) is here.

    Then the Texas Spring Forum How the Internet of Things Will Impact New Manufacturing Solutions is on April 22nd at Intel Austin, 1300 South Mopac Expressway. It also starts at 7.30am. Speakers are from Freescale, Cisco, ARM, Brewer Science, Applied Materials and Intel. Full details (early bird ends April 15th) are here.


    More articles by Paul McLellan…

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    Evaluate MEMS Devices out-of-fab Before Fabrication

    Evaluate MEMS Devices out-of-fab Before Fabrication
    by Pawan Fangaria on 03-21-2014 at 10:30 am
    Categories: Coventor, EDA

    MEMS design and fabrication is highly complex in the sense that the fabrication process heavily depends on the design, unlike IC fabrication which has a standard set of processes. A slight change in MEMS design can alter its fabrication steps to a large extent. For example, setting device parameters such as capacitance or linear displacement can affect the choice of the film thickness, etch rate, sidewall profile and so on. The design and process are so much tied together that many iterations through the fab are required (which consume costly resources and time) in order to get a perfect build. While an IDM has to keep its fab resources deployed for such a build-and-test experimentation in-house, a fabless design house has to additionally incur time for its design to take several tours through an external fab. This all has significant impact, first on cost of design and manufacturing and then turn-around-time, thus squeezing the window of opportunity which is already small in today’s competitive semiconductor market.

    In such a scenario, there is nothing like having a software tool at the designer’s desk which can provide a 3D model of the complete MEMS device based on its layout and process description. The iterations between the design and the process can take place virtually at the terminal itself until the final model of the device is perfect to enter the fab for manufacturing.

    I am impressed with the SEMulator3D Virtual Fabrication Platform from Coventorwhich simplifies this build-and-test cycle for MEMS in the most economical and fastest way through its Voxel Modeling Engine and virtual metrology operations for measurement of critical technology parameters. Above is an example of RF Tunable Capacitor model derived from its layout and process behavior, which has its actuation part in silicon wafer (black block on top) bonded on the RF part in glass wafer (yellow and white block at bottom).

    How do you describe the process and metrology steps through the process editor? Above is the edited process file for the RF Tunable Capacitor. It has steps defined similar to a real fabrication flow. Several measurement types can be defined such as CD (critical dimension), difference between max and min elevation, thickness of films at particular locations, angle of a sloped sidewall and so on.

    SEMulator3D can show a cross section of the device model at any location. In the above cross section of a RF Tunable Capacitor, CD (finger width of the comb drive), Film Thickness (structure thickness) and Line to Line Spacing (width of the perforation plate) are shown. The virtual metrology measurement options provide ‘3D DRC’ for validating these dimensions. Particular regions (e.g. Comb drive fingers stator and rotor Line-to-Line) can be selected to view in 2D layout editor for virtual metrology and analysis.

    DRIE (Deep Reactive Ion Etching) has scalloping issues which need to be analyzed and controlled. To characterize the scalloping effect, comb fingers of the Tunable Capacitor were etched using SEMulator3D’s DRIE Custom Python module which provides anisotropic etching through a time-domain multiplexed processing scheme. In this scheme, etching and polymer deposition are alternated to pattern high aspect ratio of structures.

    Above images show the SEM (Scanning Electron Microscope) view of fabricated and SEMulator3D view of simulated DRIE profile of inter-digitated comb fingers. The average values of parameters such as height, width and rate are highly dependent on design parameters and etching equipment. There is good agreement between the simulation and experimental results.

    The image above shows a scallop dimension, simulated on SEMulator3D, of 501nm height and 176nm width. Longer etch cycle times are responsible for larger scallop heights that in turn are responsible for deeper scallops. A SEM view of similar fabricated etched parts compare well with the modeled view by SEMulator3D.

    The Virtual Fabrication Platform of SEMulator3D accelerates the development time for MEMS devices by a large extent at significantly lesser cost and higher accuracy by eliminating in-fab set up and process variations during unit process interaction studies and quantitative analysis.

    Alexandre Mehdaoui of Coventor has described in great detail the overall Virtual Fabrication process for MEMS with nice examples, pictures and references in his new whitepaperposted at Coventor website. It provides an interesting learning about what goes in fabrication and how that has been automated in a software tool like SEMulator3D.

    More Articles by Pawan Fangaria…..

    lang: en_US

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    ARM, Cadence and the Internet of Things

    ARM, Cadence and the Internet of Things
    by Paul McLellan on 03-20-2014 at 6:30 pm
    Categories: Arm, Cadence, EDA, IP

    There is clearly a lot of hype about the Internet of Things (IoT) right now, but also it is clear that it will be a real market. In fact, it already is with various medical, fitness and home-appliance products already available. At CES in January, wearables was probably the biggest trend. That doesn’t always pan out (3D TV was the biggest trend a couple of years ago and how’s your 3D TV working out?) and in terms of acres of silicon it will not compete with smartphones for some time.


    I wrote here about a report on the Internet of Things that ARM had commissioned from the Economist Intelligence Unit. That was 6 months ago but the basic information in the report is very much still current. With acquisitions like Google buying Nest, if anything the conclusions of the report that IoT is real and inevitable seem even stronger now.

    In the meantime, the Maker movement isn’t waiting for true products to appear in the space they are making them themselves. Some of these will turn out to be early prototypes of ideas that will become widespread. For example, hereis a little circuit that will send you a text message when your dryer is done. If your dryer is in the garage or the basement where you don’t always hear it, wouldn’t you want your dryer to have that capability. Or hereis an open source-thermostat, basically a Nest you can build yourself. Just Google “internet of things maker” to see some of the other interesting ideas that are floating around: the future is closer than you think.


    IoT devices are characterized by needing a combination of technologies:

    • A microprocessor to run all the software including the communications stack
    • Flash and other memories
    • Analog (or analogue as ARM likes to call it, you have to read it with a British accent) for sensors
    • RF for networking
    • Perhaps MEMS devices such as accelerometers

    There is a perception that creating such a mixed signal design is hard. ARM and Cadence have an upcoming webinar MCU Mixed Signal Design Challengesat 11am Pacific on April 9th on the topic. I doubt that they are going to claim that such designs are easy, but the combination of Cadence’s Virtuoso environment with ARM’s processor and physical IP makes it a lot smoother than it used to be. Indeed, design tools have advanced so much in the last few years that IoT chips with all their various blocks can be designed so that they are production quality from the start, and work first time.

    The webinar will be moderated by Curt Schwaderer of OpenSystems Media and will feature:

    • Diya Soubra, CPU Product Marketing Manager from ARM
    • Joel Rosenberg, Platform Marketing Director from ARM
    • Mladen Nizic, Engineering Director from Cadence.

    More details including a link for registration are here.