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October 12, 2013June 14, 2019

What Can Accelerate 3D Semiconductor Manufacturing?

What Can Accelerate 3D Semiconductor Manufacturing?
by Pawan Fangaria on 10-12-2013 at 9:30 am
Categories: Coventor, EDA

In the beginning of this decade there was a lot of buzz around 3D chip manufacturing. Many EDA tools were developed to facilitate semiconductor designs in 3D space. Naturally, we are moving to the edge on 2D without much room to further squeeze transistors and interconnect. However, lately I haven’t heard much about 3D products. What happened? All I could guess is that there must be manufacturing difficulties, yield and ramp-up issues and the like. Then, last week I got to hear from IHS iSupplithat NAND Flash memories are moving into 3D manufacturing. That was interesting news, so I looked further into one of the latest articles on iSuppli website written by Dee Robinson, here. It’s understandable because NAND Flash memory is the fastest in reaching that limit of finer geometry in 2D production, however I was disappointed after learning that 3D NAND Flash will take four years from now to reach about 65% (by 2017) of total NAND Flash share. Why should it take so long?

Actually, I was perplexed because during my last conversation with Dr. David Fried (CTO-Semiconductor ofCoventor), he was showing me a complete conventional SRAM block built in less than an hour by his SEMulator3D virtual fabrication platform.

[SEMulator3D build of a SRAM up to M3 and a cutaway section]

And, I have been following up with SEMulator3D which strengthens my belief that it is capable of facilitating the designer / process engineer doing all the trials (which a fab will do in months) in a matter of days before producing the best model which can provide optimum yield in the final fab. Then why can’t it help ramp-up 3D NAND Flash now? I thought of talking directly to Dr. Fried on this and then I found another blog on the Coventor website written by David himself on 3D NAND Flash memory, here. It was a great coincidence; the blog talks about the challenges of semiconductor equipment and manufacturers in keeping up with super high precision and high aspect ratios with stacks of a large number of layers and deep tiny holes in them going through all the different process steps. But then he also talks about SEMulator3D which can really help accelerate 3D NAND Flash to achieve production ramp-up much faster, with better yield as its defectivity analysis feature can prevent defects (which can be catastrophic in case of 3D stacks as a single defect can destroy the whole column) much early in the cycle.

So, this was a reason enough to talk to Dr. Fried in the context of 3D NAND Flash on how SEMulator3D can help in accelerating achieving this attractively placed feat and then provide the base for other 3D semiconductor manufacturing in general. Here is my conversation with Dr. David Fried –

Q: I have read your blog, so will not get into that detail. But tell me, considering SEMulator3D is used by 3D NAND Flash manufacturers, by when do you think this technology can come into main stream production?

It’s pretty clear to me how challenging 3D NAND Flash manufacturing must be. I come from an advanced CMOS logic background, and some of the challenges of 3D NAND Flash seem almost insurmountable to me. We’re starting to hear from all the major NAND Flash players about how close they are to 3D high-volume manufacturing. However, seemingly tiny issues could produce significant production delays if not accounted for. Process variation, both systematic and random, could impact the performance or retention characteristics, or even physical yield. Any manufacturer of 3D NAND Flash needs a thorough understanding of the impacts of process variation, specifically in this incredibly challenging process flow. Some variation can be accounted for in performance guard-bands or margin, but certain aspects of variation will drive design and process solutions. SEMulator3D’s capability to predictively model complex processes and quickly study the impacts of process perturbations in a quantitative manner will deliver the type of data required to solve these challenges and ramp yield on aggressive schedules. From those manufacturers with a proper understanding of variation, we could see 3D NAND Flash products within months. For others, performance, reliability and yield issues could delay these products by quarters to years.

Q: Can SEMulator3D detect all kinds of defects ranging from contact alignments (throughout the stack) to connectivity, electromigration and other electrical defects?

SEMulator3D has predictive modeling capability that extends to several different physical defect mechanisms. First, systematic process variation is modeled easily with the Expeditor batch modeling tool. This covers examples such as lithographic misalignment, deposition and etch variation and perturbations in all these processes across the area of the wafer. Semulator3D also has the capability to implement random defectivity in the model, and study the physical or electrical impacts of these defects. Since the physical dimensions of SEMulator3D models can be extracted quantitatively, critical parameters that drive electrical or reliability failures (such as minimum line width or cross-sectional area in the case of electromigration) can be identified and located early in the development process, so solutions can be applied before costly manufacturing delays or reliability failures in the field.

Q: I can see NAND Flash as the first one jumping onto the 3D wagon, are there other breeds of memories which should go 3D way? And how SEMulator3D can help accelerate that path?

Logic, including SRAM, is already moving more 3D with the advent of FinFETs. But, frankly, all semiconductor technologies have had significant 3D aspects for many years. DRAM has had very tall dense capacitors in the flow for generations; Interconnect has always been a multi-layer patterned stack of wires and vias; even so-called “planar” transistor technology has gates and contacts that represent complex 3D geometries. With densities scaling across the entire industry, accurately predicting these 3D structures is the key to any advanced node. I am very excited to see all the novel memory structures emerging from research labs, including MRAM, Spin-Transfer Torque (STT) Memory, Phase-Change Memory, Resistive Memory, and many others. All these new memories have different storage mechanisms, but to make a competitive product, they’ll all need to be scaled to miniscule dimensions and packed into extremely tight geometry. Predictive modeling of those novel processes, integration schemes and product designs will be the key to jumping the gap between research and production.

Q: Memories have regular structures in general, so in my opinion, those should be relatively easier compared to other ICs. Do you see value in complex ICs adopting 3D path? I guess process complexity will further increase for those. How can SEMulator3D help?

A memory product is comprised of more than just the array devices. You’re correct that the storage array is composed of very regular structures. This makes patterning a bit more uniform and processes a bit more controlled in those regions. However, on any given memory product there is also a significant amount of peripheral logic and I/O. These areas are comparatively randomly designed relative to the uniform array area. Much of the challenge in yielding complex memory products is controlling the process both in the uniform array and in the non-uniform peripheral logic and I/O circuitry. Developing one wafer-scale process that accounts for all design types is the goal. As such, memory product development is quite similar to logic IC development. As I said before, all technologies in the industry have had 3D aspects previously, and are pushing the 3D structures even further in advanced nodes. SEMulator3D’s virtual fabrication environment enables a fast methodology for evaluating processes and integration flows across a range of different design areas. The same types of process variations, both systematic and random, affect the wafer as a whole, and can be modeled and evaluated quickly using SEMulator3D, its Expeditor batch-modeling tool and quantitative analytical techniques involving Virtual Metrology.

Q: Coming back to memories, recently I heard about MRAM, ReRAM, Memristorand the like also on memory manufacturers’ radars to enhance capacity and performance. How do you associate those in the overall scheme of memory manufacturing in the near future?

As I mentioned before, I’m excited about all the new memory types I see in research. I can’t tell which of these memory technologies will win in the end. But, I have a suspicion that we’ll continue driving a few different technologies for different applications. As we currently have deployed DRAM for low-cost dense memory, Flash for non-volatile memory and SRAM for high-performance memory, I see the industry keeping a mix of memory technologies going into the future to cover the full range of application requirements. I simply don’t think there’s any one memory technology out there that could replace the multi-tiered memory stack that we’ve become accustomed to. So, in the coming years, I think we’ll be called upon to develop more and more different technologies, with different processes, different designs and different integration flows. All of them will be impacted by the imperfections of manufacturing processes, and these imperfections represent the grand engineering challenge we’re all working to surmount.

This again was a very nice conversation with Dr. Fried, enhancing my knowledge about memories, 3D semiconductor design and manufacturing and SEMulator3D as an enabler for these technologies. I like it!!

lang: en_US

October 11, 2013

Mobile-Ready EDA and Semi IP Web Sites

Mobile-Ready EDA and Semi IP Web Sites
by Daniel Payne on 10-11-2013 at 7:12 pm
Categories: EDA, General, IP

18 months ago I blogged about how the mobile revolution that we enjoy today is really enabled by EDA software and IP in the hands of SoC designers, yet very few EDA and Semi IP companies had mobile-ready web sites. In that past 18 months we’ve witnessed only a handful of companies migrate to mobile-friendly web sites, the most familiar sites to mobilize are Mentor Graphics and Ansys.

What follows is a chart showing a comparison between April 2012 and October 2013.

And now to compare the EDA and IP media sites:

Summary
Change happens slowly with EDA and IP vendors migrating to mobile-friendly web sites, sad but true. Kudos to those companies that have made the investment to make their web sites friendly to users like me that browse the web on an iPad, Nexus 7 tablet and Samsung smart phone.

October 9, 2013June 14, 2019

Managing All of That IP on Your SoC

Managing All of That IP on Your SoC
by Daniel Payne on 10-09-2013 at 10:26 pm
Categories: EDA, Perforce

It’s common to see an SoC with a few hundred IP blocks today, which is quite a change from full-custom IC designs developed in the early days (i.e. 1980’s) where there was little IP re-use at all. This shift in the technology and business of IP has created a relatively new industry of IP providers from small to large in size.

Comparison of old vs new SoC (#IP blocks, % of chip that is IP)

Continue reading “Managing All of That IP on Your SoC”

October 9, 2013June 14, 2019

What do Intel and Congress Have in Common?

What do Intel and Congress Have in Common?
by Daniel Nenni on 10-09-2013 at 8:00 pm
Categories: Foundries, Intel Foundry

The war of words continues, when will it end? I consider myself a reasonably educated and informed person, certainly above average by U.S. standards, yet I have no idea why the U.S. Government continues to write checks they cannot cash and I don’t know who to believe in the resulting media blasts. I truly miss the days of Ross Perot and his pie chart political campaigning!

Intel is the same for me as they continue to bash the fabless companies thus writing checks they cannot cash. It first started when Intel entered the foundry business with Intel Fellow Mark Bohr predicting the demise of the fabless semiconductor ecosystem. It continues today as Intel starts to compete directly with Qualcomm, Nvidia, Marvell, ARM, TSMC, and the rest of the fabless semiconductor ecosystem. Remember, Intel has about a hundred thousand employees while the fabless semiconductor ecosystem has hundreds of thousands of employees. Intel invests billions of dollars in R&D every year while the fabless companies invest more than a trillion.

The latest comes via twitter:

Francois Piednoel ‏@FPiednoel
#ARM is very excited, TSMC has powerpoints about FinFet … 😉 powerpoint … From PPT to FAB, about 3 years…

Francois Piednoel ‏@FPiednoel
well, from the moment you start ordering your tooling to a process, there are definitively 3 years … you need to cut on cafe.

Francios is a career Intel engineer so he is certainly not speaking from firsthand experience. There is also a winky face so he can claim humor but it is being repeated as a fact because that is how the internet works today (just listen to people who believe what you believe). Even though Francios only has 374 followers this one has gone viral and has filled my inbox with chatter.

To be clear: TSMC and Samsung have released production FinFET PDks and will be accepting FinFET tape-outs this quarter. Production ramping will start in Q4 2014 so you will see FinFET FPGAs and SoCs in the first half of 2015, absolutely. That is 1.5 years, not “about 3 years” Mr Piednoel.

Growing up as a computer guy in Silicon Valley Intel certainly earned my utmost respect. Unfortunately, doing business in and around Intel for the last 30 years has taught me that if people had a choice they would NOT do business with Intel due to arrogant and predatory business practices.

Unfortunately for Intel, people do have a choice in the Chrome book, tablet, and smartphone markets, which by the way are eating the Intel PC and laptop markets for breakfast, lunch, and dinner. The server market is also at risk now that the legions of ARM licensees are releasing a plethora of low cost and low power 64-bit server products. Let’s see what Q3 brings INTC shareholders next week but I see no real upside here.

In a logical world technology would win every time and Congress would act like a responsible adult but clearly we do not live in an even near logical world. We live in a highly emotionally charged world where Twitter can topple entire Governments much less a 100,000 employee semiconductor company. Just my opinion of course and I will add a winky face here for good measure 😉

October 9, 2013June 14, 2019

Catch Mentor’s embedded sessions at ARM TechCon

Catch Mentor’s embedded sessions at ARM TechCon
by Beth Martin on 10-09-2013 at 9:00 am
Categories: EDA

For Halloween this year, why not tell your embedded software debug horror stories at ARM TechCon? Mentor will have several campfire sessions you should consider attending, but here my Halloween thread breaks down. These three sessions are all quite cheery.

This one, Software Debug on ARM Processors in Emulationis on using emulation for software debug. Emulation gives the software team earlier access to the design, but the software needs to be debugged. Emulators allow access to signals around the core that are not accessible in the final device, and these can used to debug and trace the processor. In this session, Russ Klein, a Technical Director in the Mentor emulation division, will talk about the different debug approaches available, trade-offs involved in each approach, and how and when they can be most effectively applied during the design cycle. Russ has been developing verification and debug solutions that span the boundaries between hardware and software for over 20 years, so believe that he’s an expert.

As the ARM architecture scales to meet tomorrows requirements, coherent caching becomes a critical component of an ARM system. In the session Cache in Your Chips: Coherence in an ARM SoC Environment, Mentor’s verification architect Andy Meyer, looks at the issues around multiple caches, why coherence is useful, and gives detailed examples of how coherent caches work in the ACE and CHI AMBA protocols. Andy goes over what to consider in your design from a verification and performance viewpoint, plus stimulus generation methods, metrics capture, making sense of performance and coverage analysis. Andy is somewhat of a celebrity; among his accomplishments in the field, he was one of the developers of OVM, and is the author of “Principles of Functional Verification.”

Another session, Pre-silicon Bringup, Debug and Analysis of Embedded Software on ARM based SoCs looks at how software-driven verification uncovers deep hardware software faults and deadlocks by incorporating trace-based debug and analysis techniques. These faults discovered at this early stage would not have been otherwise found using standard hardware verification methods. This session is given by Mentor Graphics’ own Shabtay Matalon. He has been active in system-level design and verification tools and methodologies for over 20 years.

But don’t limit yourself to those three sessions, Mentor has nine other sessions at ARM TechCon. You can see them all at Mentor’s ARM TechCon page. Mentor also has an on mentor.com”]ARM Solutions microsite where you can see their company-wide ARM support.

October 9, 2013June 14, 2019

Spectre from Cadence Goes FastSPICE

Spectre from Cadence Goes FastSPICE
by Daniel Payne on 10-09-2013 at 2:31 am
Categories: Cadence, EDA

Transistor-level circuit designers have an insatiable appetite to run numerous SPICE circuit simulations in order to determine circuit speed, current and power across Process, Voltage and Temperature (PVT) conditions. Just look at the number of PVT corners increasing as the technology nodes go to 16nm:

The good news today from Cadence is that they’ve developed a new FastSPICE circuit simulator, named Spectre XPS.

I spoke by phone last week with John Pierceof Cadence to get an update on what they’ve done to birth Spectre XPS.

What is Spectre XPS?

Spectre XPS is a new FastSPICE circuit simulator that uses techniques like partitioning in order to simulate large, extracted netlists with 10’s of millions of elements. Another technique is to reduce the large number of RC elements into a more manageable number, while retaining accuracy.

You can now simulate large, extracted netlists that just wouldn’t fit into Spectre APS and perform an accurate, dynamic IR drop analysis.

The new simulator accepts netlists in the familiar Spectre and HSPICE formats, runs Transient and DC analysis, uses Spectre commands and models, is compatible with all the PDKs from foundries, and integrates with Virtuoso ADE.

When Should I use XPS or APS?

As your netlist size grows into the millions of elements then Spectre XPS makes sense, while for smaller designs you can continue to simulate with Spectre APS. The UltraSIM product was originally targeted at hierarchical designs, however that simulator will go into a maintenance mode because Spectre XPS can handle 10’s of millions of elements now.

An SRAM design was simulated with Spectre XPS and it had some 30+ million elements (25M RC, 7.5M MOS), and used up only 7.5GB of RAM:

The capacity is there, plus it should benchmark well against competitor circuit simulators in terms of speed. In general you can expect the XPS simulator to be 5X to 15X faster than APS at comparable accuracy levels:

If you use AMS Designer for mixed-signal simulation, then stay tuned for when Spectre XPS gets integrated into that.

Continue to use Spectre APS for smaller designs, and for highest accuracy circuits like: BER of an ADC, PLL Jitter.

Learning Spectre XPS

If you’re an existing Spectre user then learning XPS takes only a few minutes. You can trade off speed versus accuracy using a simple setting with 5 levels. That’s quite an improvement from using UltraSim which had lots of switches and settings for tuning.

Summary

Cadence has a new FastSPICE circuit simulator that increases capacity to 10’s of millions of devices, allows IR drop analysis for extracted netlists, gives the competition something to worry about, and works well simulating embedded memories. If you’re thinking about evaluating FastSPICE circuit simulators, then place Spectre XPS on your list.

October 8, 2013March 22, 2022

Managing Multi-site Design with Cliosoft at LBNL

Managing Multi-site Design with Cliosoft at LBNL
by Paul McLellan on 10-08-2013 at 11:40 pm
Categories: Cliosoft, EDA

With the award of the Nobel prize for physics to Higgs (who used to work in the same building at Edinburgh as I did, reflected glory) and Englert yesterday, CERN has been in the news. ClioSoft has an interesting presentation given at CERN about designing a detector chips. The work was done two or three years ago, managed from Lawrence Berkeley National Laboratory (which is at the top of the hill above UC Berkeley). The talk was given by Maurice Garcia-Sciveres of LBNL.

One of the big challenges is that the design team was distributed, with designers at 5 different sites around the world. The collaboration platform for managing all the design data was ClioSoft. The golden repository was at LBNL and was automatically mirrored at all the other sites.

The features that they especially relied upon were:

low-cost educational licenses
worldwide access to design data in real time
revision management (backups, versions, snapshots)
graphic diff tool to visualize changes in schematics and layout
simple and flexible administration
very robust (they never lost any data)
fast (with the caching, data access the same as accessing local data)
flexible, allowing all data types to be shared in the same repository, digital and analog design, documentation etc.
capability to link seamlessly to local design data such as PDKs, IP etc (that was not kept in the repository and was acquired separately at each site).

A large part of the talk is about the chip and the design methodology but there is an emphasis on how the design was organized to allow distributed collaboration and management of a large design. The team is the first to admit that they don’t have a secret recipe guaranteed to work for organizing a big geographically distributed design like this. But the design was successful and they point out all the things they did well (and not so well). Of course, any major project needs a disciplined approach to design data management.

ClioSoft’s hardware configuration management solutions are seamlessly integrated into the major schematic/layout environments: Cadence’s Virtuoso, Mentor’s Pyxis, Agilents ADS and both Synopsys Custom Designer and Synopsys Laker. Design data is automatically checked out from within these environments without requiring switching back and forth between the tool being used to get real work done and the design data management interface itself.

The slides for the talk are here (pdf of powerpoint).

Also Read

Analog ECOs and Design Reviews: How to Do Them Better

ClioSoft at GenApSys

VIA Adopts Cliosoft

October 8, 2013June 14, 2019

Can you Publicly Benchmark EDA Tools?

Can you Publicly Benchmark EDA Tools?
by Daniel Nenni on 10-08-2013 at 7:00 pm
Categories: EDA

There is an interesting discussion on SemiWiki in regards to the age old question aboutbenchmarking EDA tools. I remember benchmark discussions at my first DAC in 1984. It was deemed impossible to do a “fair” public benchmark then and it’s not possible now, just my opinion of course but let me tell you why. Simply stated it is a legal, technical and political mountain that just cannot be climbed.

The first comments in the forum discussion pointed out that current EDA purchase agreements prevent public benchmarks. I don’t remember specific contract clauses when I started in EDA but I do know we signed NDAs (non-disclosure agreements) that begot confidentially. That is definitely the case today as there are specific confidentiality contract clauses and NDAs are a standard part of the EDA product evaluation process so even if it was technically and politically possible there are definitely legal barriers.

The tool reviews on DeepChip were also referenced. The credibility of the reviews are in question since they are generally vendor sponsored with “friendly” customers and ghost written by a PR person. I still see value in this type of tool review assuming there is no financial link and vendors are not hand picking participants. There is recent FTC scrutiny on websites that do product reviews (endorsements). The lawyer I hired to educate us on the legal liabilities of running SemiWiki strongly advised us to clearly document the financial trail related to content mentioning a sponsor or advertiser. As a result we have dedicated landing pages for each SemiWiki subscribing/sponsoring company, the company is clearly identified in the header of the article, and there is a sponsor disclosure in the footer of all pages. The SemiWiki bloggers are also listed with links to their LinkedIn profiles for professional affiliations. It might be overkill but the last thing we need is the FTC on our backs and the credibility of a site with original content such as SemiWiki is critical to our survival, absolutely.

The consensus of the discussion suggests that the technical aspect of benchmarking is the real challenge and something that is just not feasible. Tracking tool versions, replicating hardware environments, guaranteeing the authenticity of the results, and applying the results to different design requirements is a daunting (expensive) task. That is assuming EDA vendors cooperate, which they most certainly will not. I do not see large semiconductor companies supporting this effort either since they view EDA tool usage as a competitive advantage and are very secretive in this regard. Coincidentally, as I write this, I’m at the Si2 conference which started out reviewing their impressive progress over the last 25 years. Unfortunately the hard earned Si2 standards accomplishments pale in comparison to the EDA benchmarking challenge as I see it.

One of the more interesting comments was that we try something like a consumer reports product review which would be a structured and detailed report. Rather than getting friendly customers from vendors, we get this type of feedback directly from users who can answer a standard set of questions directly by posting on a dedicated SemiWiki forum. To post on SemiWiki you need to be a registered member. To register and create a screen name you need to provide a LinkedIn profile which we do check for authenticity. The forums can be moderated by SemiWiki members that have no financial ties to vendors.

Let’s brainstorm here, if we can come up with something modeling consumer reports that the fabless semiconductor ecosystem can benefit from I would be happy to put resources into it. Sound reasonable?

lang: en_US

October 8, 2013June 14, 2019

Mentor Seminar: Evolution of diagnosis-driven yield analysis

Mentor Seminar: Evolution of diagnosis-driven yield analysis
by Beth Martin on 10-08-2013 at 1:20 pm
Categories: EDA

It’s a fact that new process nodes come with some amount of yield challenges. One way to find and eliminate silicon defects is through diagnosis-driven yield analysis (DDYA), which is the topic of a free seminar by Mentor Graphics in Fremont this Thursday, October 10 from 11:30am – 2pm (yes, lunch is included because Mentor loves you).

During the transition to the 28-nm node, several leading semiconductor companies couldn’t ship enough of their products partly because of lower-than-expected yield. This situation keeps product engineers busy with new yield learning methods. DDYA has evolved, like all living things, from a primordial soup of data collection and sorting to a well-honed, DFM-aware, noise-reduced workhorse for finding and eliminating silicon defects.

The past and future application of DDYA is the focus of the seminar. If you are responsible for improving the yield of your company’s products, there are worse ways to spend the early afternoon.

The presenter is Brady Benware, an engineering director responsible for the diagnosis and yield improvement solutions at Mentor, and all-around good guy. He will show how diagnosis-driven yield analysis was used successfully to drive yield improvement in recent process technology history, revealing some surprising lessons learned.

Evolution never stands still, though, so Brady will also show how DDYA is actively adapting to address the expected yield challenges the new FinFET fabrication technologies.

October 8, 2013June 14, 2019

Atrenta Japan Technoloogy Forum

Atrenta Japan Technoloogy Forum
by Paul McLellan on 10-08-2013 at 12:27 am
Categories: EDA

As they have done for the last few years, Atrenta held its fifth annual user group meeting at the Shin Yokohama Kokusai Hotel on September 13. The attendees are a mixture of customers and other interested members of the semiconductor supply chain. There were nearly 90 people there representing 48 different companies in Japan.

The trick for a good user group meeting is to get customers to speak about their actual experience. Nobody wants to spend all day listening to presentations by marketing people. Atrenta seems to have managed to get plenty of representatives of the big Japanese semiconductor companies to present their experiences and so they ended up with a full agenda of detailed technical presentations.

This is what was presented. You can click on any presentation to get more details from the Atrenta website.

Fujitsu Use of SpyGlass Constraints: How Fujitsu Semiconductor Limited deals with critical timing constraint issues
Improving FPGA Verification at Hitachi: Use of SpyGlass CDC and Lint by Hitachi Information & Telecommunication Engineering, Ltd. to enhance their FPGA design flow
MegaChips Uses of SpyGlass Constraints and SpyGlass TXV: MegaChips’ use of SpyGlass Constraints and SpyGlass TXV to create high quality SDC for 3rd party IPs
Renesas Use of BugScope: Renesas Electronics Corporation using new techniques to confirm the quality of the verification environment for large-scale LSI development
SpyGlass Physical Use at Hitachi: How Hitachi Storage Development reduced debug iterations and ultimately their design schedule by integrating SpyGlass Physical into their design flow
SpyGlass Platform Adoption at Denso: The results achieved at the semiconductor circuit R&D department of the Electronics Device Business Unit of Denso by adopting the SpyGlass platform

One interesting fact. Based on a survey conducted at the end of the meeting, over 60% of the attendees showed interest in learning more about BugScope that Atrenta acquired last year when they bought NextOp. Bugscope is a tool that helps generate assertions automatically for assertion-based verification. This is very time-consuming and error-prone to do by hand. As a rule of thumb, you want one assertion for very 10 to 100 lines of RTL but each assertion takes hours to create and debug, so for a sizeable piece of RTL this is a huge undertaking without using Bugscope. Another problem that Bugscope helps with is ensuring that assertion coverage is complete, another task that is notoriously hard to do well manually.

The next Atrenta event coming up in Japan is EDSFair 2013 in the Pacifico Yokohama on Nov 20-23 where Atrenta will have a booth. More details on the EDSFair are herein English and here in Japanese.