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May 12, 2014June 14, 2019

Solido Patent Enabling Variation-Aware Custom IC Design

Solido Patent Enabling Variation-Aware Custom IC Design
by Daniel Nenni on 05-12-2014 at 8:00 am
Categories: EDA, Solido

This is patent number twelve for Solido Design Automation THE leading provider of variation analysis and design software for high yield and performance IP and system-on-chip (SOCs). Additional patents are pending on high-sigma analysis, high-dimensional data mining, and other technologies to design and verify custom integrated circuits.

It has been my pleasure to work with Solido on strategic foundry relationships and other business development tasks for close to five years now. Solido’s product, Variation Designer, is used by top semiconductor companies to boost SPICE simulator efficiency by dramatically reducing number of simulations for PVT, 3- to high-sigma Monte Carlo and variation debug while increasing design coverage.

If you want to know who Solido’s customers are think SoC companies and just about everyone else who cares about yield at 40nm and below. In fact, you will be hard pressed to find a fabless company with an SRAM team that does NOT use Solido for high-sigma verification.

[LIST=1]

Method and system for verification of electrical circuit designs at process, voltage, and temperature corners. Enables users to signoff designs under PVT variation, reducing the simulations by 2-10X+ compared to brute-force simulation of all corners. U.S. Patent No. 8,612,908.

Monte Carlo-based accurate corner extraction. Designers can extract 3-sigma statistical PVT corners on circuit outputs with a minimal number of simulations, even for circuits with 100K+ devices. U.S. Patent No. 8,494,670.

Interactive schematic for use in analog, mixed-signal, and custom digital circuit design. Users are able to to quickly identify variation hotspots on schematics themselves. U.S. Patent No. 7,761,834.

Pruning-based variation-aware design. Enables designers to perform variation-aware design in a unified flow, where corners are the centerpiece. U.S. Patent No. 8,074,189.

Model building optimization. Designers can further reduce the number of SPICE simulations inside several Solido Variation Designer applications including Fast Monte Carlo and Cell Optimizer. U.S. Patent No. 8,006,220.

On-the-fly improvement of certainty of statistical estimates in statistical design, with corresponding visual feedback. During a run of Solido Variation Designer, designers can quickly assess the statistical confidence of yield & output predictions, how uncertainty reduces over time, with real-time updates. U.S. Patent No. 8,589,138.

Global statistical optimization, characterization, and design. Enables users to explore the space of possible circuit sizings and gain extensive insight into the relation from design variables to outputs. U.S. Patent No. 8,024,682.

Data-mining-based knowledge extraction and visualization of analog/mixed-signal/custom digital circuit design flow. Offers insights into the effects of variation on their circuits, and the causes of that variation, “for free” via data science technologies to mine existing SPICE simulations. U.S. Patent No. 7,707,533.

Modeling of systems using canonical form functions and symbolic regression. Facilitates manual equation-based analysis, by suggesting easy-to-understand equations that relate design, environmental and process variables to outputs. U.S. Patent No. 8,332,188.

System and method for determining and visualizing tradeoffs between yield and performance in electrical circuit designs. Enables users to rapidly explore the relationship between circuit performances and yield in a visual, interactive fashion. U.S. Patent No. 7,689,952.

Method and system for proximity-aware circuit design. Designers can perform electrically-aware layout design and handle well proximity and other effects, without the inconvenience of tight coupling to front-end design tools. U.S. Patent No. 8,281,270.

Trustworthy multi-objective structural synthesis and expert knowledge extraction with application to analog circuit design. Enables users to quickly explore thousands of possible circuit topology options, and understand the strengths and weaknesses of each topology. U.S. Patent No. 8,443,329.

Solido Events at DAC:
Solido DAC Booth #933 Variation Designer Demo Register
June 2, 10:30am DAC Panel on Variation-Aware Custom Design Best Practices Register
June 2-4, Solido TSMC Theatre presentation

About Solido Design Automation Inc.
Solido Design Automation Inc. provides fast, accurate variation analysis and design software for custom IC’s so that our customers can achieve maximum yield and performance in their designs. Solido’s product, Variation Designer, boosts simulator efficiency by dramatically reducing number of simulations for PVT, 3- to high-sigma Monte Carlo and variation debug while increasing design coverage. Variation Designer is being used by top semiconductor companies and is qualified by TSMC and GLOBALFOUNDRIES to design memory, standard cell, custom digital and analog/RF IC’s at leading design nodes. The privately held company is venture capital funded and has offices in California, Asia, Europe and Canada. For further information, visit www.solidodesign.com.

New Frontiers in MEMS and Their Enablers

New Frontiers in MEMS and Their Enablers
by Pawan Fangaria on 05-11-2014 at 10:00 pm
Categories: Coventor, EDA

With the 51[SUP]st[/SUP] DACapproaching quickly, I spent some time last week-end to look around about what new trends, technologies and innovations will be most talked about during DAC. Every year, I find some exciting new technologies in the semiconductor industry and the overall semiconductor ecosystem that get wider exposure to the community during DAC. This year I will not be surprised to see MEMS get more attention; more and more MEMS devices are being used for personal, industrial, automotive, security, medical, home and many other appliances.

Some time ago, I had talked about TI’sDLP technology, pico and phone projector. To my surprise, I see many companies working in this area – mini-projector for smartphones, micro-mirrors for many other applications, and others. Above is a picture of Fraunhofer’s mini-projection system for smartphone, where a user can operate the smartphone via the projection function or from the display screen. Any portion of an image in the projection can be zoomed in by swiping the projection with your finger in the same way as on the display screen.

Clearly with development such as these, and the overall excitement about other areas such as the Internet of Things (IoT), wearable devices, and ubiquitous sensors there is a bright future ahead for many areas of electronic design – and addressing the entire overall solution from software, hardware, assembly and so on must happen. MEMS are in the center of almost all of this activity, so it reminds me to keep an eye on what MEMS design tools provider Coventoris doing and what they have to say about recent trends– since they are working with the world’s leading MEMS developers every day.

When I reviewed Coventor website for their MEMS software tools offerings, I happened to go through some of their blogs and this was another proof of significant amount of R&D happening in developing new MEMS devices like these. A blog on bolometerstells me that there is great momentum around microbolometersand many of Coventor’s customers have been asking for evaluation and specific support for these type of devices (which were not so much in demand earlier) in their simulation and design tools. MEMS is an area where every device needs to be customized and in today’s business dynamics one cannot survive with the lengthy build-and-test cycles through foundry to qualify a device; simulation tools like SEMulator3D, CoventorWare and MEMS+ are a must to accelerate the process. In fact these tools will be very handy in exploring the development of new devices. I am happy to see that this trend is picking up!

Looking further into another blogby Gunar Lorenz, Director, System Level Simulation at Coventor, I got a bit of a ‘sneak peek’ at the upcoming release of Coventor’s new MEMS+ 5.0 platform (MEMS+ is a very innovative platform for helping designers combine MEMS with traditional ICs, an important trend in electronic design these days). The new release will be announced over the summer and it has many new capabilities for developing cutting-edge devices, about which I can talk later in much detail. But the preview blog post discussed some new features around the design of Micro Scanning and Projection Mirrors.

Typically, the electrostatic comb structures, which tilt the mirror out-of-plane, disengage completely during the mirror operation, and it’s a big challenge to keep the system in sync. In MEMS+ 5.0, the comb library components stay accurate even with the comb fully disengaged and that is reflected in the above graph where there is excellent agreement between MEMS+ with disengagement and the CoventorWare field solver.

Again, comb fingers between two moving flexible structures, a key modeling requirement for gimbaled two-axis mirrors, is now supported in MEMS+ 5.0 comb finger models.

The new release of MEMS+ will also feature a ROM (Reduced Order Model) export capability that can address the challenge of simulating frequency hysteresis, which typically requires large simulation time due to large number of time steps involved. This capability goes much beyond the typical multi-threading and algorithmic optimization of software to accelerate simulation speed. There is much more to look forward to in MEMS+ 5.0 release, and I’m eagerly waiting to write more about it.

I must say – it’s a great two way communication between the device developers and the tool enablers that gives rise to new devices and customizes and refines the existing ones for their application into ever newer smart electronic systems. With such automated tools and plenty of opportunities ahead, particularly in the much-talked about world of IoT, I am sure we will see a multitude of new MEMS devices that will be used in areas we haven’t even imagined yet.

Healthy Semiconductor Growth in 2014 and 2015

Healthy Semiconductor Growth in 2014 and 2015
by Bill Jewell on 05-11-2014 at 5:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

The first quarter 2014 semiconductor market was $78.5 billion, down 1.8% from fourth quarter 2013 and up 11.4% from a year ago, according to World Semiconductor Trade Statistics (WSTS). The year-to-year growth was the highest since 4Q 2010. The year-to-year growth has been accelerating for the last four quarters. Our February forecast at Semiconductor Intelligence was for 10% semiconductor market growth in 2014. This forecast is dependent on healthy quarter-to-quarter growth of 5% or higher in 2Q 2014 and 3Q 2014. The table below shows 1Q 2014 (or nearest fiscal quarter) revenue growth for major semiconductor companies and their guidance for 2Q 2014.

Most companies (9 of 15) reported revenue declines in 1Q 2014 versus 4Q 2013. Of the companies providing guidance, 11 of 12 expect revenue increases in 2Q 2014. Micron expects a decline in 2Q 2014 due to both declining memory prices and declining bit shipments. For the other companies the expected revenue increases range from 0.7% to 12%. The weighted average revenue growth for the above companies in 2Q 2014 is about 3%. Several companies provided a range of guidance, with the midpoints shown in the table above. The high end growth guidance ranges from 6% for Intel, Broadcom and AMD; 7% for Qualcomm; 8% for Infineon and NXP; and 14% for Texas Instruments. The higher guidance points toward a potentially strong 2Q 2014.

A robust 2Q 2014 could help drive year 2014 semiconductor market growth into double digits. Will this momentum carry into 2015? Below are forecasts for 2014 and 2015.

The forecasts for 2014 range from 4.1% from WSTS to 11.9% from Mike Cowan. We at semiconductor Intelligence are keeping with our February forecast of 10%. The trends for 2015 follow three distinct patterns. WSTS, Gartner and Semiconductor Intelligence expect 2015 growth to be similar to 2014. Future Horizons projects a strong acceleration from 8% in 2014 to 18% in 2015. Mike Cowan expects growth to decelerate from 11.9% in 2014 to 4.7% in 2015.

Semiconductor Intelligence’s forecasts for 2014 and 2015 are based on an improving economic outlook and continued growth of key end equipment drivers. The table below shows recent projections for global GDP growth from the International Monetary Fund (IMF) and growth rates for PCs, tablets, mobile phones and smartphones from Gartner and IDC. The IMF expects accelerating GDP growth in 2014 and 2005. Gartner projects PC units will continue to decline, but tablets should continue healthy growth. The combination of PCs and tablets are expected to show double digit growth in 2014 and 2015. Although overall mobile phone units are forecast to continue low single digit growth, smartphones will continue to be a major driver for semiconductors.

lang: en_US

May 11, 2014

Is the Chief IoT Barrier Privacy?

Is the Chief IoT Barrier Privacy?
by Daniel Nenni on 05-11-2014 at 9:00 am
Categories: EDA

The World Affairs Council event, The Internet of Things: Global Implications of Merging the Physical and Digital Worlds, was hosted by Cadence last week. One thing I can tell you is that Cadence sure does know how to throw a party! They had me at free food and beer but the topic was also of great interest since my next project will involve IoT, absolutely.

More than nine billion devices around the world are currently connected to the Internet, including computers and smartphones. That number is expected to increase dramatically within the next decade, with estimates ranging from quintupling to 50 billion devices to reaching one trillion. Please join us for a discussion of how the Internet of Things will impact the way we live, the way business is done and how resources are consumed. Important to the discussion will be the challenges ahead when merging the physical and digital worlds and the implications for privacy and security around the world.

The content speakers were from eBay, ARM, and Cisco. There was also a lawyer from GE and the moderator was the Director of Privacy, Center for Internet and Society, Stanford Law School. After introductions and brief statements there was a Q&A which focused primarily on privacy and big data. There were several professional journalists attending so I will leave the reporting to them and share my personal thoughts here.

Generally I sit at the back so I can see what other people are doing. I’m a fan of sociology and feel there is a lot to learn by observing behavior at these events. Content and interaction is always important but lately I look at the age of people and how they use mobile devices. In that regard this event was a treasure trove of information.

Looking at the audience of 100 or so semiconductor professionals I saw one laptop open, a handful of tablets, and the rest were smartphones. In the one hour session just about EVERBODY checked their phone at least once with quite a few people on them throughout the session including the guy next to me typing furiously on his Blackberry. Several phones rang during the conference and some people answered while walking out to finish what must have been an important conversation. That is the “always-on culture”, absolutely. My guess at the average age of the audience is 50ish so I’m just above average.

Internet privacy discussions don’t really interest me. We gave up our privacy when the internet came into our homes so who are we kidding here? I remember when E-commerce first started, enlightened people jumped on board with full force while others hid their ignorance behind security and privacy issues. “It’s not safe to put your credit cards on the internet.” they said. “It’s safer than giving your credit card to a complete stranger at a diner.” I said. I remember picking up cordless phone conversations on our baby monitor. Do they even sell phones with cords anymore?

In 1999, Sun Microsystems’ then-CEO Scott McNealy infamously declared, “You have zero privacy anyway. Get over it.”

In 2009 Googles’ then CEO Eric Schmidt infamously declared,“If you have something that you don’t want anyone to know, maybe you shouldn’t be doing it in the first place.”

If you want privacy stay off of the internet, simple as that. And don’t leave the house because there are cameras everywhere recording your every move. Don’t drive a late model car either or use a wireless router or anything bluetooth. In watching my four kids (who are now adults) communicate, privacy is not an issue as they are part of the always-on-oversharing-generation.

Bottom line: Privacy is an old person problem, one that will negatively affect your quality of life so get over it. Definitely be “privacy aware” but keep the paranoia to a minimum and enjoy the technology that is changing the world, just my opinion of course.

In regards to the Internet of Things or Internet Everywhere or Internet in our Underwear there is no stopping it so you might as well monetize it and enjoy the ride. How about this, let’s make the amount of data available from IoT so BIG that it is impossible to do anything with it. That’s our only hope for privacy.

The next live seminar that has caught my interest is “Strategies for Next Generation Semiconductor IP Management” at the Computer Museum in Mountain View, CA. They had me at Computer Museum, I love that place!

Disclaimer: SemiWiki is NOT a gossip website for hire. SemiWiki is an open forum (crowdsourcing) for semiconductor professionals. If you would like to post your experience from a conference or if you would like someone from SemiWiki to cover your event please let us know.

Mentor @ #51DAC Must See!

Mentor @ #51DAC Must See!
by Daniel Nenni on 05-11-2014 at 4:00 am
Categories: EDA, Siemens EDA

We’ve packed each day full of exciting activities focused on the latest in cutting-edge design. Use this site to find your favorite Mentor experts and events—whether in our suites and networking events, at our partner booths or in the conference. You won’t want to miss a thing!

Celebrating Your Design Creativity!
Rejuvenate with free coffee drinks every day, and restore your creative juices with free wine and beer, 4-6 p.m. daily.

Experts at the Mentor Graphics Booth
We’ve brought some of our best researchers and partners to DAC just to meet you. Find your favorites in the list below. Then hurry and sign up for their sessions, before they fill up!

Networking and Luncheons
There’s nothing better than learning about the latest in cutting-edge design, while enjoying good food and socializing with your peers. Mentor puts on the most ‘seriously’ fun events daily, so make sure you get them on your calendar.

Mentor Experts in the DAC Conference
Come listen to our brightest researchers and executives discuss the latest design issues in the DAC Conference panels, tutorials, workshops, papers and in the user track.

Partner Activities
Mentor Graphics offers the broadest support for the electronics ecosystem/supply chain. That’s why you’ll find Mentor experts sharing in a numerous partner activities on the exhibition floor—both in our booth and at our partners’ locations.

Back to the Future: Is There Success without Moore’s Law?
Monday, June 2, 2014
This panel will look at the ways that IC innovators are adding value to established IC nodes through increasing functionality, reduced power consumption, higher reliability, integration of MEMS and silicon photonics, and die stacking.

What will Moore’s Law Cost Us at 10nm?
Tuesday, June 3, 2014
For the first time in many years, there is a lot of uncertainty about how we get to the next IC scaling nodes. Will EUV be ready? Will we have to go to triple or quadruple patterning? Can DSA be commercialized quickly enough? What are the cost implications for these various alternatives? Can we see a way to get to 10nm and 7nm with an affordable technology? Are we at the point where designs are so tightly linked to a manufacturer’s specific process that multi-sourcing is unfeasible? How much commonality is there, and what can tools do to hide the differences? If it’s doable, is multi-sourcing economically viable? This panel will consider these all important questions and provide some insights if not the final answers.

Tackling FinFET Analog Mixed Signal and Memory Verification Panel
Wednesday, June 2, 2014
Analog, mixed-signal, and SRAM design teams migrating to FinFET process nodes are implementing new architectures to take advantage of FinFET benefits and overcome its limitations. As a result they need to retool their transistor-level verification flow for more accuracy, performance and capacity to offset the increased layout, device modeling, device noise, voltage scaling, and process variation effects. Designers of complex analog/mixed-signal circuits such as PLLs, ADCs, SerDes, and transceivers, need to explore alternative architectures and measure their impact in non-planar silicon. Embedded SRAM design teams realize that it is no longer acceptable to tolerate 5% or more inaccuracy in memory IP characterization. This panel is an interactive forum where attendees can exchange ideas and questions with a group of experts who are tackling the exciting opportunities and challenges related to the move to FinFET nodes.

Technical Focus Areas
AMS/Custom IC Design
Automotive
Design & Functional Verification
Embedded Software
IC Design & Test
Verification Academy

Executive Participation
Wally Rhines Mini-keynote
Wally Rhines Fireside Chat

Automotive participation
Serge Leef: http://www2.dac.com/events/eventdetails.aspx?id=170-25
Andrew Patterson: http://www2.dac.com/events/eventdetails.aspx?id=170-58

Technical session dates/times and descriptions can be found here
http://www.mentor.com/events/design-automation-conference/schedule

On the fun side
The 2014 World Champion Robotics Team will be doing a meet & greet at our booth on Tuesday between 10-4pm.

About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com

May 10, 2014June 14, 2019

Dassault #51DAC Assault!

Dassault #51DAC Assault!
by Daniel Nenni on 05-10-2014 at 9:00 pm
Categories: Dassault Systemes, EDA

This is one of the most aggressive DAC appearances I have seen from Dassault, absolutely. Dassault Systèmes is branded as the: 3D EXPERIENCE Company that provides virtual universes to imagine sustainable innovations. Its world-leading solutions transform the way products are designed, produced, and supported. Dassault Systèmes’ collaborative solutions foster social innovation, expanding possibilities for the virtual world to improve the real world.

Join us for these informative Conference Sessions featuring Dassault Systèmes Speakers:

Session:Modeling and Simulation for Automotive Electronic Systems (June 3, 4:00 pm, Room 310) – Michael Munsey, Director ENOVIA Semiconductor Strategy, Dassault Systèmes
Panel:System Engineering Methods and Tools for Automotive EE Design: Old wine in a New Bottle? (June 4, 4:00 pm, Room 310) – Khurshid Qureshi, Director, Systems Engineering Center of Excellence, Dassault Systèmes
Session: Multi-level Model Based Approach Supporting Development and Simulation of Embedded Systems (June 4, 6:00 pm, Esplanade Foyer) – Guillaume Belloncle, Transportation & Mobility Industry – Smart, Safe & Connected Car Solution Experience, Dassault Systèmes

Booth #1033: 

Customer Cocktail Reception: Co-hosted by Dassault Systèmes and Kalypso on Monday, June 2[SUP]nd[/SUP] from 4:00 – 6:00 pm
Demo: Design Collaboration – For streamlined semiconductor design ecosystems (using the NEW PANASONIC 4K 19″ tablet) 
Demo: Semiconductor IP Management – For efficient IP quality, packaging and inventory management 
Demo: Requirements Driven Verification – For consolidated management of diverse design verification and validation 
Demo: Manufacturing Collaboration – For managing complex packaging and product variants 
Presentation: Future of IP Management 
Presentation: Climbing the Design Collaboration Maturity Ladder  
Learn how to register to win an iPad 2 and other prizes in our daily drawing!

DAC Automotive Village, Booth #603, Kiosk #6:New to DAC this year!
Dassault Systèmes is Driving Future-Focused Innovation– Join us to learn more at our Automotive Village kiosk where we will be featuring solutions to:

Increase Design/Engineering Productivity
Ensure Traceability to Comply with New Industry Safety Standards
Complete Early Vehicle Performance Validation
Re-use Components Across Multiple Platforms
Synchronize Mechatronics with Systems Engineering, Improving Performance and Cost Efficiency
Demo: Synchronized Mechatronics and Systems Engineering
Automotive Village Reception: Join us for a special reception in the Automotive Village on Mondayfrom 5:00 – 6:00 p.m.

Stars of IP Party:
Dassault Systèmes is a proud Co-Host of the special Stars of IP Party – The premier Semiconductor IP Social Event at DAC taking place on Tuesday, June 3[SUP]rd[/SUP] from 8:00 p.m. – 12:00 a.m. at the Local Edition.

Semiconductor Requirements Driven Verification
Manage complex data relationships, integrate operational silos, and meet time to market deadlines with a verification and validation data management platform that allows for end-to-end traceability from product definition to end product configuration. All aspects of the verification and validation flow, from system architecture validation, through final die and package test are managed, tracked and documented.

Semiconductor Manufacturing Collaboration
Manage complex product execution where dyes from the same wafer are part of multiple product SKU’s. Organize multiple sourcing networks to meet volume requirements, mitigate risk (natural disasters) and to optimize for cost (such as currency fluctuations). Track, trace and audit supplier qualifications. Specify and qualify design and manufacturing data before it is handed to the downstream manufacturing systems to eliminate errors.

Selecting the Right Standard Cell & Memory for 28HPM DSP core: real case with CEVA XC4210

Selecting the Right Standard Cell & Memory for 28HPM DSP core: real case with CEVA XC4210
by Eric Esteve on 05-09-2014 at 11:14 am
Categories: Ceva, IP, Synopsys

Listening to a webinar at your desk, in front of a PC screen will never replace a live presentation, but the lesson learned to time spent ratio can be incredibly higher than when traveling to a conference to listen several presentation. If you are interested by the approach taken by a complex DSP design team to overcome the various bottlenecks they have faced with, from synthesis to floor-plan and floor-plan to place and route (P&R), and want to understand how the team has selected the various Synopsys library cell and Memories, then this webinar is certainly for you:

“Optimizing DSP cores for Performance and Power with DesignWare Logic Libraries and Embedded Memories”

And you can register, and attend to the seminar right away, just go here

The above picture is the XC4210 diagram, one of the most complex DSP core from CEVA. XC4210 has a fully programmable DSP processor architecture, made of two vector processing units – each unit operates on 256-bit vector registers offering a powerful SIMD engine

Up to 8 simultaneous instructions (8-Way VLIW)
Efficient DSP support for non-vectorized data
Efficient support for control and ANSI-C operations

Extremely powerful computation capabilities

64 16×16-bit MAC operations
64 arithmetic operations per cycle
Over 400 16-bit operations in a cycle

The challenge is dual: this core has to be optimized both for Base Station implementation and for Mobile Handset application. Thus, the targets are very different:

Base Station: the goal is Freq. > 1 Ghz, and Leakage < 1W
Mobile Handset: the goal is Freq. > 400 Mhz, and Leakage as low as possible

CEVA has used the Synopsys DesignWare TSMC 28 HPM standard cell library and memory compiler. If you take a look at the Power/Performance figure below, you realize that the cell selection possibilities are very wide, allowing optimization to be pushed to the limits, very low leakage for Handset application, very high performance for base station. In fact, CEVA claims to have reached 1.3 GHz, passing the target by 30% for the BS option!

Another challenge is the size of the on-chip memory, very large for a DSP core. Synopsys is offering Ultra High Density memories, offering 48% area saving (compared with the HD memory) along with a 33% better leakage, these memories have been developed to support CPU, GPU and DSP needs. You will find extremely useful information in this White Paper, “CPU, GPU and DSP Core Optimization for High Performance and Low Power”.

To know how CEVA has defined the Top Ten Bottlenecks: “Physical Design Challenges”

[LIST=1]

Global signal distance

Wait signal long distance

Memory path distance

Vector path (vector size: 512 to 1024 bit)

Density

Congestion issues Predictability

Congestion of the Clock trees

Cell and pin density

Congestion and shorts

and even more important how the design team has manage to solve these bottlenecks, making the best use of Synopsys DesignWare 28HPM Library and design tools, you will have to listen the webinar. I also recommend listening to the questions, at the end of the webinar, all of these are relevant, and you will learn from the answer too!

From Eric Esteve from IPNEST

I’d give my right ARM to be ambidextrous

I’d give my right ARM to be ambidextrous
by Don Dingee on 05-09-2014 at 8:00 am
Categories: Arm, IP

Baseball loves a good switch hitter – from Frisch to Mantle to Rose to Murray to Jones, they are a rare and valuable commodity. AMD is calling on ambidexterity for its processors in 2015 and beyond, this week tipping plans for 20nm “Project SkyBridge” parts in either ARM or X86 with a common footprint. What remains to be seen is where they bat in the lineup. Continue reading “I’d give my right ARM to be ambidextrous”

May 9, 2014December 27, 2023

4G BaseBand Support with TeakLite4? Add Also CEVA-Bluetooth!

4G BaseBand Support with TeakLite4? Add Also CEVA-Bluetooth!
by Eric Esteve on 05-09-2014 at 4:46 am
Categories: Ceva, IP

The CEVA-TeakLite-4 is the DSP IP issued from the TeakLite family, started about 15 years ago with the 16-bit, single MAC TeakLite. Now the TeakLite-4 is a 32-bit, quad MAC IP core, supporting 2G/3G/4G Wireless BaseBand or PowerLine Communication. But even the latest BaseBand computational requirement doesn’t saturate this DSP core, as it can handle CEVA-Bluetooth connectivity (Classic or Low Energy), thereby dramatically lowering the cost, complexity and power consumption of chip designs targeting smartphones, the Internet of Things (IoT), wearables and wireless audio devices.

This latest generation of DSP IP core, to be integrated into communication SoC or Audio/Voice IC, is a good illustration helping understanding why DSP standard IC business is vanishing, except maybe in very specific (low production volume) segments. But the target applications for the CEVA-TeakLite-4 DSP cores are primarily audio and voice processing in mobile, home, and automotive products in chips ranging from the smallest, lowest-power audio CODECs, to application processors, to home audio, including digital televisions (DTVs), set-top boxes (STBs), game consoles, and more. These consumer or communication segments are by nature generating high production volume, thus a SoC development is the most cost effective solution. This DSP core being a low-power, native 32-bit, variable 10-stage pipeline, fixed-point DSP architecture framework, fully synthesizable, process-independent design, this option allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency. Moreover, selecting the TeakLite-4 family allows optimizing the system, for Ultra Low-Power or High-Performance, as the designer benefit from a modular approach. The TL410 and TL411 IP are tailored to replace standalone DSP chips supporting Audio CODECs, Audio D-Class Amps or noise reduction chips, when TL42X IP are targeting Application Processor (smartphone or media tablet) or Digital TV or Set-Top-Box (STB) processors.

The Internet of Things comprises a multitude of devices, technologies and form factors, with many use cases and requirements. The CEVA-TeakLite-4 specifically targets user-centric IoT devices, where natural user interface, audio playback and voice communication represent key attributes of the device. This can include for example, voice activation, face triggering and other ‘always-on’ functionality in a smartphone, smart watch, smart home controller or wireless speakers. The ultra-low power nature of the CEVA-TeakLite-4 DSP ensures that these ‘always-on’ features consume minimal battery life. All of this functionality can run concurrently on the DSP without the need for a host CPU, reducing the die size and lowering power consumption of the overall device. Illustrating this, a real-life use case implementing Bluetooth Low Energy, always-on UI and sensor fusion on the CEVA-TeakLite-4 DSP requires less than 150K gates and consumes less than 150uW when implemented in a 28nm process.

According with Eran Briman, vice president of marketing at CEVA: “Our industry leadership and broad product offering of low power DSPs, software technologies and Bluetooth IP allows our customers to meet all of the market requirements for connectivity, audio, voice and sensor-fusion from a single vendor, all optimized for the lowest power use cases. No other player in the IP industry today can offer such a complete and robust portfolio of IPs targeting this space.“ If we look at the implementation of Bluetooth solution, you will notice that the designer has to integrates a specific Baseband hardware, along with CEVA TeakLite-4 core. Thus, the CEVA-TeakLite-4 is now capable of supporting the following on a single core:

Bluetooth 4.1 (Classic and Low Energy)
Always-on functionality e.g. voice trigger, face detection
HD audio playback and post-processing
Voice communication and noise-reduction
Sensor fusion (context awareness)
Android Multimedia Framework (AMF), supporting the offload of various processing elements from the CPU onto the DSP under an Android OS (including KitKat)

In addition, CEVA-TeakLite-4 also offers customers ample headroom to add functionality such as GNSS navigation and Wi-Fi connectivity, or add proprietary / 3[SUP]rd[/SUP] party software to further differentiate their solution. More information is available on the CEVA website at www.ceva-dsp.com/CEVA-TeakLite-4.

If you prefer a layered view of CEVA-Bluetooth solution, the above picture will help understanding the logical implementation and the various interfaces, from standard HCI to BlueRF-style RF interface, passing through (internal) APB processor interface.

Linley Mobile Presentation:

Ultra Low Power Integrated Platform for Connectivity and Audio/Voice/Sensing- Presentation

Eric Esteve from IPNEST

Wearables at Linley Mobile: Diverging views

Wearables at Linley Mobile: Diverging views
by Daniel Nenni on 05-08-2014 at 11:30 pm
Categories: Arteris, IP

The Linley Mobile Conference last week initiated a lot of discussion about emerging technologies and markets, especially wearables. Jessica Lipsky’s EE Times article captured some of the sentiments in her article, “Wearables Need Tailored SoCs.” But the conference covered a lot more ground than wearables, including mobile security, benchmarking, heterogeneous multicore computing, and always-on coprocessing.

You can download my “SoC Design Challenges of Wearables” presentation here:

My role was to give Arteris’ view on the direction of wearables, based on our close relationships with the major players in mobility, and now wearables (many of the chip vendors are the same). The goals were to ensure that people understood that the move to wearable computing is an evolution in computing (not a revolution), and that wearables portend neither the saving grace for the semiconductor industry nor the deathknell of the smartphone.

I started my presentation highlighting the past and future of wearable computing, starting with Steve Mann, whom I met while at MIT, and ending with Darth Vader.

Linley wanted me to talk more about trends and to be less technical, but I felt the need to drill into some teardowns of two types of wearables:

A “peripheral” wearable example: Fitbit Flex
A “smart” wearable example: Google Glass

Whether a wearable is “smart”, or not, is dependent primarily on three things:

[LIST=1]

Does it have the Human Machine Interface?

Can it do it’s own processing?

Can it communicate to the Internet through a WAN?

In my example, the Google Glass in not truly “smart” because it requires a wireless LAN access point to communicate to the Internet.

Although the most buzz around wearables is for consumer electronics, I posited that these markets might be the wrong ones for our industry to target if the goal is to create economically viable products more quickly. In his keynote, Linley stated that consumer wearables are a technology in search of a use case (I’m paraphrasing here) and I think the data bears this out. There’s lots of FitBits and ugly “smart” watches sitting in dresser drawers today, and this problem will only get worse as companies tackle stranger and stranger use cases in an attempt to find “the killer app.”

Wearables: In search of a Killer App

I asserted that there really are “killer apps”; namely, apps that if some people don’t have them, then they could be killed. One example is a wearable glucose-monitoring device for a diabetic person. This type of device helps the user manage a chronic condition.

Another example is the Viking turnout gear for firefighters which incorporates sensors and LED indicators to let firefighters know when they are in danger of getting a second-degree burn (there’s only 50 degrees difference between feeling pain from heat and getting burned). Firefighters getting burned on the job are acute, rather than chronic conditions.

For target markets, my proposal is to focus on medical, military and industrial safety rather than consumer markets to better understand how people will use wearable technology. These markets are smaller than the totality of consumer electronics, but there are already established use cases and therefore economic value (i.e. cash) attached to solving these problems.

Wearable technology immediately waterfalls to Smartphones
Finally, I worked hard to dispel the erroneous assertion that wearable technology will somehow supplant the mobile phone anytime soon. To make this point, I showed how the features that shipped in the FitBit Flex and Whithings Pulse in 2013 have already been incorporated into 2014’s Samsung Galaxy S5 (Disclaimer: Arteris FlexNoC interconnect IP is present in one or more SoCs within the Samsung Galaxy S5). To drive this point home we reviewed the Samsung Galaxy S5 motherboard photos from TechInsight’s teardown, highlighting the various sensors for pressure, heart rate, acceleration and direction.

With regards to wearables and smartphones, the bottom line is that wearable technology, especially sensors, will quickly waterfall to smartphones. And the smartphone will be around for a long time because it owns the Human Machine Interface with its screen for viewing and for touch entry.
Here’s my conclusion slide:

The panel discussion was the highlight of the conference for me. The following people participated in the panel and Q&A:

Pankaj Kedia, Sr. Director, Product Management and Business Development, Qualcomm
John Min, Director, Solutions Engineering, Imagination
Risto Lahdesmaki, CEO, Idean
Kevin Shaw, CTO, Sensor Platforms

It was great to hear a broad array of perspectives. There is agreement that wearables will change how we interact with and use electronic devices. What is not as clear is whether wearable adoption will occur at an evolutionary pace (my opinion), or initiate a revolution in computing and the semiconductor industry.

By Kurt Shuler, Vice President of Marketing, Arteris

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