SemiWiki – Page 825 – The Open Forum for Semiconductor Professionals

June 26, 2014June 14, 2019

What’s New with Circuit Simulation for Cadence?

What’s New with Circuit Simulation for Cadence?
by Daniel Payne on 06-26-2014 at 11:53 am
Categories: Cadence, EDA

Every year at DAC I enjoy making the rounds to see what’s new with SPICE circuit simulators, so on June 3rd I met with Xiuya Liand Dan Zhuof Cadence in San Francisco to get an update about their Spectre tool. There’s plenty of competition in the SPICE area from Mentor Graphics (Analog FastSPICE, Eldo, ADiT), Synopsys (HSPICE, CustomSim, FineSim) and others.

Continue reading “What’s New with Circuit Simulation for Cadence?”

June 26, 2014June 14, 2019

Real FPGAs don’t eat fake test vectors

Real FPGAs don’t eat fake test vectors
by Don Dingee on 06-26-2014 at 8:00 am
Categories: Aldec, EDA, FPGA

Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot less certain and a lot more time consuming. Continue reading “Real FPGAs don’t eat fake test vectors”

June 25, 2014April 10, 2025

Single Event Upsets

Single Event Upsets
by admin on 06-25-2014 at 5:04 pm
Categories: EDA

Do you know what a SEE is? It stands for single event upset. We live on a radioactive planet which is also bombarded with cosmic rays, so particles are bombarding our chips. The materials used in packaging also can create particles that cause problems, even the solder. Reliability and aging has been an area that has not been at the forefront of people’s minds while the huge volumes in leading edge processes are mostly driven by the smartphone market. If your phone crashes or reboots it is not the end of the world. But as medical, automotive and aerospace start moving into more advanced nodes we will certainly care. If the ABS system in your car crashes you certainly care a lot. And even in communications, while our cellphones are not a big deal, large enterprise routers crashing upsets their owners, so it is not just an issue for the life-critical systems.

Addressing SEE has to be done at several levels. Materials, the process, the design of cell libraries, the design itself at the SoC level. This is one of the areas that you are going to have to worry more about in the future since, like pretty much anything to do with semiconductors, the problem gets worse with each process node. The transistors are smaller and easier to flip. Memory bits are smaller and easier for a particle to cause a multi-bit upset. Analysis requires tools at the TCAD level and also at the standard design level.

Silvaco has a webinar coming up soon to go over all the issues as to how to analyze your design. The webinar will provide a discussion of the methods used by radiation effects engineers to model the impact of Single Event Effects (SEE) and some of their effects on devices and circuits. The remarkable advances in modern device technology creates specific challenges for high–fidelity radiation effects modeling of these phenomena, while the reduction of feature sizes has made the accurate modeling of SEE and other radiation effects of critical importance. These include the need for modeling Soft Error Rates (SER), Multi Bit Upsets (MBU), chip packaging, and detailed single event effects modeling at the device and circuit level.

The agenda for the webinar is:

Why understanding SEE is important
Basic mechanisms
Destructive single events effects
- Modeling and analysis –TCAD tool flow
- Device techniques for increasing resiliency to SEE
Non-Destructive single event effects
- Modeling and analysis –TCAD and EDA tool flow
- Device and circuit techniques for reducing non–destructive SEE
System methodology examples for a DC-DC boost converter, power diode, and logic block with quenching

The webinar Modeling and Analysis of Single Event Upsetswill be presented by Dr. Christopher Nicklaw, Staff Scientist at Silvaco, who has over thirty-five (35) years experience working on radiation effects in materials. It is Tuesday July 8th from 10am to 11am Pacific Time.

More details are here. Even if you can’t make that time, register anyway and Silvaco will email you a link to the on-demand webinar afterwards.

What Seeking Alpha is Telling us about Intel

What Seeking Alpha is Telling us about Intel
by Daniel Nenni on 06-25-2014 at 9:00 am
Categories: Foundries, Intel Foundry

New Media is a double edged sword for sure. The good news is that you get to read articles by people who actually work in the semiconductor industry. The bad news is that hidden agendas and disinformation abound so let the reader beware, especially if that reader is risking their retirement money!

As I mentioned before, “Understand what people say but also understand why they are saying it” and this definitely applies to Intel articles on Seeking Alpha (SA). One of the biggest SA Intel shills is Mr. Russ Fischer who is listed as a retired 35 year semiconductor professional, investor, and a MENSA member. This makes me wonder where Mr. Fischer spent his 35 years as a semiconductor professional? According to my expert speculation by the way Russ Fischer writes, he was a career Intel employee, absolutely.

The Seeking Alpha site attracts shills like moths to a flame by allowing investors to write about stocks they own and even paying them a penny per click for their efforts. Let’s look at a post Russ made to support my expert speculation that I can spot an Intel employee by the silly comments they make about the fabless semiconductor ecosystem. Let’s start with these three gems from his recent article “Intel: Perception versus Reality”.

[LIST=1]

Intel will conquer the mobile business (only an Intel employee would say that).

TSMC went gate last only after Chairman Morris Chang dictated that TSMC follow Intel(I have heard this omyth from other Intel employees).

The rest of the industry is struggling with 20nm planar processes with no sign of an answer to TriGate for another couple of years, if ever(only Intel employees call FinFETs TriGate).

First and foremost, Intel has a long LONG way to go before they “conquer” mobile and they are losing billions of dollars in the process. Remember, if not for the fabless semiconductor ecosystem “mobile” as we now know it would not have happened so show some respect here. What do you call an IDM that underestimates the power of the fabless semiconductor ecosystem? Fab-lite…

Second, during one of my Taiwan trips in 2010 I asked Dr. Shang-yi Chiang why TSMC decided on Gate-last versus Gate-first. Shang-yi was TSMC’s Executive Vice President and Co-Chief Operating Officer, he joined TSMC in July 1997 as Vice President of Research and Development (R&D) and has successfully delivered many new process technologies including 28nm. Shang-yi told me quite honestly that TSMC had both Gate-first and Gate-last 28nm HKMG architectures under consideration but concluded that, yes, Gate-first is simpler (less manufacturing steps) and would be easier to design to (less restrictive) but it was much harder to yield, especially for complex SoCs. The rest is history. TSMC successfully implemented Gate-last 28nm and achieved a dominant market share as a result.

Third, 20nm is already in production and FinFETs will arrive in 1H 2015 as planned. The irony here is that Russ completely skips over the Intel 14nm yield “struggle” and the resulting delays. Introducing new process technologies have always involved unforeseen challenges. How does a 35 year semiconductor professional MENSA not know this? The important thing is how you face these challenges and how you collaborate with your customers and partners along the way.

It really is a shame that Russ is disgracing his former employer in this fashion for a penny per click. I would not be surprised if Intel asked him to remove his employment record on his SA profile. Semiconductor executives should all know that history has shown if customers have a choice they will not do business with a company that does not play well with others, absolutely.

Xilinx has the Power Advantage over Altera

Xilinx has the Power Advantage over Altera
by Luke Miller on 06-25-2014 at 6:00 am
Categories: FPGA, Xilinx

I thought I write about one of the most important subjects in FPGAs, that is power. Power of course is not just based on node size, and it is funny why so many people are concerned about node size. If not just as important is the architectural decisions that drive down power. Do you really care if your part is 16nm or 14nm? Or do you care more about power, performance etc…

Core voltages continue to drop, and serial data rates are going up… way up. Standards, so called, like JESD204b and Hybrid Memory Cube solve many board routing nightmares and power issues BUT chew up an awful lot of GT lanes. I’m not complaining, I hate DDR but this migration highlights the leadership of Xilinx’s Gigabit Transceivers. Xilinx just finished publishing a white paper on the power advantages at their 20nm/16nm node. “Power Reduction in Next-Generation UltraScale Architecture”.

These power reductions are being realized today on real hardware by real customers. They configure and even work. Xilinx’s power performance is not only at 20nm, but below are some nice 28nm charts of how Xilinx does against the ‘competitor’. I wonder who that is?

Back to the serial interfaces that I was all wound up about. The above shows a 4 channel design, At 28 gb/s, Xilinx is running about 800mw and Altera at 1000mw. Yes this is the same node compare, 28nm. Ok, so you say big deal lukey dukey, I don’t care about 200mw. Ok, how about your design that uses 64 lanes for Hybrid Memory cube and another 32 for JESD204b? Power differences just for transceivers begins to add up. We approximately would have 19.2 Watts for Xilinx, and Altera 24 watts. So Xilinx here is 5 watts better. All the green folk just cheered.

Most designers start early in the design cycle having the goal of about being complete when the silicon rolls of the line. That means the quality of tools, specifically the models that yield the power need to be accurate. Interested in seeing how well Xilinx does in model to hardware correlation with respect to power? That is how accurate are the power estimator tools?

Xilinx is rock solid once again. Using the ‘competitors’ tools may leave you with a design that no worky because you no cooley. This is huge and it points to execution once again. The difference is Xilinx set’s design goals and achieves them. The competitor, waits for hardware to come back and then begins to write the data sheet. Like I said earlier, node is not that important. Power, performance and of course tools all lead to a quality of result that only Xilinx can deliver and can be relied upon.

OK, let’s put this all together at the system level shall we?

What more can I say? I always do wonder this, why in the world are you using Altera? I wrote about 28nm power for the most part, and the power separation will only continue coupled with accurate powering modeling from Xilinx. Makes me wonder what type of design you are going to have at 20nm?

lang: en_US

June 24, 2014June 14, 2019

Wally Rhines at #51DAC: EDA Grows From Solving New Problems

Wally Rhines at #51DAC: EDA Grows From Solving New Problems
by Paul McLellan on 06-24-2014 at 8:23 pm
Categories: EDA, Siemens EDA

Wally Rhines gave the keynote at DAC in 2004. One of the things that he pointed out ten years ago was that EDA revenue for any given market segment is pretty much flat once the initial growth phase has taken place and the market has been established. Incremental EDA revenue only comes from delivering new capabilities. Historically these have largely been in new area.

EDA started with custom layout, then added PCB, then ASIC, then COT and so on. Each new market grew EDA but the older markets remained flat. For example PCB revenue grew to a certain size and has remained pretty much that size every since.

At DAC this year Wally presented an update ten years on as where the current and future growth areas for EDA are.

Traditional EDA is flat and over the 2001-2013 period, the growth has all come from new areas: DFM has had a CAGR of 27% over the period, ESL of 11%, formal 10%, emulation 6% and so on. These new areas have risen from a relatively small base in 2001 and are now on their own represent $1.5B of revenue to put on top of the nearly $3B of traditional EDA.

Increasingly the incremental EDA revenue is not coming from completely new markets but from adding completely new capabilities to the traditional tools. So front end design has been flat but adding ESL, formal, power, signal integrity and emulation has led to a CAGR of 9.2% for front end over the last few years compared to 3.1% over the whole 2001-2013 period.

There are new challenges and new opportunities at 10/7/5nm: FinFETs require tools to deal with process complexity, thermal and stress. The lack of EUV requires capabilities to handle directed self-alignment, double and triple patterning and density balancing. These will be one basis for growth in the next few years.

Historically, EDA semiconductor revenue per transistor and EDA revenue per transistor have decreased at around 30% per year. The first is simply Moore’s law and the second reflects EDA revenue having been 2% of semiconductor revenue for at least 20 years. One big question, of course, is whether this will continue or whether the graphs we have all seen showing cost per transistor increasing reflect our future.

The basic thesis is that EDA grows from solving new problems. Some of these problems are in existing EDA markets, with incremental capability like ESL or formal. Some come from supplying traditional tools but into new markets, such as selling RET capability to foundries (who historically have not had enormous EDA budgets) or selling emulation to software developers. And some from new markets such as embedded software, cyber-security or automotive subsystems. Although the term is overhyped right now, this is growth from the internet of things, which will require security, embedded software, wireless communication, subsystems and more.

So with all of these things, new capabilities, access to new budgets, completely new markets, then Wally believes that the future of EDA is rosy. After all, given that EDA only grows from solving new problems, the fact that there are plenty of new problems is a driver for the whole EDA industry.

Wally’s full presentation is HERE.

ESL Tool Update from #51DAC

ESL Tool Update from #51DAC
by Daniel Payne on 06-24-2014 at 4:13 pm
Categories: EDA

As promised in my May 27th blog, I visited an ESL company at DAC three weeks ago that introduced two new tools:

Thermal Profiler
Power Intelligence

Continue reading “ESL Tool Update from #51DAC”

June 24, 2014

Internet of Things (IoT) Startup Showcase @ SEMICON West!

Internet of Things (IoT) Startup Showcase @ SEMICON West!
by Daniel Nenni on 06-24-2014 at 3:00 pm
Categories: ESD Alliance, Semiconductor Services

It’s hard to believe that SEMICON West is upon us once again at the Moscone Center in San Francisco. This is the premier semiconductor conference for cutting-edge equipment, processes, and materials, to solutions to today’s design and manufacturing challenges. Remember, it’s not what you know (because we all know everything already), it’s who you know and SEMICON West connects you to the people, products, and technologies advancing the future of microelectronics! Even if you are familiar with SEMICON West you may want to visit the FAQ for a refresher.

This year one of my favorite topics will be explored during anInternet of Things (IoT) Startup Showcase. If you do attend please introduce yourself, it would be a pleasure to meet you! I will be wearing my trademark blue SemiWiki polo shirt. It’s just like the Steve Jobs turtleneck thing only different.

An SK Telecom Americas Innopartners Program
Thursday, July 10, 2014
1:30pm-3:30pm

This Session brought to you by:
With 30 billion connected devices expected by 2020, the Internet of Things (IoT) is changing the way we work and live. But in order for the IoT to spring to life, innovations at the core technology level are essential. SKTA Innopartners Innovation Accelerator will showcase six innovative new IoT technology startups with onstage presentations covering four target market segments including; semiconductor and systems, telecom, enterprise/datacenter solutions, smart device related, and healthcare devices/bioinformatics. A networking “meet and greet” with industry executives and VCs will also precede the session.

SK telecom Americas is the business development and venture capital arm of SK telecom, Korea’s largest wireless operator and a global technology leader, and has worked with some of the brightest minds in VC and angel investing – and some of the biggest technology companies in Silicon Valley – to design a novel and new funding model. SKTA Innovation Accelerator seeds and accelerates core technology startups to create and manage the essential data center. The Innovation Accelerator matches entrepreneurs with industry leading strategic partners and provides initial funding up to $1M as a combination of working capital, state-of-the-art facilities, development tools and professional services (e.g. legal and financial). Entrepreneurs concentrate on developing their technologies, while strategic partners and venture capitalists access lower-risk investment.

[TABLE]
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| Welcome, Opening Remarks
Angel Orrantia
Business Development Director
Innovation Accelerator
SKTA Innopartners
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| 1:40pm-2:00pm
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| Lumiode Light Engines – Daylight Visible Microdisplays for Augmented Reality

Abid Hussain Biography
Vice President of Marketing
Arrayent
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| 3:20pm-3:30pm
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| Closing Remarks
Angel Orrantia
Business Development Director
Innovation Accelerator
SKTA Innopartners
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Please check back frequently for updates and more information as agendas develop and speakers are announced.

SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test). More than semiconductors, SEMICON West is also showcase for emerging markets and technologies born from the microelectronics industry, including micro-electromechanical systems (MEMS), photovoltaics (PV), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

lang: en_US

June 24, 2014

Is SOI Really Less Expensive?

Is SOI Really Less Expensive?
by Scotten Jones on 06-24-2014 at 8:00 am
Categories: Foundries, TechInsights

Introduction
There have been some claims made recently that planar Fully Depleted Silicon On Insulator (FDSOI) is less expensive than bulk planar processes and FinFETs at various nodes. Some of these claims suggest that FinFETs in particular are significantly more expensive. My company, IC Knowledge LLC produces the most widely used IC cost modeling software in the semiconductor industry. Recently we have developed a new version of our Strategic Cost Model that is particularly well suited for cost comparison between bulk, FDSOI (planar) and FinFETs (both on bulk and SOI). In the rest of this article I will presents some results from these comparisons.

Assumptions
One of the key objectives of this analysis is to make the comparison between the different process variants as direct a comparison as possible. Our model uses detailed process flows for each process and we have tailored the process flows to reflect the requirements of the different processes while keeping as many process details the same as possible. Specifically:

We have used an M1 half-pitch of 48nm for the 28nm node, 38nm for the 20nm node and 32nm for the 14nm node for all processes.
Each process has 10 metal layers with layers 1 through 4 at 1x, 5 and 6 at 2x, 7 and 8 at 4x and 9 and 10 at 8x the M1 dimension.
STI/Fin, gate, contact and silicide (where used) are all 1x layers (STI/Fin is 0.75x and gate is 1.3x for FinFETs).
All processes add local interconnect (1x layer) and MIM capacitors at 20nm.
All processes include mask set amortization with the same exposures per reticle.
All calculations are for a 300mm wafer fab running 30,000 wafers per month located in the United States. The fab is always assumed to be a new greenfield fab.
All processes support 3 threshold voltages.
All processes assume the same yield loss per mask.
At processes use the same multi-patterning schemes at each node.

28nm Bulk Versus 28nm FDSOI
The first case we examined is a 28nm bulk planar process modeled after TSMC versus a 28nm FDSOI planar process modeled after ST Micro. The following table summarizes the two processes:

The costs in the table are all normalized to the total cost of the bulk 28nm process being 100%.
As we can see from the table, the FDSOI process has a higher starting wafer cost but a simpler process and the net final result is a slightly lower overall wafer cost.

20nm Bulk Versus FDSOI Versus FinFET
For the second case we looked at a 20nm bulk planar modeled after TSMC, versus a 20nm FDSOI planar process modeled after ST Micro. The following table summarizes the two processes.

The costs in the table are all normalized to the total cost of the 20nm bulk planar being 100%.
From the second table we can see that the cost for the bulk planar process and FDSOI process are virtually identical. The FDSOI planar process once again has a higher starting wafer cost but the simper and lower cost process offsets the starting wafer cost.

14nm FDSOI Planar Versus FinFET on Bulk and FinFET on SOI
For the final case we will look at a 14nm FDSOI Planar process modeled after the ST Micro process and compare it to a FinFET on bulk process modeled after TSMC and a FinFET on SOI process modeled after IBM. The following table summarizes the three processes.

The costs in this table are all normalized to bulk FinFET total cost being 100%. From the third table we can see that when the same assumption set is used across all processes, FinFETs on bulk are 6% less expensive than planar FDSOI and 3% more expensive than FinFETs on SOI.

Discussion
At both 28nm and 20nm we find that planar FDSOI is roughly comparable to bulk planar processes in cost. In both cases planar FDSOI should produce a significant advantage over bulk planar in performance and or power consumption making planar FDSOI a very attractive option for 28nm and 20nm.

At 14nm we find that when making comparable yield assumptions for planar FDSOI and FinFETs on both bulk and SOI, that FinFETs are the least expensive process although only by a small amount. The current results are in contrast to some previous work that found FinFETs to be significantly more expensive than planar FDSOI at the same node. We believe the key driver of the differences in results is very unfavorable yield assumptions for FinFET processing used in the previous work. We furthermore believe that mature FinFET process yields have already been achieved by Intel and will soon be achieved by others and that such process yields will be in the high ninety percent range making yield a non-differentiating factor between the processes.

To-date, the majority of the logic producers have chosen FinFETs on bulk for the 14nm (16nm for TSMC) generation. From this analysis it does not appear that cost is a significant differentiator between these three process options. IBM is the only company known to be pursuing FinFETs on SOI at 14nm driven by IBM’s embedded DRAM on SOI technology. Once again cost is not a differentiator based on this work.

Conclusion
Using the same yield per mask layer assumptions for both planar FDSOI and FinFETs it has been shown that the costs for planar FDSOI and FinFETs on bulk or SOI are all comparable at the 14nm node. Decisions on which process to pursue are therefore expected to be driven by factors other than cost.

lang: en_US

June 23, 2014

The “Key” to Reality

The “Key” to Reality
by Bill Boldt on 06-23-2014 at 9:00 pm
Categories: Foundries

If we wanted to reduce the definition of authentication to its most Zen-like simplicity, we could say authentication is “keeping things real.” To keep something real you need to have some sort of confirmation of its identity, as confirmation is the key (so to speak).
Continue reading “The “Key” to Reality”