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June 23, 2014

Cliff Hou’s DAC Keynote

Cliff Hou’s DAC Keynote
by Paul McLellan on 06-23-2014 at 10:21 am
Categories: Foundries, TSMC

Cliff Hou had two major appearances at DAC this year. He gave the opening day keynote…and he wrote the forward to Dan and my bookFabless: the Transformation of the Semiconductor Industry which about 1500 lucky people got a copy of courtesy of several companies, most notably eSilicon who sponsored the Tuesday evening post-conference party where we signed several hundred copies. You can still get a copy if you missed out, just click on the book cover on the top left hand side of the front page of SemiWiki.

Cliff’s keynote was about the future challenges of getting to 10nm and beyond. 14/16nm (they are basically the same despite the different numbers) are pretty much a done deal. Not yet in volume production but on track to get there later this year.

Cliff started by talking about mobile which is what drives semiconductor leading edge processes. Design innovation drives process innovation which enables more design innovation. As a result we have product innovation. It seems like we have always had smartphones but in fact the iPhone only came along 7 years ago. Up until then we had dumbphones although some marketing guy at Nokia cleverly called them feature phones to make them seem…almost smart.

Of course every process generation things get harder. Double patterning, FinFETs, multiple-patterning and so on. The big challenge is that as we approach 10nm, everything becomes more costly and so the economic driver that has been behind the semiconductor industry for the last few decades is weakening. It seems clear that the technical challenges can be overcome but at what cost?

There are two different sets of challenges getting to each new process node: the process issues, mostly around lithography, and the ecosystem issues.

lithography: continue to scale 193nm immersion
device: continue to deliver 25-30% speed gain at the same or reduced power
interconnect: address escalating parasitics
production: ramp volume in time to meet end-customer demand
shortened development runway to meet product windows

Design and technology co-optimization used to be fairly straighforward. The best local optimum was also the best overall optimum: shortest wire length the best, best gate-density the best area scaling, best technology also best cost. But these rules don’t hold any more. Everything has to be co-optimized from process, EDA tools and IP. If one of these is not up in time then the designs cannot be completed and the fab will not be filled as soon as capacity is available. And given the cost of a fab at $5-8B then a fab that is not full costs a huge amount in depreciation.

The time to get to market is speeding up too. First test chip, first PDK, first shuttle, volume production, the big milestones on a new node are getting compressed. At 10nm, Cliff reckons they will be roughly half the time they had at 28nm. The cost of bringing the process up and building the fabs to run it makes it imperative to start recovering the cost as soon as possible.

Bottom line: this all requires much closer collaboration between all the partners to make everything work in a timely manner. This is the key to unlock 10nm and beyond and turn the vision into reality.

The Secret Essence of an IoT Design

The Secret Essence of an IoT Design
by Pawan Fangaria on 06-23-2014 at 7:00 am
Categories: EDA

Today the semiconductor industry along with electronics industry is looking up to capitalize from massive expansion foreseen in IoT (Internet of Things) domain. In simple terms we can consider IoT as connectivity between machines which can communicate with each other and work as programmed. In localized applications such as factory automation which may require one-way communication with dedicated private network, the machine-to-machine connectivity can be easier with lesser complexity. But what happens when in the real world of IoT the devices are exposed to public network and are needed to make intelligent decisions while maintaining proper security? How can a patient in India be monitored from a specialized medical institute in USA under adequate privacy? The simple machine-to-machine model is no more adequate. Integrated software platforms are required which can enable development and integration of code from various heterogeneous sources to build intelligent devices which can have secure connections through autonomous network insertion and are capable of making decisions with bi-directional communication. And the platforms must be extensible to accommodate upcoming protocols of connectivity, security and other needs as the world of IoT is in expansion mode. Also, an efficient power management is needed for devices as many of them are placed in remote areas and they operate on battery.

The software to maintain connectivity, security and power, if considered in true sense of IoT can be very complex. In IoT world, devices can be dynamically added or removed from the network; the resource discovery and service announcements are done autonomously. The zero configuration networking protocols such as mDNS (multicast Domain Name System) and DNS-SD (DNS-based Service Directory) support such services without needing any central server, thus enabling scalability in the IoT networks. The architectures such as REST (Representational State Transfer) should be leveraged to maintain separation between client and server that ease in network scalability and improve performance and security.

As IoT devices support bi-directional data and can be connected on dispersed public networks through a horde of connectivity options such as Bluetooth, Wi-Fi, ZigBee and so on, they are highly susceptible to unscrupulous attacks. In order to protect the IoT system and devices, all kinds of security threats (active and passive) must be detected, neutralized and corrected. Various checkpoints such as encryption, authentication, and source of data before its transmission must be employed. The protocol OCSP (Online Certificate Status Protocol) streamlines the client side resources required for x.509 certificate verification. The TLS (Transport Layer Security) which uses AES-256 (Advanced Encryption Standard) and 3DES can be used to provide high level of encryption required for IoT devices. Also MAC (Message Authentication Code) is used to ensure integrity of the message without any alteration during transmission.

Power management is another issue for IoT devices which must consider all avenues of power saving. Fortunately, there are several methods (e.g. DVFS, sleep and idle modes, clock gating, hibernate etc.) and low power technologies available to optimize power; however the underlying software must be designed to gain full advantages of these techniques.

So, coming to the core question, what must be the essence of an IoT design which can keep it running by fulfilling all the above needs amid several complexities? It’s the real-time operating system and software on top of it which works behind the scene and enables the IoT devices to work flawlessly and intelligently as desired under various networking and security protocols without any security breach. I like the Nucleus RTOS provided by Mentor Graphics which is an ideal full-featured underlying RTOS framework for an integrated IoT solution.

Nucleus is a widely deployed and scalable 3KB microkernel based RTOS designed for today’s IoT world. It supports an array of networking and security protocols with high performance connectivity and integrated power management system. It fits nicely into a memory constrained MCU-based device, and yet provides the functionality required for IoT systems.

The connectivity options include widely available Wi-Fi, Bluetooth, BLE (Bluetooth low energy), USB 2.0/3.0 for IPv4/IPv6 based networks and so on. The architecture is extensible to include additional software protocols as required. A full featured IPv4/IPv6 stack with over 50 protocols and support for zero-configuration networking that includes mDNS and DNS-SD is available for networking.

The security is provided for data in storage as well as in transmission. While in storage, the data can be encrypted and password protected. The security during transmission includes TLS/SSL with encryption options including AES-256, 3DES, DES, RC4 and many others. OCSP authentication and Hash functions are available to ensure message integrity without any alteration.

An extensive Power Management Framework available in Nucleus lets the IoT devices operate under various low-power modes through intuitive API calls. A complex device can be transitioned into hibernate or standby mode by safely turning off peripherals, moving code into non-volatile memory and changing the operating point of the device.

A complete underlying RTOS like Nucleus can offer software developers and design architects a versatile framework for developing IoT devices and systems that can work unabated with their full potential in public network and real life situations. Andrew Caples, Senior Product Marketing Manager at Mentor has described in great detail about the requirements of IoT and Nucleus in his whitepaper posted at Mentor’s website. It’s a nice read.

Intel Invests in the Fabless Ecosystem!

Intel Invests in the Fabless Ecosystem!
by Daniel Nenni on 06-22-2014 at 11:00 am
Categories: Ansys, Inc., Cadence, EDA, Intel Foundry, Siemens EDA, Synopsys

During my illustrious career one of the most useful axioms that I use just about everyday day is: “Understand what people say but also understand why they are saying it.” This certainly applies to press releases so let’s take a look at what Intel unleashed during #51DAC (in alphabetical order):

ANSYS And Intel Collaborate To Deliver Power, EM And Reliability Sign-Off Reference Flow For Customers Of Intel Custom Foundry –

Cadence and Intel Collaborate to Enable a 14nm Tri-gate Design Platform for Customers of Intel Custom Foundry –

Mentor Graphics Tools Fully Enabled on Intel’s 14nm Processes for Customers of Intel Custom Foundry –

Synopsys and Intel Collaborate to Enable 14-nm Tri-Gate Design Platform for Use by Customers of Intel Custom Foundry–

Building a fabless design ecosystem is a very difficult thing. TSMC has been doing it for 25 years which resulted in the Grand Alliance we have today. As the #1 pure-play foundry, ecosystem partners swarm TSMC. The big challenge is silicon validation which is what the TSMC OIP is all about. As the #1 consumer of EDA tools, Intel has a distinct advantage since they write some very big checks. Close to half a billion dollars a year I am told. Samsung is in a similar position, being one of ARM’s biggest customers Samsung foundry definitely has the IP advantage. Samsung also writes some very big partner checks.

When GlobalFoundries got started, they wrote some really big checks to EDA and IP vendors as well. In fact, they were some of the largest single orders for partners I have seen. If I remember correctly Virage Logic got $6M, all for the greater good of the fabless semiconductor ecosystem, absolutely.

Big ecosystem checks do not necessarily mean big wafer orders though so we will have to wait and see. It certainly is a step in the right direction and it tells me that Intel will be back for 10nm foundry business, even more agressivley than 14nm. The 10nm ecosystem press releases will be coming next. It’s a four horse race so let’s see who wins the 10nm PR derby.

I also think it is interesting to see the embedded quotes. Since these four press releases came out within minutes of each other it makes speculating even more fun.

“A close collaboration between Intel Custom Foundry and ANSYS on reliability verification reference flow for 22nm and 14nm enables our customers to efficiently deliver more robust and reliable designs for next-generation electronic products,” said Venkat Immaneni, senior director, Foundry Design Kit Enablement, Intel Custom Foundry. “This platform enables our customers to use an industry-leading power, EM and reliability sign-off solution on our design platforms.”

“Our collaboration with Cadence on tools and low power memory interface IP will allow our customers to take advantage of Intel’s 14nm design platform and design differentiated products for their markets,” said Ali Farhang, vice president, Design and Enablement Services, Intel Custom Foundry. “We are working together to ensure joint success of our customers.”

“We are very happy to be working with Mentor Graphics to ensure that a full suite of simulation and verification solutions are in place and optimized for our 14nm processes,” said Venkat Immaneni, Senior Director of Foundry Design Kit Enablement at Intel Custom Foundry. “This means our mutual customers can use the tools they have in place and are comfortable with, while taking advantage of Intel’s process leadership.”

“The combination of Intel’s 14-nm Tri-Gate process technology and Synopsys tools, memory and interface IP enables designers to create industry-leading SoCs for their target markets,” said Ali Farhang, vice president, Design and Enablement Services, Intel Custom Foundry. “By building on our successful collaboration on Intel’s 22-nm design platform, we have been able to seamlessly extend the solution to our 14-nm process technology.”

Before I give my expert speculation of the quotes maybe you can offer yours?

ARC EM DSP supports Always-on Devices

ARC EM DSP supports Always-on Devices
by Eric Esteve on 06-22-2014 at 3:01 am
Categories: IP, Synopsys

The ARC EM family is the low-power, embedded and low footprint processor part of the larger ARC processor. To target the ultra low-power markets like wearable and IoT, Synopsys has added DSP capabilities to EM5D and EM7D. To be specific, these cores are optimized for ultra low-power control and DSP, thanks to:

Energy-efficient 3-stage RISC pipeline
Unified single cycle 32×32 MUL/MAC unit
Energy-efficient signal processing of voice/speech, audio and sensor data
Operating Floating Point Unit (FPU)

Thus, the EM5D and EM7D cores are especially suited to always-on voice activated and sensor processing applications. The dynamic power consumption of the ARC EM processors can be as low as 3 uW/MHz, particularly well-suited for wearable devices and battery powered applications.

But users are demanding IoT and wearable devices with longer battery life, this is not surprising, and at the same time expect more complex features and better user interface, requiring higher levels of signal processing… and lower power consumption!

As you can see on the picture below, the ARCv2DSP instruction set architecture (with over 100 DSP instruction) is separated with the parallel 3-stage pipeline, counting 32×32 MUL/MAC unit, square root, divide and butterfly acceleration, as well as various size (2 x 32b/40b or 1 x 64b/72b) accumulators. To cope with customer demand for flexibility, DSP features are configurable, and can be tailored to suit the application. But we have to remember that the power consumption is the most critical feature, thus ARC EM5D and ARC EM7D benefit from enhanced (8 states) sleep modes. Synopsys is claiming 7 uW/MHz power specifications for a core running up to 530 MHz on 40nm LP and delivering 1.77 DMIPS/MHz (or 3.41 CoreMarks per Mhz).

Synopsys propose an evaluation of the power consumption of ARC EM5D (using an RTL simulation including both logic and memory dynamic power) running Sensory’s Power Sound Detection from the TrulyHandsfree Voice control technology and consuming 4 uW, comparing with Competition A (maybe Tensilica?) at 17 uW and Competition B (maybe CEVA?) at 20 uW. Impressive! I can’t guarantee that these data from Synopsys’s competitors are the latest available, neither who is who, even if I am almost sure that A and B are Tensilica and CEVA, or reverse.

Another interesting benchmark from Synopsys: the Power Performance Area (PPA) comparison of the EM5D (the ARC core with DSP capabilities) with:

ARM Cortex-M4
MIPS icroAptiv
Tensilica mini108
ARM 968

When interpreting this diagram, you have to remember that you are an engineer, but I think the picture is also accessible to non-engineers. The performance is expressed by the top circle, in total DMIPS, on the Y axis. The power, in mW is the right edge of the circle, on the X axis. And the (Silicon) area is the diameter of the circle. Thanks to the selected competitors, you may compare the circle area (even if there is a geometric amplification, as area is function of the square of the diameter…), as all the competitor’s products exhibit a larger area.

As with any benchmark, the result will depend of the selected competitors, and the selected technology. A larger area on 65LP technology could have a negligible impact on 28nm technology, for example… Nevertheless, these benchmark result qualify the ARC EM DSP enhanced family for addressing IoT and wearable markets, requiring ultra low-power and signal processing capabilities, optimized for signal processing of always-on voice/speech, audio and sensor data applications. The ARC MetaWare toolkit complement this H/W offer, providing rich DSP software library and C/C++ Compiler.

From Eric Esteve from IPNEST

Enabling Technologies that Will Shape the next Wearables

Enabling Technologies that Will Shape the next Wearables
by Daniel Nenni on 06-21-2014 at 10:00 am
Categories: EDA, Events

One of the benefits of spending the last 30 years working in Silicon Valley and publishing a fabless semiconductor book is that I get invitations to speak at events I would normally be attending. Being on the other side of the podium is truly a unique experience and one worth pursuing, absolutely. This month I spoke at #51DAC about the book and last week I presented my thoughts on the competitive landscape to a private gathering of 100+ semiconductor professionals. We are entering exciting semiconductor times with immense opportunities for entrepreneurs which I would liken to the fabless gold rush of the 1990s. During that time, TSMC brought us the pure-play fabless semiconductor ecosystem that enabled hundreds of fabless companies that are now worth billions of dollars.

One of my favorite fabless success stories, which is in the book, is Chips and Technologies. At one point in time C&T had more silicon on the PC motherboards than Intel and you have to ask yourself why? Because the fabless business model enables innovation that is not available from the IDMs, simple as that. This cycle will repeat itself now that the industry is in consolidation mode which is freeing up fabless semiconductor entrepreneurs en masse.

Next month I will be speaking at the CASPA 2014 Summer Symposium. Take a look at the keynote and panel speakers below. This is an excellent opportunity to network and investigate what is next for the semiconductor industry. Calling all semiconductor entrepreneurs! I hope to see you there:

“Enabling Technologies that Will Shape the next Wearable Applications”穿戴式应用的未来的支撑技术

Create Mainstream Market Opportunities For A Broad Range of Industries 为不同行业创造主流市场的机会

Abstract:
“Now that wearables are all the craze, how to make sense of all the hype? Wearable startups are popping up everywhere with many innovative ways to address people’s lifestyles and routines in an attempt to augment our lives.

The challenge is to find that spark that will make wearables more appealing, relevant and useful to the population. Lessons learned from the first wave of wearables…Addressing the continued challenges of unobtrusiveness, simplicity of use and power management. And how to gain wider adoption outside of the Bay Area / Silicon Valley, where Google Glass and other wearable gadgets are the norm? More and more wearable applications and proof-of-concepts are beginning to emerge, but not yet widely ubiquitous around the world. What will it take to take wearables to the next level? Wearable technologies should solve problems and enhance our lives rather than hinder it.

Today’s distinguished speakers and panelists of visionaries and technologists will talk about the first generation of wearable devices, share their personal experiences and challenges they have faced, as well as give us a glimpse into what the next generation of wearables will look like.”

Date:July 12[SUP]th[/SUP], 2014 Saturday
Time: 12:00-5:30pm
Location: Intel SC12 Auditorium
3600 Juliette Ln. Santa Clara, CA 95054

Registration:Here

Speaker Roundtable: Here

Agenda:
12 pm – 1 pm Registration & Networking
1 pm – 3 pm Welcome & Keynotes
3:10 pm – 4:45 pm Panel Addresses and Discussion
4:45 pm – 5:30 pm Speaker Roundtable: CASPA Members Only (online registration w/ $5)

Keynotespeakers:

Moderator: Daniel Nenni, SemiWiki

Jack Young, QUALCOMM Life Fund, QUALCOMM Ventures (Wearables expert)
Kambiz Hooshand, Archimedes Ventures (IoT expert)
Hing Wong, Walden international (China start-ups expert)

Panel speakers:

Greg McNeil, Innovation Labs Flextronics (Wearables)
Kelvin Low, Senior Director Foundry Marketing SSI
Sam Massih, Director, Wearable Sensors
Jeff Tsai, Ceo Wellex (Wearables)

Founded in 1991, CASPA has developed into the largest Chinese American semiconductor professional organization worldwide. Currently CASPA has more than four thousand individual members covering multiple disciplines. Most of them are semiconductor professionals working in Silicon Valley, Southern California, Oregon, Washington, Arizona, Texas, New York, China, Taiwan, and Singapore. CASPA also has more than 70 corporate sponsors, including EDA, design, IDM, foundry, packaging / test, venture capital, science and technology development parks, legal and financial service companies located in the United States, Taiwan, Hong Kong, China, Singapore and Japan.

Noise-Coupled Analysis for Automotive ICs at DAC

Noise-Coupled Analysis for Automotive ICs at DAC
by Daniel Payne on 06-20-2014 at 2:00 pm
Categories: Ansys, Inc., EDA

My favorite method to learn about EDA tools at DAC is by listening to actual IC designers, so on June 3rd I heard Jacob Bakker from NXP talk about his experience with noise coupled analysis for advanced mixed-signal automotive ICs.

Continue reading “Noise-Coupled Analysis for Automotive ICs at DAC”

June 20, 2014June 14, 2019

Intel & Ansys Enable 14nm Chip Production

Intel & Ansys Enable 14nm Chip Production
by Pawan Fangaria on 06-20-2014 at 10:00 am
Categories: Ansys, Inc., EDA, Foundries, Intel Foundry

In the semiconductor industry, it feels great to hear about the process technology shrinking to lower nodes along with innovative transistor structures that offer major gains in PPA (Power, Performance and Area). However, it requires huge investment of capital, time and effort from foundries to conceptualize, prototype and prove such technology for production. In order to design large chips based on such technology, robust design automation tools are required that must confirm to the complex foundry rules and constraints imposed by such technology and also fulfil the challenging requirements of PPA and reliability for the chip. The key is to produce chips with high yield and reliability that lasts for long duration.

I think most of us know about Intel’s new fabrication technology for 3D transistors, popularly known as Tri-gate transistors which can have multiple source-drain channels and a vertical gate overlapping each channels from three sides, thus reducing leakage and power consumption significantly and increasing speed with quick switching of transistors. Since this technology is proven, we now have started hearing about reference flows for semiconductor designs involving various EDA tools qualified with this technology. I am particularly impressed with Ansysand Intel announcementthis month about their production proven reference flow for ‘Power, EM and Reliability Sign-off’ of designs based on Intel’s 14nm Tri-gate process.

The reason I liked it is because very recently I blogged about Ansys’s RedHawk 2014 platform which addresses critical challenges of high density, high performance FinFET based designs to produce new generation of complex SoCs with high degree of reliability including power, noise, EM and ESD effects. Although FinFET and Tri-gate transistors have similar structure, it is important that Intel has qualified through its custom foundry the complete design flow based on its Tri-gate technology by involving multiple tools of Ansys and made it commercially available as reference flow for its custom foundry customers in the mobile and cloud market segments which typically need very low power consumption, high speed of operation and lower area. I’m sure this design flow and technology will prove beneficial for other market segments as well because most of the semiconductor designs are becoming PPA critical day-by-day.

This reference flow involves RedHawk[SUP]TM[/SUP]for SoC power and EM sign-off, Totem[SUP]TM[/SUP]for custom IP power and EM integrity, and PathFinder[SUP]TM[/SUP] for full-chip ESD validation, thus completing top to bottom flow for power, noise, EM and ESD reliability sign-off.

RedHawk provides chip, package and system level analysis and sign-off for dynamic power integrity, noise and reliability of low power, high performance SoCs. It checks for simultaneous switching noise, decoupling capacitance, package inductance, power and signal wire electromigration, ESD protection, RTL-to-GDS power closure and so on and signs off the design for power, noise and reliability with silicon correlated level of accuracy.

Totem is an ideal tool for IP sign-off with full-chip layout based power and noise analysis for mixed-signal designs. It can very effectively be used for early stage prototyping, designing of package and power network and signing off the chip with accuracy.

PathFinder provides ESD (Electro-static Discharge) integrity (with HBM and MM checks) to address much needed reliability of designs at such lower nodes. It can exhaustively analyze the whole design to identify potential weaknesses which may expose the chip to ESD related failure. It can be used from early prototyping to final sign-off stages of the chip to improve yield and eliminate conditions that can lead to any ESD event.

The confidence of this flow at 14nm Tri-gate process is much higher as it is production-proven and is an extension from the previous collaborative work of Intel and Ansys on 22nm technology. My feeling is that in coming days, this flow will prove very effective in bringing the main stream production on 14nm Tri-gate technology involving Ansys’s design and analysis tools for power, noise and reliability.

On the Road from Makers to Consumers

On the Road from Makers to Consumers
by Don Dingee on 06-20-2014 at 12:00 am
Categories: Foundries

It’s time to break with conventional thinking. For decades, the measure of success for semiconductors has been OEM design wins. Most consumers haven’t known, or cared, about what is inside their electronic gadgets, as long as they work. That may be about to change, because a new intermediary is finding its voice – and being heard in high places. Continue reading “On the Road from Makers to Consumers”

June 19, 2014

Workshop: Embedded Applications and Kernels

Workshop: Embedded Applications and Kernels
by Daniel Payne on 06-19-2014 at 6:13 pm
Categories: EDA, General

Design Automation Conference Workshop on Suite of Embedded Applications and Kernels

In June, the first Suite of Embedded Applications and Kernels, or SEAK, workshop at the 2014 Design Automation Conference in San Francisco introduced a new Defense Advanced Research Projects Agency program in the area of embedded system benchmarking for U.S. Department of Defense-related applications. SEAK aims to define a new, open suite of benchmarking with a novel methodology in terms of performance and power to evaluate end-to-end embedded systems for DoD’s application areas.

Continue reading “Workshop: Embedded Applications and Kernels”

June 19, 2014

A Brief History of QuickLogic

A Brief History of QuickLogic
by Paul McLellan on 06-19-2014 at 10:18 am
Categories: FPGA, QuickLogic

Quicklogic was founded in 1988 as a fables semiconductor company supplying anti-fuse devices. In fact VLSI Technology, where I was working at the time, was their foundry.

Although today anti-fuse is often used as a generic word for one-time-programmability, the origins of the name are grounded in reality. In a fuse, like the things we used to use before we had circuit breakers in our houses, if the current gets to high, the fuse-wire melts and thus breaks the circuit and so protects the wiring from damage or starting a fire. Anti-fuse works the other way around. A non-conducting bit of the circuit becomes permanently conducting if a high current is passed through it, so rather than breaking the circuit, it makes the circuit. Quicklogic called their implementation ViaLink technology since it basically made a non-conducting via become conducting.

In 1991 they introduced what were then the industries highest performance, lowest power FPGAs based on this technology. A couple of years later they introduced open tool synthesis to make programming the devices more straightforward. In 1997 they introduced their first devices combining hardwired logic with programmable logic fabric.

In 1999 Quicklogic went public on Nasdaq.

In 2001 they introduced their first devices combining processors with programmable logic. In 2007 they tweaked their business model and introduced their Customer Specific Standard Product (CSSP) customer engagement model, combining both hardware and software to produce innovative products for mobile and industrial customers. This provides the flexibility of an FPGA without requiring the customer to do their own design, combined with the focus of an ASSP without the high NRE and long lead-time.

The following year they introduced the PolarPro II designed to meet the connectivity, intelligence, security and system logic requirements for mobile applications.

In 2010 they introduced ArcticLink II VX providing an innovative approach to reducing power used by the display in mobile devices, resulting in 25% batter extensions in smartphones. The technology is known as Visual Enhancement Engine (VEE). By varying the display backlight power depending on what is being displayed, power can be saved without impacting the user experience. Since then various more advanced versions of this technology have been brought to market.

The most recent product offerings have been:

ArcticLink 3 S1 ultra-low power sensor hub offering OEMs always-on context awareness at a cost of under 2% of battery life
PowerPro 3, their first one-time programmable logic-devices for mobile and industrial markets
The catalog CSSP product strategy

And earlier this month they announced two products, the S1 wearable sensor hub and software for recognizing tap and wrist rotation for use in watch-like wearable devices. The always-on power consumption is less than 250uW. I wrote about them in an earlier post here.

CSSPs are complete, customer-specific solutions that include a combination of silicon solution platforms, Proven System Blocks (PSBs,) customer-specific logic, software drivers and firmware. CSSPs extend battery life, provide alway-on context awareness, improve the viewability of images on mobile displays and add differentiated features to handheld mobile devices. QuickLogic supplies leading edge, low-power customizable semiconductor sub-system solutions for tablets, smartphones, broadband data cards, secure access data cards and mobile enterprise products. These solutions include storage, I/O, display, network and memory.

More about Quicklogic on their website here.