SemiWiki – Page 822 – The Open Forum for Semiconductor Professionals

RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)

May 17, 2014

Intel’s Manufacturing Lead Explained

Intel’s Manufacturing Lead Explained
by Daniel Nenni on 05-17-2014 at 4:00 pm
Categories: Foundries, Intel Foundry

The calls from Wall Street keep coming with basically the same set of questions: “Does Intel really have a 2-3 year process lead? Can Intel lead the foundry segment? Can Intel Lead the Mobile SoC Segment?” The feeling amongst the buy and sell side investment people is that unless Intel can lead a market they will not stay in it (Intel TV). Given that, my answers are no, no, and no, absolutely.

The calls I get from Wall Street are generally a direct result of articles published on Motley Fool and Seeking Alpha. They pretty much let anyone post on these sites and Seeking Alpha even lets you post under pseudonyms. From what I have read there is very little if any actual semiconductor experience behind these articles yet they talk semiconductor with authority. They all have disclaimers at the bottom saying what stocks they own but that gets lost when people start quoting and cutting and pasting from the articles.

Disinformation of course is a competitive weapon and something Intel is very good at. Most of these authors are spoon fed PR stuff, they Google the rest to support what’s in the spoon. Add in the personal bias of owning the stock and you get a serious amount of disinformation which is why Wall Street keeps calling.

But of course I have a bias too. I do not trade stocks but having grown up in the fabless semiconductor ecosystem I’m very biased for it. Semiwiki even published a book on it “Fabless: The Transformation of the Semiconductor industry.” That is why I get the calls, so they can hear both sides of an issue, which can lead to a much more informed investment decision.

The real game changer in the semiconductor industry is not Intel but Samsung. Samsung is going after Intel to be the world’s largest semiconductor company and I believe it will happen, absolutely. Just look at their financials and aggressive marketing tactics. This company is out to win at all costs.

Samsung’s recent announcements with GLOBALFOUNDRIES and STMicroelectronics provide additional pieces of that roadmap. Samsung is now second sourcing a 28nm FD-SOI solution which is above and beyond what TSMC offers and Samsung is now driving 14nm process development rather than following IBM.

The advantage of working in Silicon Valley for 30+ years, meeting people face-to-face, and developing mutually beneficial relationships is access and honesty. After talking to both TSMC and Samsung about FinFETs I can tell you with a great amount of certainty that designs have taped-out, yield is better than expected, and risk production will start in Q4 2014. TSMC and Samsung will both ship close to 1M FinFET wafers in 2015.

Intel has struggled with 14nm of course as reported accurately on SemiWiki last year. Let’s not forget that Intel CEO BrianK held up a laptop at last year’s Intel Developers Forum and crowed, “14nm is up and running!” Today Intel claims 14nm will be “up and running” in 2H 2014 in the shape of Broadwell (PC) and CherryTrail (SoC). If that is in fact true, Intel has a six month manufacturing lead at 14nm. I wonder what BrianK will hold up at this year’s IDF?

It’s a shame Intel does not disclose wafer shipments so we can do an apples to apples comparison here. How about it Intel? Show us a little FinFET transparency? How many 14nm wafers are you going to ship next year? Of course you would have to break out microprocessor and SoC wafers because as we all know SoCs are a much harder to produce.

Bottom Line: Intel’s purposed manufacturing lead is a paper tiger, absolutely.

Also Read: Intel’s SoC Challenge!

Secret to Beating Your FPGA Competitor’s Design

Can I ask you a personal question dear reader? It is only fair, you know so much about me and all, so here goes… Why are you still hand coding you’re FPGA design? Surely you are not hand coding interfaces, like PCie, SRIO, DDR, GbE, JESD204B, HMC etc… Correct? OK, why then are you still hand coding the guts of the world’s best, super-duper shiny Xilinx FPGA? And yes, I did say world’s best, best in DSP, IO, SoC, IP, etc… So how do you plan on using the 8 TMACS available to you in the Xilinx Kintex-115 via the 5520 DSP? Which are the widest and fastest in the FPGA world. Can you say nice Dynamic Range?

We get comfortable don’t we? We engineers do not like risk and giving up control. I have said this before but I have not written a DSP function by hand since 2011. Been writing them in C/C++. Let’s face it the Xilinx Virtex-II Pro had like 232 DSP, and we were wowed, ‘this is it, it does not get better than this’!

I think we all agree that a VME rack of 8 boards with 3 Virtex-II Pro FPGAs per board all collapse down into a few UltraScale FPGAs. That is mind boggling, but who is doing the firmware design? Herein lies the problem. As the FPGA Blob keeps eating functionality around it, we are left with a very formidable problem of getting that system designed and integrated on that FPGA. Since I am a RADAR/EW fella, the problem at hand is usually intense very parallel math pipes. FIR filters, FFT’s, DFTs, Complex Mults, QR Decomposition, CFAR, blah, blah…Is VHDL or Verilog coding going to get you to the finish line, on time, under budget? Not to burst your bubble but probably not, and defiantly not if your competitor is using Xilinx’s Vivado HLS. (High Level Synthesis). Vivado HLS handles fixed or floating point data types. So you need weights for that Adaptive Beamformer? You can easily design a QR decomposition core in a few hours, for real, and complex data as well. From a RADAR perspective this means you can design the whole beamformer, pulse compressor and doppler filter in one Xilinx UltraScale FPGA, fixed and/or float. Same idea applies to any function you can dream of.

The above results are real examples who have tasted and seen that the power of Xilinx’s Vivado HLS is key to having the edge over the competitor. The design time is greatly reduced due to simulation of the design takes place as a compiled C/C++ executable not RTL. The Math, Latency, device usage and clock frequency are verified within minutes of the design. RTL simulation for a Doppler Filter card in a RADAR system would take days of RTL simulation and then weeks to chase down bugs to fix the design. Not so using C/C++, the simulation time is in seconds. The HLS design also accepts change and is truly portable. The same code you use in the programmable logic in the Xilinx FPGA easily compiles on the ARM core in the Zynq. Times are changing much like the days of assembly migrating to compilers. Now is the time to make the move to the most valuable tool in the Xilinx FPGA designer’s tool box, Vivado HLS.

lang: en_US

May 16, 2014June 14, 2019

Low Power Design

Low Power Design
by Paul McLellan on 05-16-2014 at 9:08 pm
Categories: EDA, MunEDA

Audience:
Circuit designers, project leaders and managers responsible for analog/RF low power design
| style=”white-space: nowrap” | 2014-05-19
2014-05-19
2014-05-19
2014-05-19
2014-05-19
| style=”white-space: nowrap” | 08:30 BST
09:30 CEST
13:00 IST
15:30 CST
16:30 JST
| 01:00
| style=”text-align: center” |
Dr. Marat Yakupov
MunEDA GmbH
| style=”text-align: center” |
Dr. Marat Yakupov
MunEDA GmbH
|- style=”font-weight: bold; background: #ccc”
| colspan=”6″ style=”padding: 2px” | Description
|-
| colspan=”6″ | Low power consumption is a major design objective of integrated circuits for mobile and battery-driven applications. Particularly analog/RF designers must balance complex and difficult trade-offs between various circuit performance metrics, robustness, and power consumption. In this webinar we show how MunEDA’s circuit sizing and analysis tool suite WiCkeD helps the analog designer achieve better design results in a shorter time. Basics of analog low power circuit sizing methodology will be discussed, as well as practical circuit applications.
|-

So it all depends on what sort of design you are doing. Big digital block, lots of clock gating and stuff. But a big analog block. Not so quick. But MunEDA has a webinar to help you.

Analog/RF designers must balance complex and difficult trade-offs between various circuit performance metrics, robustness, and power consumption. In this webinar they show how MunEDA’s circuit sizing and analysis tool suite WiCkeD helps the analog designer achieve better design results in a shorter time. Basics of analog low power circuit sizing methodology will be discussed, as well as practical circuit applications.

Who knew state of the art design could be so wicked? Or WiCkeD. OK, that is the most weird capitalization I’ve ever seen.

Anyway, MunEDA has this webinar coming up on all this stuff. Wicked is actually a tool suite for nominal and statistical design. Which is basically design, these days. If you are in an advanced process there is simply a lot of stuff you simply can’t ignore. And for analog design the possible errors are so large that you need to look at this stuff whatever process generation you are using.

The webinar is titled Full-Custom Low Power Design Methodology with MunEDA WiCkeD and is presented by Marat Yapupov from MunEDA in Mun (that would be Germany). It is at 9.30am European time which is 3.30pm or 4.30pm in Asia. Sorry Californians, you don’t want to know the time in your area (OK it is half an hour after midnight).

The registration page is here.

Calypto @ #51DAC Must See!

Calypto @ #51DAC Must See!
by Daniel Nenni on 05-16-2014 at 7:00 pm
Categories: EDA

DAC 2014 in San Francisco promises plenty of new information on emerging low power techniques and faster ways to get to working, fully verified RTL using high level synthesis and formal verification. Get the latest from the industry leader in technologies for high level design and verification and low power RTL designby attending our sessions at DAC. These in-depth presentations and demos by our engineers will demonstrate solutions for designers to create high quality and low power electronic systems for today’s most innovative electronic products.

Please see the topics and registration times below:

Ciena: Cutting Design and Verification Time for a Coherent Optical Processor with HLS (User Presentation)Boris Hristov from Ciena describes Ciena’s DSP design flow using Catapult[SUP]®[/SUP], and how HLS can make major reductions in ASIC development time.
Monday: 4:00 PMor Tuesday: 11:00 AM

Google: G2 VP9 Hardware Decoder Development Using Catapult HLS (User Presentation)
This session will cover Google’s successful implementation of Catapult high-level synthesis in the development of G2 VP9.
Monday: 2:00 PM

Reaching for Maximum Power Reduction at RTL using PowerPro[SUP]®[/SUP] & SLEC[SUP]®[/SUP]
We show how PowerPro’s RTL power analysis and patented optimization helps you create low power RTL and verify it with the sequential formal technology of SLEC Pro.
Monday: 11:00 AMor 5:00 PM; Tuesday: 12:00 PMor 4:00 PM; Wednesday: 10:00 AMor 2:00 PM

Why and How to Adopt a HLS and Verification Methodology
This session describes how you can reduce your RTL verification effort by 50%, and the steps needed to make it happen.
Monday: 1:00 PM; Tuesday: 10:00 AM; Wednesday: 3:00 PM

Cutting Through the Noise: A Practical Comparison between C++ and SystemC for HLS (Tutorial)
Have you ever wondered which language is the best choice for your project? This unbiased tutorial will give you the scoop.
Monday: 12:00 PMor Wednesday: 1:00 PM

Leveraging HLS to Achieve Low Power Designs: Catapult LP
Theonly HLS product to focus on power at the architecture level where the biggestimpact can be made. CatapultLP embeds Calypto’s unique PowerProtechnology “under the hood” for maximum power savings.
Tuesday: 2:00 PMor Wednesday: 11:00 AM

About Calypto
Calypto® Design Systems family of products enables ASIC, SOC and FPGA designers to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design. With Calypto’s Catapult High-Level Synthesis products, designers have the option of using SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, PPA optimized RTL. Calypto’s PowerPro product line enables users to analyze both static and dynamic power usage at RTL and either automatically or manually create a power optimized RTL that includes memory and leakage power optimization. The SLEC family of products formally verifies the complete RTL without the need for time consuming simulation and complex testbenches. The end result is dramatic reduction in time to market with up to 60% reduction in power usage.

lang: en_US

May 16, 2014

A Paradigm Shift in the Foundry Supply Chain!

A Paradigm Shift in the Foundry Supply Chain!
by Daniel Nenni on 05-16-2014 at 12:00 pm
Categories: Foundries

Samsung has plenty to talk about this year at DAC. The FD-SOI partnership with STMicroelectronics for example. Also the Samsung GLOBALFOUNDRIES 14nm partnership. Thus the “Paradigm Shift in the Foundry Supply Chain” theme. Samsung is also leading the pack with giveaways!

Samsung Endorses FD-SOI!

Samsung ♥ GLOBALFOUNDRIES

At the booth (#819):

Talk with experts about Samsung’s world-class foundry business and what we can do for you.
Learn why analysts agree that the Samsung-GLOBALFOUNDRIES cooperation on 14nm FinFET is an inflection point for the industry.
See 14nm and 28nm wafers and products that have been manufactured in these industry-leading processes.

Register for the Ecosystem Breakfast:
Samsung with Synopsys and ARM are hosting a breakfast session at DAC.
Monday, June 2[SUP]nd[/SUP]
7:30AM – 8:45AM
Westin Hotel, Metropolitan Ballrooms 1 & 2

Hear from a panel of experts on how early collaboration at 14nm is easing the transition to this advanced process node.

Registration is required to participate: Request your seat at the table now.

Attend conference presentations by Samsung’s Foundry Eco-System partners:

ARM
Cadence
Mentor
Synopsys
GLOBALFOUNDRIES

Learn, Engage, and Have Fun!
There’s lots of ways to learn, engage, and have fun with Samsung at DAC 2014. Don’t miss your chance to win some great giveaways!

Samsung FinFET T-Shirt
Samsung Galazy Fit
GoPro Hero 3
Samsung Chromebook

Samsung Foundry
Advanced process technologies, manufacturing expertise, and first-class services
Learn why Samsung Foundry is a critical resource for competitive fabless and integrated device manufacturer semiconductor companies. Samsung Foundry offers deep expertise in advanced process and design technologies as well as an excellent track record in high-volume manufacturing. We offer a full range of foundry capabilities from design engagements to turnkey projects, with a focus on leading-edge process technologies from 90nm to 32/28nm on 300mm wafers and beyond.

Benefit from Samsung’s optimized foundry solutions
By outsourcing some or all of the design and manufacturing details to Samsung, you can be confident of maintaining the highest possible product quality while saving time and cost. Samsung Foundry provides a full range of solutions including advanced process technology, design services, design intellectual property (IP), and manufacturing facilities. Customer support is available at every step, from the initial engagement to volume manufacturing. And customer IP is stringently protected.

Panel: Strategies for Next Generation Semiconductor IP Management

Panel: Strategies for Next Generation Semiconductor IP Management
by Holly Stump on 05-16-2014 at 7:00 am
Categories: Cadence, Dassault Systemes, IP

I just returned from the “Semiconductor Executive Briefing: Strategies for Next Generation Semiconductor IP Management” panel,held at the Computer History Museum, sponsored by Dassault Systèmes.

(Left to right) Moderator: Warren Savage, President and CEO, IPextreme, with panelists John Tam, Director of Business Development, IP Group, Cadence; Bernard Murphy, Ph.D., CTO, Atrenta; Michael McNamara, CEO, Adapt-IP; Joe Dury, Director, Kalypso.

Warren: What are the key issues around IP today?

Yes,we have unparalled access to IP today, but still….how it is packaged, quality,documentation, and management is still a challenge!
Mac: Back in the day, we knew IP was a Good Thing, but we had no idea! IP is not like LEGOS, click and fit! It is complex, and different developers (digital,analog, software) each have their own concerns. Stitching it all together is a challenge; low power requirements and short product lifecycles complicate it even more.
John: The market is huge; Cadence and Synopsys alone do over $500M. That is a value proof point.
Joe and Bernard agreed: understanding all use cases is important, some of the finger pointing stems from the lack of this.

Metrics: how are we doing, and how can we tell?

Joe: Percent of re-use is one metric, but hard to measure, especially with derivatives.
Mac: Think…there used to be 5 or 6 cell phone chipsets, now only 1 or 2: this is a measure of IP success! Even though it reduces need for EEs and EDA tools…Be careful what you wish for! (Laughter)

IP decision-making: make or buy, and preserving differentiation…

Bernard: It’s a tough decision; external IP is attractive to reduce time, and risk, or if you lack expertise. But you need to ask yourself, what is my differentiation? Hardware? Software? Price? Channel? Some other corporate strength? And if you back away from internal IP development, expect an impact on EE staff…
John: Yes, it is hard to bound the problem; need to know what you are optimizing, and also over sales volumes.
Few companies have the luxury of custom development, fruit not withstanding. How can they differentiate? Red cell phones vs blue?
Mac: Even the (legal) term IP connotes something malleable, almost intangible…Most IP is built around standards, overarching decision factors are around differentiation and time to market.

Fingerpointing When Things Go Very Wrong…

John: Problem is, everyone wants to tweak IP and use it in a different (off-label)way, not as specified, for differentiation.
Bernard: Yes, when you take a standard, like AMBA, and use it in a non-standard way, like extensions, this may create problems.
Joe: It is back to the use case; we are still evolving our concepts of IP.
Mac: “You mean you cannot do 100% test coverage???” Laughing…the question of a naïve user… I am a strong believer in SystemC modeling. Also, as IP moves to a higher and higher level, larger blocks, more of the burden is removed from the user. Large IP blocks, not small, so you don’t need 80-200 IP blocks to stitch together. So consolidation is good in this sense: you only have 7 engineers to choke, not 80!
Joe: Remember the early days? “Real Men Have Fabs.” (Author note: I was there, a woman, designing chips at HP and I had 3 fabs! Grin…) Now, fabless is the model, we all profit. It is analogous.
Mac: To date, verification (in all its forms) has given IP a real boost, flushing out stitching problems, although it is not an easy problem or panacea.
Bernard: Recently at DVCon, still found SoC verification is like the Wild Wild West…lots of methodologies. Often the goal is to compress the hardware verification stage and run real software ASAP.
John: You can never have enough verification…but how much do you need? It comes to what you can afford in terms of time- tools-methods.

Warren: Do 3-D ICs present new IP challenges?

Yes, yield, revenue sharing, licensing implications are more complex. Manufacturing efficiencies will drive this: whether to combine analog and digital, how to treat MEMS.

Warren: What about IP protection?

Bernard: Protection is not only about the IP vendor; it is bidirectional. Think aboutprotection for users from their IP, for example leaks and security issues.
Mac: I organized an IP Track at DAC, please join me to explore this more… IP vendors need to trust their customers, we only have legal protection and one cannot from a practical perspective encrypt (too many downstream tools.)
John: If someone wants to steal IP, they generally can, be careful. And, as IP ages, it becomes more of a commodity.
Mac: Yes, just come up with the next Big Thing in IP!
Joe: Locks keep honest people out.
Bernard: Some technologies for protection can be designed into chips, but they are largely analog and don’t help with soft IP. However, this area is evolving…
John: This issue tends to favor customers buying IP from larger companies, where they have completed the long contract negotiations, the indemnity clauses, recourse.etc.

My key takeaways:

Celebrate the evolution of IP!
Know what your differentiationis!
And remember…bigger IP blocks mean less risk, and fewer necks to choke!

(Author caveat: This is paraphrased, from memory, any errors are All My Fault, not Theirs. Just cut me off,without an IP core!)

Bonus: photo of the Babbage Difference Engine at the fabulous Computer History Museum:

lang: en_US

May 16, 2014

eSilicon @ #51 DAC – Why is a Chip Company at DAC?

eSilicon @ #51 DAC – Why is a Chip Company at DAC?
by Daniel Nenni on 05-16-2014 at 6:00 am
Categories: eSilicon, Semiconductor Services

eSilicon is a fabless chip company that is credited with starting the fabless ASIC movement. You can read more about them in the ASIC chapter of SemiWiki’s new book on the fabless semiconductor industry. But why would a fabless ASIC company come to DAC?

At one level, eSilicon starts where EDA technology ends – taking a taped out chip to volume production, managing yield, quality and delivery logistics across a global supply chain.

But it looks like there’s more to the story. eSilicon introduced an automated quoting capability for multi-project wafers (MPWs) a few months ago. It allows the user to book a slot on an MPW in literally minutes. Paul McLellan wrote about his experience using this application on his iPhone here. It seems like there are more new announcements in the business process automation area from eSilicon. They’re not saying what they are yet, but I think it will be interesting to see what’s being demonstrated at the eSilicon booth (512).

eSilicon has a lineup of suite presentations that explain the various parts of their unique business model. You can check those out and pre-register for an appointment here. You can get the big picture of all eSilicon’s DAC activities here.

eSilicon’s model relies heavily on ecosystem partners and they’ll be interviewing some of them in their booth as well. Note that I’ll be there at 10:30 each day to discuss SemiWiki’s book on the fabless industry and talk about my recent trip to the Mazda Raceway at Laguna Seca where I got the opportunity to get up close and personal with the Flying Lizard Motorsports team as they ran an American LeMans Race. eSilicon is a sponsor for this race team. Note that eSilicon is handing out free copies of the SemiWiki fabless book to those who attend an activity in their booth. I think it’s a way better giveaway than a squeaky toy, but I might be biased.

As a final note – don’t forget to come to the networking reception at DAC on Tuesday at 6PM at the Esplanade Foyer in Moscone Center. The reception is sponsored by SemiWiki, and Paul McLellan and I will be signing copies of our book for the first 300 attendees. The books are provided courtesy of eSilicon of course.

About eSilicon
eSilicon, a leading independent semiconductor design and manufacturing solutions provider, delivers custom ICs and custom IP to OEMs, independent device manufacturers (IDMs), fabless semiconductor companies (FSCs) and wafer foundries through a fast, flexible, lower-risk path to volume production. eSilicon serves a wide variety of markets including the communications, computer, consumer, industrial products and medical segments.

About DAC The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.

lang: en_US

May 15, 2014June 14, 2019

Concept Engineering Showcases Effective SoC Debugging Techniques

Concept Engineering Showcases Effective SoC Debugging Techniques
by Pawan Fangaria on 05-15-2014 at 10:00 pm
Categories: Concept Engineering, EDA

In a complex environment of semiconductor design where an SoC can have several millions of gates and multiple number of IPs at different levels of abstractions from different sources integrated together, it becomes really difficult to understand and debug the overall SoC design. Of course, along with the SoC integration, optimization of the overall design in terms of timing, power and area is of utmost importance. Often designers find it difficult to correlate the design at the RTL, gate, transistor and RC levels; debugging at parasitic level becomes very cumbersome. Imagine looking at the RC network of a net in the sea of a million gate circuit! One needs easy and user friendly tools to quickly isolate, comprehend and analyze particular portions or components of a design in order to inspect and debug them properly.

After attending some of the demos and webinars of Concept Engineering, I can confidently say that they have a class of really effective tools which allow designers to easily comprehend and focus on any portion of interest in their design to debug and optimize the design. The tools can show any component or group of components at the lowest level of transistor along with R and C as well as at the highest level of abstraction for simplicity with a great navigation capability that keeps the things in sync and demarcated as needed by the user. The tools can be used with great level of ease and flexibility at pre-layout as well as at post-layout stages.

It’s pleasing to say that Concept Engineering is showcasing their offerings at DAC 2014. There will be presentations and demos on various tools, solutions, debugging methods & tips throughout the days on June 2-4. Concept Engineering has tools at all levels – StarVision which works at all levels for SoC debugging and IP integration, RTLvision, GateVision and SpiceVision. Also they provide software components for EDA tool developers for them to integrate these capabilities in their environment. NIview is a schematic generation utility which has an option for added GUI that can be based on Qt, Java, Tcl/TK, Perl/TK, MFC and so on as needed by the EDA tool vendor; there is a provision not to have GUI as well, in which case NIview works for schematic generation in batch mode. Also, Concept Engineering provides powerful customization to EDA and design tools through several user ware APIs which they ship with complete documentation that can help users to even develop new APIs at their end as well.

It’s an opportunity for those who are attending DAC to visit Concept Engineering booth #1201 and see their tools & technologies live to get an actual feel of how effectively they can help in SoC design, debug and optimization and IP integration. A deep dive discussion can be arranged on request for specific design needs or tool customizations.

By using Concept Engineering tools, one can view a design at any desired level – RTL, Gate or Spice, instantaneously on-the-fly; there can be mixed-signal and mixed-language level viewing as well along with cross-probing between different views. A fragment of the circuit can be extracted and saved as Spice netlist which can be externally used for partial simulation and re-use in IPs. The parasitic structures can be turned off for easy recognition of CMOS functions in a complex circuit. A logic symbol and schematic can be automatically created from a Spice netlist. The post-layout parasitic networks (DSPF, RSPF or SPEF) can be visualized and analyzed, and Spice netlists can be created for critical path simulation and analysis. The parasitics can be back-annotated at pre-layout stages. During tape-out time when there is a need of fast debugging, selected elements can be dragged and dropped between different views such as schematic, cone, parasitic and source code and cross probed. Cone views can be used very effectively for AMS design debugging because they provide very clear picture of tracing signals passing through different levels of hierarchies. The Clock Tree Analyzer in StarVision provides a graphical representation of all clock domains along with their interconnections. A double click at any interconnection can show the clock domain crossing in that path. The tool has an integrated waveform viewing capability. The connectivity checking (ERC) can be done to identify any floating or incomplete nets or components. The structures such as multi fan-in and fan-out can be checked for heavy load or drive.

The list of techniques and features in these tools is never complete without actually seeing and experiencing them. Whenever I have seen these tools, either in a demo or in a webinar presentation, I found new features and new ways of operations in these tools. They are extremely versatile, flexible and fast which can easily delight their users!

It will be a very positive experience visiting booth #1201, Moscone Center at the 51[SUP]st[/SUP] DAC on June 2 – 4, 2014.

Quantom Dots and Semiconductors?

Quantom Dots and Semiconductors?
by Daniel Nenni on 05-15-2014 at 4:00 pm
Categories: Foundries

Imagine life without science and great minds that made life worth living! It is personalities like Newton, Thomas Alva Edison, Graham Bell, Alexander, Michael Faraday who have made us realized the true potential of science.

Imagine what would have happened if Newton had not discovered gravity? It is due to gravity that earth revolves around sun. Many of you would have enjoyed adventurous sports such as bungee jumping, sky diving or parachuting. Such amazing sports could not be performed if we would have not known the law of gravity.

If it wouldn’t have been Michael Faraday, we could have stayed aloof from electricity. You would have light in your house; however, with an oil lamp. You could take a bath with hot water; however, without a geyser. There would not be heat without fire; likewise, no Ac’s, no refrigerator, no Television, no computers and no movies. Life would have been so boring! It is impossible to even dream of a week without electricity.

Likewise, there are so many scientific discoveries that have completely changed human lives and improved their living. For example, antibiotics, penicillin, X-rays, atomic bombs, etc.

One such amazing discovery is of quantum dots invented by Alexei Ekimov and Louis E. Brus. They are nano particles that show quantum mechanical properties. Their electronic properties fall between those of discrete molecules and bulk semiconductors. Their amazing quantum properties make them widely applicable in numerous industry sectors. As quantum nano particles change their size, i.e., they reduce in their size, they emit colors. This property is harnessed by many manufacturers for anti-counterfeiting activities. At present, they are used in labeling biological materials in vivo and in vitro of animals other than human. Through this, one can easily identify biomolecules.

In 2004, researchers of Carnegie Mellon University, jointly with QDC’s scientists found that quantum dots, which were infused inside the body of animals were emitting distinctive lights for eight months. Hence, a study has been undertaken for using such nano particles in human body in treating and monitoring diseases such as cancer.

Quantum dots would also find application in apple’s retina displays used in Phones, iPod Touch, MacBookPro and iPads. USPTO- US Patent and Trademark Office published applications from apple that proposes to use quantum dots technology in their retina displays.

Quantum dots light emitting property can be used in solar energy by trapping sunlight. “The key accomplishment is the demonstration of large-area luminescent solar concentrators that use a new generation of specially engineered quantum dots,” said lead researcher Victor Klimov of the Center for Advanced Solar Photophysics, at Los Alamos.

“LSCs are especially attractive because, in addition to gains in efficiency, they can enable new, interesting concepts such as photovoltaic windows that can transform house facades into large-area energy generation units,” he said

Quantum dots are proving to be of great use in varied fields and their market is growing fast. Many researches have concurred that quantum dots market would grow exponentially in future. This is due to its exceptional quantum mechanical characteristics. One such research was published by allied market research recently and it analyzed quantum dots market to reach $5.04 Billion by 2020. This would make it a profitable technology for investors.

by Amritesh Suman

lang: en_US

May 15, 2014

PrEDAC Mixer

PrEDAC Mixer
by Paul McLellan on 05-15-2014 at 3:53 pm
Categories: Events

This month’s EDAC mixer is once again at the Savvy Cellar in Mountain View (basicallly in the Caltrain station). It is on May 22nd from 6-8pm.

Get together with your fellow industry peers and insiders at the monthly EDAC Mixer, to the benefit of local charities. You don’t need to donate anything, you just show up and pay for your own drinks. A portion of the proceeds will go to local charities, this month to the Mountain View Educational Foundation (MVEF), a volunteer driven non-profit that provides funding for enrichment programs and educational material to enhance the solid academic curriculum and maintain the high quality of education in the Mountain View Whisman School District. To learn more about MVEF, visit their web site here.

Although I doubt you will get thrown out if you just attend, EDAC would like you to register (it’s free) so they have some idea of numbers. Register here.

So just in case it isn’t clear, here is what you do:
[LIST=1]

Decide to go

Show up at Savvy Cellar, 750 Evelyn at 6pm on 22nd Map

Mingle with your industry colleagues

Pay for any food and drink you consume

Savvy Cellar will donate a percentage to MVEF

Of course the ultimate EDA mixer comes up about 10 days later on the Sunday night of DAC, June 1st, from 5.30-7pm at the Intercontinental Hotel, 888 Howard Street. Just show up.