IC designers use EDA tools to implement their logical and physical design, and these tools require foundry-specific information for:
I’ve been blogging about EDA and Semiconductor companies using social media to create new ways to talk and listen to engineers, so today I looked at Aldec and how they are using social media. Aldec offers EDA products for: FPGA Simulation, functional verification, emulation, and MIL/Aero verification. Their Home page has six icons with links for social media down in the footer section.
Did you go to IEDM 2013 in Washington DC ? You may have attended to the “Advanced CMOS Technology Platform” chaired by TSMC, and listen to the FD-SOI related presentation “High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond”. According with the abstract, this paper is the first time report of “high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET).” If you didn’t go to Washington DC, or not familiar with FD-SOI, having a look at FD-SOI device architecture could help:
(The readers familiar with CMOS device architecture may prefer to skip this paragraph)
The 20nm Gate Length (L[SUB]G[/SUB]) is the drawn gate feature (L[SUB]EFF[/SUB] being the effective Source to Drain distance, between the two arrows on the picture), and the BOX Thickness (TBOX) is the height of the green Buried Oxide zone, giving to FD-SOI the SOI part of the name: Silicon On Insulator, by opposition to Bulk technology, where there is no green zone, but the Silicon substrate. Another precision can be useful: although the paper mentions 20nm Gate Length, it applies to 14nm Node… That’s just the marketing magic! When you draw a 20nm Gate, the effective distance between drain to Source tend to be smaller, due to chemical effect during Drain and Source doping diffusion, and the Semiconductor industry tend to use this effective channel length as the Node denomination. In this case, everybody knows that smaller is better! These few precisions are for those who are not familiar with transistor architecture (or who may have forgotten that they learn at the University…like me).
The paper (from STMicroelectronics, CEA-LETI, IBM, Renesas, SOITEC and GLOBALFOUNDRIES) can be read here.
Now, we have some basic technology knowledge and we can go further in the paper, and learn more about UTBB FDSOI devices featuring 20nm gate length for 14nm Node:
The paper ends with scaling considerations: scaling to 10nm node and below will likely require further LG reduction, and to maintain electrostatic performance, a thinner channel thickness (TSi) will also be needed. However, at very thin TSi (< 3nm), quantum confinement starts to dominate Vt. Fortunately, UTBB devices have another scaling enabler: TBOX. Fig. 18 shows DIBL & SS as a function of TBOX. A DIBL reduction of 20mV is seen when scaling TBOX from 25nm to 10nm:
In summary, FDSOI exhibits competitive effective current, excellent electrostatic behavior, very low Avt and Bias Temperature instability 20% better than bulk. Moreover, UTBB FDSOI is planar and capable of 14nm and beyond, at probably a lower cost than FinFET on bulk technology, the latest being more complicated (more expansive?) to process. But such a smart technology will be effectively more cost effective for chip maker if market adoption is wide enough to first benefit from cost reduction linked with volume production, and also large enough IP ecosystem…
From Eric Esteve from IPNEST
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Wednesday, January 8.
Sensors are big at CES. Big as in many vendors and applications, but small in size. Sensors were prominent features in automobiles, PCs, tablets and mobile phones. But the most exciting is the relatively new area of digital health and fitness. CES has 366 exhibitors in this category, with most of them featuring sensor technology.
In digital fitness, the LG Lifeband Touch won the Tech Radar Best of CES award for best fitness tech (pictured below). The sleek looking wristband flexes to fit your wrist with one end open, thus no pressure points. On its own it senses heart rate, motion, acceleration and altitude. Paired with an iPhone or Android phone it alerts to incoming calls or texts and controls music.
The best looking device was the Wellograph Sapphire Wellness Watch. The rectangular, moderate sized black watch has a sapphire crystal display and a choice of dress or sport band. It tracks pulse and activities and displays data and graphs. In contrast, some companies are still putting out bulky devices which look like you are wearing your phone on your wrist (as shown in the unidentified device below).
Wearable sensor devices which include health and fitness devices are expected to be a $1.8 billion market in 2014. Fitbit is the leader in fitness devices, claiming two-thirds of the market in 2013. This is certain to be a strong growth category in the next several years.
Headed home tonight. I will finish up with a summary of CES and what devices will have the most impact on the semiconductor industry in the next few years.
More Articles by Bill Jewell…..
Taking place annually in Silicon Valley, DesignCon is the premier educational conference and technology exhibition for electronic design engineers in the high speed communications and semiconductor communities.
Created by engineers for engineers, DesignCon is the largest gathering of chip, board and systems designers in the world and is focused on the pervasive nature of signal integrity at all levels of electronic design – chip, package, board and system. Combining technical paper sessions, tutorials, industry panels, product demos and exhibits, DesignCon brings engineers the latest theories, methodologies, techniques, applications and demonstrations on PCB design tools, power and signal integrity, jitter and crosstalk, high-speed serial design, test & measurement tools, parallel & memory interface design, ICs, semiconductor components and more.
DesignCon enables chip, board and systems designers, software developers and silicon manufacturers to grow their design expertise, learn about and see the latest advanced design technologies & tools from top vendors in the industry, and network with fellow engineers and design engineering experts.
The 2014 Technical Conference Program will consist of 14 tracks overing all aspects of electronic design, from chips through boards and systems.
Check out Who Attends DesignCon, and photos and videos from 2013!
Location
Date: Tuesday, January 28, 2014 – Friday, January 31, 2014
Location: Santa Clara, CA
EXPO– January 29 – 30, 2014
ANSYS Booth #513
Panel Sessions
System-Level Power Integrity: Tools Providers and Tool Users Engage
Date: Wednesday, January 29
Time: 3:45pm-5:00pm
Location: Ballroom G
Closing the Loop: What Do We Do When Measurements and Simulations Don’t Match?
Date: Thursday, January 30
Time: 3:45pm-5:00pm
Location: Ballroom H
Technical Papers
A Loewner-Matrix-Based Algorithm for State-Space Fitting of Frequency-Domain Data with Nonuniform Frequency Sampling
Date: Wednesday, January 29
Time: 10:15am-10:55am
Location: Ballroom K
Chip-Package-System ESD Simulation Methodology Using a Chip ESD Compact Model
Date: Thursday, January 30
Time: 2:00pm-2:40pm
Location: Ballroom J
Comprehensive Full-Chip Methodology to Verify Electromigration and Dynamic Voltage Drop on High Performance FPGA Designs in the 20nm Technology
Date: Thursday, January 30
Time: 2:50pm-3:30pm
Location: Ballroom E
About Apache
The proliferation of high-performance mobile devices — such as smartphones and tablet computers — along with the trend toward smaller electronic systems are driving engineers to design and deliver more power-efficient products with extended battery life, while still satisfying increasing performance requirements. Meanwhile, rise in power consumption and electricity costs from the IT infrastructure required to support growing mobile connectivity demands more energy-efficient products. In addition, the explosion in system-to-system wireless communications is amplifying the amount of noise within and between ICs, threatening the system with malfunction or failure.
The Apache suite provides innovative power analysis and optimization solutions that enable engineers to design and deliver products meeting stringent power specification limits, while still reliably and consistently delivering power to the entire system and mitigating failures or performance degradation caused by power-induced noise. Apache’s comprehensive suite of integrated software and methodologies spans a full spectrum of power, noise and reliability solutions, including power reduction, power and signal integrity, thermal management, and EM, ESD and EMI verification, from early in the design phase through final system sign-off.
Apache’s differentiated platforms address the unique challenges associated with various phases of the IC and electronic system design process, including RTL-level power budgeting; IP power delivery integrity validation; SoC integration and power noise sign-off; and IC package/board power and signal integrity, reliability verification and cost optimization. Apache’s accurate and compact models enable RTL-to-silicon, analog-to-digital, and chip–package–system power methodologies that facilitate effective coordination among multiple engineering teams and help to drive the electronic ecosystem.
The combined Apache and ANSYS suite provides even more functionality. It enables R&D teams to solve chip power delivery problems, package/board thermal/electromagnetic extraction, system enclosures and time-domain circuit analysis. Multiphysics capabilities impart the ability to simulate various physical phenomena across chips, packages and systems, including power optimization, signal integrity, electrostatic discharge (ESD), electromagnetic interference/electromagnetic compatibility (EMI/EMC), heat transfer, fluid dynamics and structural mechanics. The multi-user aspect provides the simulation platform and collaboration tools that enable electronics, electrical and mechanical engineers — along with managers and executives from different divisions within the organization — to collaborate in designing increasingly complex products.
More Articles by Daniel Nenni…..
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When people discuss capabilities of leading edge process nodes they tend to focus on digital logic. Microprocessors in particular. But a process requires more than just digital logic and standard cells to be successful. In particular, pretty much every SoC contains a lot of memory so the memory capabilities of a process are important.
Continue reading “FD-SOI Memories”
Tuesday, January 7
Today was the official start of International CES. The crowds were huge – almost every area of the massive Las Vegas Convention Center was crowded.
Now that we have all spent lots of money replacing our old picture tube television sets with big flat panel HDTVs, manufacturers are pushing the next big thing: Ultra High Definition (UHD) TV. Also known as 4K, UHD TV has about 8 million pixels compared to 2 million pixels in HDTV. The detail is incredible. The TV above is Samsung’s 105 inch diagonal, curved UHD TV. Samsung also showed a 110 inch flat UHD TV and an 85 inch bendable UHD TV which can move from flat to curved.
Size matters in UHD TV. Matching Samsung’s 110 inches were Chinese companies CNS and TCL. LG and Toshiba each had 105 inch UHD TVs in a 21 by 9 format, similar to a wide movie screen. Sharp measured in at 90 inches. Companies showing 85 inch UHD TVs included Panasonic, RCA, Sony and Chinese companies Changhong, Haier, Hisense, and Konka.
3D TVs which do not require glasses to view were shown by Haier, Konka, Samsung and Sharp. As with the Izon TV demonstrated on Monday, the glasses free 3D TVs did not have the intensity of 3D TVs which require glasses. However the 3D effect was very acceptable for casual viewing.
Tomorrow is my last day at CES, though the show runs through Friday.
Bill Jewell, www.sc-iq.com
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Gone are the days when analog design had its sweet space on a single chip. However, it’s the main driver in this new electronic world which is geared by Internet-of-Things, wireless, mobile, remote control and so on. How does an electronic device sense a touch by human, motion, temperature, sound etc.? It’s the analog circuitry embedded into the SoC of your electronic device that connects the environment with the device. Quality, accuracy and speed of that sense matters very significantly, otherwise that electronic device will become a nuisance to you. Now you can very well imagine how complex and costly it would be to design a robust high-speed analog IP which can sit (without being disturbed by neighbouring noise) into the complex limited space, high performance, multiple functionality SoC of today. Typically, high performance data converters (between analog and digital), voltage regulators, sensors, clocks etc. are very common in demand.
The design can be better handled by looking at each issue objectively and focusing on important criteria to be met under particular circumstances. So, what are the key criteria to look at?
Sampling Rate – Faster sampling of data in a data converter achieves higher accuracy in rendition of analog signals. According to Nyquist theorem, to generate an accurate reproduction of an analog signal in digital form, the sampling rate should be higher than twice the highest frequency of the signal. However, there is cost involved in faster sampling; it requires higher bandwidth, more power consumption and challenge in synchronizing samples of each bit. Appropriate trade-off must be done depending on application area. The graph below summarizes typical levels of sampling rates and resolution for different applications.
Bit Resolution – This determines the accuracy of representation of analog signal into digital. A higher bit resolution produces analog signal more accurately into digital. A designer in this case can determine bit resolution based on how accurately a signal needs to be represented. For example, an audio device will need higher bit resolution as the voice needs clarity, whereas a thermal sensor in water temperature or air conditioner does not need that high resolution. The table below provides optimal ranges of sampling rate and resolution for various applications.
Noise Ratio – Noise reduces the accuracy of data conversion. Generally it is said that analog components are victims of digital aggressors in the semiconductor design. Care must be taken in placing the analog and digital components appropriately to keep SNR (Signal-to-Noise Ratio) under tolerable limits, even with possible margins by increasing bit resolution or sampling rate. Again, it depends on the type of appliance; an audio or wireless device is extremely sensitive to noise compared to a temperature sensor.
ENOB (Effective Number of Bits) – This reflects the actual performance of data conversion. Due to noise and distortion of signal, it’s not possible to get an ENOB as high as the number of bits in an ADC (analog-to-digital converter). An 11-bit ADC with an ENOB of 10.5 is considered to be well optimized and more effective design than a 12-bit ADC with an ENOB of 10. And hence it’s important that the system requirement are well understood before designing.
Power – This is a major concern for all designs, especially with analog circuits getting into mobile applications. It’s DAC (digital-to-analog converter) that needs more power to drive higher amplitude signal. The challenge is to achieve high amplitude without sacrificing power.
While considering all these challenges and the need for careful evaluation of options, what we did not talk about is the time taken to design such analog IPs. It takes considerable time and that adds into overall design cycle time impacting on time-to-market in a highly competitive semiconductor industry. It’s highly desirable to choose best IPs already optimized with performance and standardized on different criteria and integrate them into SoCs. Cadence offers a broad portfolio of more than 250 silicon-proven analog IPs that include 7-bit 3GSPS dual ADC and DAC, 11-bit 1.5GSPS dual ADC and 12-bit 2GSPS dual DAC which support 28nm designs and provide a conversion rate up to 10X faster compared to competing solutions.
Bob Salem and Kevin Yee from Cadence have very elaborately described these challenges of high-speed analog IPs in their whitepaperposted at Cadence website. It’s an interesting read.
More Articles by Pawan Fangaria…..
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Monday, January 6, 2014.Press conference day at International CES, starting with LG at 8 am and finishing with Sony at 5 pm. Some of the most interesting presentations (I will not overuse the word “cool” today) were:
Izon, LLC introduced a glasses-free 3D TV. They demonstrated on a 24 inch screen playing the latest “Superman” movie from a 3D Blu-ray player (they promised bigger screens at their booth). The display was definitely 3D, but not quite as pronounced as with 3D glasses.
Intel introduced RealSense technology designed make human interaction with technology more natural, intuitive and immersive. The first product is a 3D camera built into PCs and tablets which allows accurate recognition of gestures and facial features. Intel demonstrated games, educational applications, music and video conferencing all controlled by gestures without touching the PC, keyboard or mouse. Intel also introduced the next-generation Dragon Assistant from Nuance which it calls a conversational personal assistant. Will this finally be the voice recognition technology which works well enough for people to begin talking to their PCs (instead of swearing at them)? Stay tuned.
International CES: Day One
The most exciting press conference of the day was Qualcomm’s unveiling of the first electric formula 1 style race car. The Spark-Renault SRT_01E will run in a series of races called the FIA Formula E Championship beginning in September 2014 in Beijing, China. Qualcomm is a major sponsor and is using the Formula E to promote its push into automotive communications applications. The car can accelerate from 0 to 62 mph in 2.9 seconds and has a top speed of about 150 mph. When the car was making laps the most noticeable sound was squealing tires rather than engine noise.
Tomorrow is the official start of International CES.
Bill Jewell, www.sc-iq.com
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I like to call Andes Technology the biggest microprocessor IP company you’ve never heard of. I wrote about themback in October when I sat down with them during the Linley Microprocessor Conference. Part of the reason you have never heard of them is that they are based in Taiwan and most of their business is in Taiwan and China. Mediatek is a big customer. As I said in the above blog, their strategy is partially not to be ARM, to be the processor that you can put where the code is not visible to the end user (inside a WiFi chip, for example). There is no compelling reason to use an ARM there and Andes reckon their cores deliver more performance for both area and power than equivalent ARMs. I’m sure Andes is more cost-effective than an ARM license too.
As I said above:”So what sort of performance do they deliver? With a standard 40LP TSMC library (so not even in 28um) the N1337 delivers 908 MHz and 79 uW/MHz in 0.25mm2, which is 50% higher performance at 1/3 lower power and slightly smaller area than their competition. With a speed optimized library it exceeds the gigahertz barrier (still in 40LP).”
I said in October that Andes had just closed their first US licensee. Now they have several. So you can expect to hear more about them as their US footprint grows. They also closed their first Japanese licensee last summer. I’ll have to find a new name for them once everyone has heard about them, I guess.
The big opportunity is the Internet of Things (IoT) where most of the devices will not be user-programmable so it is a level playing field as to which microprocessor it makes sense to use (unlike in the application processor in a smartphone where the instruction set shows through to all the Apps developers and even someone as established as MIPS doesn’t have traction). On a level playing field, technical specs like power, performance, area, cost all become more important and the instruction set architecture less so.
Andes was founded in 2005 in Hsinchu Science Park (near TSMC). They have over 100 employees located in Taiwan, China, Korea, Japan and US.
They already have around 80 licensees, and over 60 partners for things like compilers, debuggers and other aspects of a processor ecosystem. Over 6000 people use the AndeSight software development tools. Last October they had shipped over 300M processors. Or rather their licensees had shipped over 300M chips containing Andes processors. Their product line has at least 6 cores in, ranging from N7 and N8 which have simple 3 stage pipelines, all the way up to the N12 and N13 that have 8 stage pipelines.
Find out more on the Andes Technology website here.
