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June 28, 2014

This is How We Get One Million Design Starts!

This is How We Get One Million Design Starts!
by Daniel Nenni on 06-28-2014 at 10:00 am
Categories: eSilicon, Semiconductor Services

One of the most interesting demos at #51DAC was the eSilicon GDS II online quote system for TSMC. Probably because eSilicon was one of the most interesting companies exhibiting this year. While writing the book “Fabless: The Transformation of the Semiconductor Industry” we took a close look at the history of fabless semiconductor design. An instrumental part of that history was the ASIC business model where design teams big and small could toss a design spec and a big wad of cash over a wall and get a chip manufactured. eSilicon transformed the ASIC business model by creating a success based partnership with customers that has resulted in hundreds of designs that may have never been.

Also Read: We Need One MILLION Design Starts!

The next transformation you will see is what I call putting the “e” back in eSilicon by internet enabling semiconductor manufacturing. Paul McLellan wrote about it recently: Online MPW Quote Systemand GDS II Online for TSMC. The goal here is to enable design starts and get them into production as quickly and as error free as possible. This is the perfect vehicle for IoT designs, absolutely!

eSilicon’s online quote system for multi-project wafer (MPW) shuttle services delivers instant, executable quotes. The service is accessed through user-friendly web or smartphone interfaces allowing users to evaluate the wafer cost of multiple options in real time at no cost or obligation.

eSilicon’s GDSII portal offers the ability to fully specify the manufacturing process requirements for submission of a GDSII design to TSMC for manufacturing. The required manufacturing process information is specified through a series of easy-to-use menus, along with requirements for packaging, testing and delivery. An executable quotation from eSilicon is provided that includes non-recurring engineering (NRE) pricing and unit pricing for the system-on-chip (SoC) device.

Calling all IoT entrepenuers!

Next month SemiWiki and eSilicon will be doing a webinar on the GDS II portal. I hope to see you there:

GDSII online quoting webinar overview
Choosing all the options necessary to tape out a completed GDSII design for volume manufacturing can be a daunting task. Which process node, what process options, which package and what tester to use are just some of the important questions to answer. And there are many optional services to consider as well. It can take several weeks to months to collect all the information to create a single, complete quotation.

What if you could go to one place and browse all the options available, then generate a complete, executable quotation in minutes? Thanks to eSilicon and TSMC, it is now possible to do just that for a wide variety of TSMC technologies.

What you will see
In this informative, interactive webinar you will witness an actual quote being generated based on real designer input. You will be taken through all the steps required to generate a complete, executable quotation that addresses tapeout costs, optional services and volume production pricing for a new chip design. And we’ll do it all in about 10 minutes using the automated GDSII quoting tool.

We’ll also take you on a journey of discovery, highlighting how various options can be traded off and how those trade-offs impact the final quotation. If you plan to tape out a design for volume manufacturing, you must attend this webinar.

High Level Synthesis update from #51DAC

High Level Synthesis update from #51DAC
by Daniel Payne on 06-27-2014 at 8:00 pm
Categories: EDA

Every since Synopsys dominated the logic synthesis market in the 1980’s we’ve had something called HLS – High Level Synthesis, meaning something higher than what Design Compiler can understand as input. At DACthis year I met with Mark Milligan of Calypto to get an update on what’s new with HLS. I first met Mark when he was at Sunrise Test Systems in the 1990’s and I was at Viewlogic, so I’ve kept in touch with him over the years.

Continue reading “High Level Synthesis update from #51DAC”

June 27, 2014December 27, 2023

I’ll be with you in a second

I’ll be with you in a second
by Don Dingee on 06-27-2014 at 3:00 pm
Categories: Ceva, IP

One aspect of always-on is power conservation, being able to respond to events without having a device constantly in full-power mode. This month, the announcement of the Amazon Fire Phone and details revealed about the Google Android Wear SDK suggest another important dimension: the competitive advantage of rapid, frictionless engagement. Continue reading “I’ll be with you in a second”

June 27, 2014June 14, 2019

Standard Cell, IO and Hard IP Validation update

Standard Cell, IO and Hard IP Validation update
by Daniel Payne on 06-27-2014 at 1:26 pm
Categories: EDA, Fractal Technologies

Every SoC team uses libraries of cells to get their new product to market quicker: Standard Cells, IO Cells and Hard IP blocks. One immediate question that comes to my mind is, “How clean are these cells?” Validating your cell libraries first makes sense, and will ensure that there are fewer surprises as your chip gets closer to tape-out time. At DAC this year I stopped by the booth of Fractal Technologiesand had a conversation with founders Rene Donkers and Johan Peeters to get an update on their EDA business.

Continue reading “Standard Cell, IO and Hard IP Validation update”

June 26, 2014

Electronics growth positive around the world

Electronics growth positive around the world
by Bill Jewell on 06-26-2014 at 6:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

Electronics production growth has turned positive in 2014 for all key geographic regions. The graph below shows three-month-average change versus a year ago for electronics production in local currency through April 2014. Total industrial production is used for Europe (EU countries) and South Korea since electronic production data is not available. The data is from government sources.

China continues to show strong growth in electronics of 10% or higher. Taiwan electronics was in a significant decline throughout 2012 and 2013 but returned to growth of 5% in April 2014. Japan electronics experienced a major decline following the March 2011 earthquake and tsunami. Japan’s electronics growth has been positive since November 2013, ranging from 4% to 8%. U.S. electronics went from positive growth in 2012 to declines of 1% to 7% in each month of 2013. The U.S. turned positive in January 2014, showing growth in the range of 2% to 4% through April. Europe’s industrial production followed the same general trend as U.S. electronics, turning positive in October 2013 and growing about 3% in each month of 2013. South Korea’s industrial production oscillated between positive and negative in 2013, but has been positive since December 2013.

Two key drivers of electronics and semiconductor growth over the last few years have been smartphones and tablets. The growth rate of these products has been slowing over the last several quarters. Tablets have slowed from over 100% year-to-year growth in 2012 to only 4% in 1Q 2014, according to IDC. Smartphone growth has decelerated from close to 50% in 2012 and the first half of 2013 to 24% in 4Q 2013 and 29% in 1Q 2012.

Despite the slower growth in the last few quarter, both tablets and smartphones are expected to show healthy growth for the year 2014. Gartner expects tablet growth of 39% and NPD DisplaySearch projects 26%. IDC lowered its forecast in May to 12% from its March forecast of 19%. IDC expects large display smartphones to take away some of the potential market from tablets. Smartphones are forecast to grow between 24% and 34% in 2014 according to Gartner. IDC is projecting 19%.

What is the next big driver of growth for electronics and semiconductors? One potential answer is the further evolution of computers and mobile phones into a single device to handle most of people’s computing and communication needs. It will probably several years of technological and design innovation before this type of device becomes mainstream.
In the near term several applications will help stimulate electronics and semiconductor growth:

Automotive production has grown steadily over the last four years. Safety, entertainment, navigation and communication applications are driving increasing electronics and semiconductor content in automobiles.
Television sales will see higher growth as more consumers purchase Ultra High Definition (UHD or 4K) TVs. However the high prices of UHD TVs will limit the market to early adopters for a few years.
Wearable devices for tracking fitness and health are becoming popular. The market for these devices is currently small but fast growing.
The “internet of things” (IoT) is getting a great deal of publicity. Basically it refers to connecting a wide range of devices to the internet to be remotely monitored and controlled by a PC, tablet or smart phone. Home security and energy management are two key IoT applications which are seeing acceptance in the market. However some of the proposed IoT applications seem to be a technology in search of a need.

The current outlook for electronics and semiconductors is good based on production statistics. Traditional and emerging devices should be able to sustain growth for at least the next few years. Our May forecast at Semiconductor Intelligence was for semiconductor market growth of 10% in 2014 and 9% in 2015. This forecast certainly looks achievable based on recent trends.

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June 26, 2014June 14, 2019

IP Management Update at DAC

IP Management Update at DAC
by Daniel Payne on 06-26-2014 at 12:42 pm
Categories: EDA, Perforce

To keep track of my business and personal finances I use software from Quicken, but for an SoC with hundreds of IP blocks how do you keep track of everything? The answer is found in the growing field of EDA tools for IP management, and at DACearlier this month I sat down with Neil Handof Methodics to get an update on what the industry trends are.

June 26, 2014June 14, 2019

What’s New with Circuit Simulation for Cadence?

What’s New with Circuit Simulation for Cadence?
by Daniel Payne on 06-26-2014 at 11:53 am
Categories: Cadence, EDA

Every year at DAC I enjoy making the rounds to see what’s new with SPICE circuit simulators, so on June 3rd I met with Xiuya Liand Dan Zhuof Cadence in San Francisco to get an update about their Spectre tool. There’s plenty of competition in the SPICE area from Mentor Graphics (Analog FastSPICE, Eldo, ADiT), Synopsys (HSPICE, CustomSim, FineSim) and others.

Continue reading “What’s New with Circuit Simulation for Cadence?”

June 26, 2014June 14, 2019

Real FPGAs don’t eat fake test vectors

Real FPGAs don’t eat fake test vectors
by Don Dingee on 06-26-2014 at 8:00 am
Categories: Aldec, EDA, FPGA

Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot less certain and a lot more time consuming. Continue reading “Real FPGAs don’t eat fake test vectors”

June 25, 2014April 10, 2025

Single Event Upsets

Single Event Upsets
by admin on 06-25-2014 at 5:04 pm
Categories: EDA

Do you know what a SEE is? It stands for single event upset. We live on a radioactive planet which is also bombarded with cosmic rays, so particles are bombarding our chips. The materials used in packaging also can create particles that cause problems, even the solder. Reliability and aging has been an area that has not been at the forefront of people’s minds while the huge volumes in leading edge processes are mostly driven by the smartphone market. If your phone crashes or reboots it is not the end of the world. But as medical, automotive and aerospace start moving into more advanced nodes we will certainly care. If the ABS system in your car crashes you certainly care a lot. And even in communications, while our cellphones are not a big deal, large enterprise routers crashing upsets their owners, so it is not just an issue for the life-critical systems.

Addressing SEE has to be done at several levels. Materials, the process, the design of cell libraries, the design itself at the SoC level. This is one of the areas that you are going to have to worry more about in the future since, like pretty much anything to do with semiconductors, the problem gets worse with each process node. The transistors are smaller and easier to flip. Memory bits are smaller and easier for a particle to cause a multi-bit upset. Analysis requires tools at the TCAD level and also at the standard design level.

Silvaco has a webinar coming up soon to go over all the issues as to how to analyze your design. The webinar will provide a discussion of the methods used by radiation effects engineers to model the impact of Single Event Effects (SEE) and some of their effects on devices and circuits. The remarkable advances in modern device technology creates specific challenges for high–fidelity radiation effects modeling of these phenomena, while the reduction of feature sizes has made the accurate modeling of SEE and other radiation effects of critical importance. These include the need for modeling Soft Error Rates (SER), Multi Bit Upsets (MBU), chip packaging, and detailed single event effects modeling at the device and circuit level.

The agenda for the webinar is:

Why understanding SEE is important
Basic mechanisms
Destructive single events effects
- Modeling and analysis –TCAD tool flow
- Device techniques for increasing resiliency to SEE
Non-Destructive single event effects
- Modeling and analysis –TCAD and EDA tool flow
- Device and circuit techniques for reducing non–destructive SEE
System methodology examples for a DC-DC boost converter, power diode, and logic block with quenching

The webinar Modeling and Analysis of Single Event Upsetswill be presented by Dr. Christopher Nicklaw, Staff Scientist at Silvaco, who has over thirty-five (35) years experience working on radiation effects in materials. It is Tuesday July 8th from 10am to 11am Pacific Time.

More details are here. Even if you can’t make that time, register anyway and Silvaco will email you a link to the on-demand webinar afterwards.

What Seeking Alpha is Telling us about Intel

What Seeking Alpha is Telling us about Intel
by Daniel Nenni on 06-25-2014 at 9:00 am
Categories: Foundries, Intel Foundry

New Media is a double edged sword for sure. The good news is that you get to read articles by people who actually work in the semiconductor industry. The bad news is that hidden agendas and disinformation abound so let the reader beware, especially if that reader is risking their retirement money!

As I mentioned before, “Understand what people say but also understand why they are saying it” and this definitely applies to Intel articles on Seeking Alpha (SA). One of the biggest SA Intel shills is Mr. Russ Fischer who is listed as a retired 35 year semiconductor professional, investor, and a MENSA member. This makes me wonder where Mr. Fischer spent his 35 years as a semiconductor professional? According to my expert speculation by the way Russ Fischer writes, he was a career Intel employee, absolutely.

The Seeking Alpha site attracts shills like moths to a flame by allowing investors to write about stocks they own and even paying them a penny per click for their efforts. Let’s look at a post Russ made to support my expert speculation that I can spot an Intel employee by the silly comments they make about the fabless semiconductor ecosystem. Let’s start with these three gems from his recent article “Intel: Perception versus Reality”.

[LIST=1]

Intel will conquer the mobile business (only an Intel employee would say that).

TSMC went gate last only after Chairman Morris Chang dictated that TSMC follow Intel(I have heard this omyth from other Intel employees).

The rest of the industry is struggling with 20nm planar processes with no sign of an answer to TriGate for another couple of years, if ever(only Intel employees call FinFETs TriGate).

First and foremost, Intel has a long LONG way to go before they “conquer” mobile and they are losing billions of dollars in the process. Remember, if not for the fabless semiconductor ecosystem “mobile” as we now know it would not have happened so show some respect here. What do you call an IDM that underestimates the power of the fabless semiconductor ecosystem? Fab-lite…

Second, during one of my Taiwan trips in 2010 I asked Dr. Shang-yi Chiang why TSMC decided on Gate-last versus Gate-first. Shang-yi was TSMC’s Executive Vice President and Co-Chief Operating Officer, he joined TSMC in July 1997 as Vice President of Research and Development (R&D) and has successfully delivered many new process technologies including 28nm. Shang-yi told me quite honestly that TSMC had both Gate-first and Gate-last 28nm HKMG architectures under consideration but concluded that, yes, Gate-first is simpler (less manufacturing steps) and would be easier to design to (less restrictive) but it was much harder to yield, especially for complex SoCs. The rest is history. TSMC successfully implemented Gate-last 28nm and achieved a dominant market share as a result.

Third, 20nm is already in production and FinFETs will arrive in 1H 2015 as planned. The irony here is that Russ completely skips over the Intel 14nm yield “struggle” and the resulting delays. Introducing new process technologies have always involved unforeseen challenges. How does a 35 year semiconductor professional MENSA not know this? The important thing is how you face these challenges and how you collaborate with your customers and partners along the way.

It really is a shame that Russ is disgracing his former employer in this fashion for a penny per click. I would not be surprised if Intel asked him to remove his employment record on his SA profile. Semiconductor executives should all know that history has shown if customers have a choice they will not do business with a company that does not play well with others, absolutely.