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Sir Hossein Yassaie, CEO of Imagination Technologies, Keynote!

Sir Hossein Yassaie, CEO of Imagination Technologies, Keynote!
by Daniel Nenni on 03-02-2014 at 12:00 pm

Semiconductor IP is a focus of this year’s Design Automation conference and I’m excited to see a keynote by one of the leaders of this market segment. Even more interesting, Dr. Hossein Yassaie was knighted by the Queen in Her Majesty’s New Year Honours 2013. The award was given in recognition of his services to technology and innovation. Imagination Technologies also collaborated on the IP chapter in our book Fabless: The Transformation of the Semiconductor Industry and Hossein answered the question “What is Next for the Semiconductor Industry?” in Chapter 8. It really is an honor to work with Imagination Technologies and Sir Hossein Yassaie, absolutely.

The Great SoC Challenge ( IP to the Rescue!)

The system-on-chip (SoC) has revolutionized the semiconductor and electronics industries, providing ever-more compact designs that incorporate increasingly large amounts of functionality and performance. This integration, together with process technology scaling, has led to mass availability of affordable, low-power mobile and consumer products.

As the number of discrete IP blocks on a typical SoC continues to escalate, and as the complexity of each of those blocks is also on the rise, SoC developers are challenged to meet not only integration demands but also tight schedules, power and thermal constraints, aggressive cost targets, support for a dizzying array of standards and more. This is compounded by an insatiable consumer appetite for always-on global connectivity, long battery life and of course access to the latest technologies, such as ultra-high definition video and photorealistic graphics.

Silicon IP providers have stepped in to ensure continued innovation by providing high-performance, low-power technologies that help SoC companies meet their design requirements in this ever-more complex environment. IP will play an increasingly vital role going forward. By offering a comprehensive IP portfolio and market driven platforms across CPU, graphics, video and vision technologies, IP providers will help companies overcome their design challenges and address a growing number of exciting new applications and market opportunities.

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems and for electronic design automation (EDA) and silicon solutions. Since 1964, a diverse worldwide community of many thousands of professionals has attended DAC. They include system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, and methodologies and technologies.

A highlight of DAC is its exhibition and suite area featuring leading and emerging EDA, silicon, intellectual property (IP) automotive, security and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design Automation (ACM SIGDA).

More Articles by Daniel Nenni…..

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Effect of Inductance on Interconnect

Effect of Inductance on Interconnect
by Daniel Nenni on 03-02-2014 at 11:00 am

In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for clock lines, or any other place there is critical interconnect in high speed analog or RF circuits.Several things have changed that are now compelling designers to look more closely at interconnect parasitics. Up until now inductance was something that could be ignored. But with higher frequencies, even simple wires inside circuits are starting to look like transmission lines. The rule of thumb has been that when the length of the signal path was long enough to become some percentage of a wavelength that the line itself starts to become a concern for signal integrity. The question is what is the critical length in designs?

Lets first look at operating frequency to see at what scales we will have to more closely examine interconnect effects. At 900MHz the wavelength in a metal conductor is ~192mm, a very large dimension relative to IC circuit interconnect. One percent of that is a whopping 1923 microns. But if we move up to 12GHz we see that the wavelength is
14.2mm, and one percent of that is 144 microns. Now we see we might actually encounter circuit elements that are around this size.

What is needed are some objective data on what happens when wires are modeled with and without inductance as circuit signal paths exceed two orders of magnitude less than the wavelength.

We have run some test cases using a straight metal line to determine the magnitude of the discrepancy between predicted and actual signal performance that comes from ignoring inductance where the wires are more than one percent of the wavelength. Phase error specs for signal lines are often capped at 1 degree of phase error. The spec for signal amplitude accuracy usually needs to be better than +/-5%.

Here is what we see from simulation using PeakView to generate electromagnetic models for a 200um line running at 25GHz. This line length is 3% of a wavelength.

This is the added impact seen by considering inductance in our analysis. It is evident that even when the line length is just 3% of a wavelength significant effects can show up.

It is recommended that design flows for high speed analog and RF circuits include an accurate EM based method for including inductive effects in circuit performance analysis. PeakView offers this capability in its HFD option. HFD allows for inductive effects to be easily included in circuit simulation runs. No manual work is required and it is fully integrated with the LVS and LPE flow. PeakView is a high performance fullwave electromagnetic solver providing accurate resistance, capacitance and inductance information that is usable by designers for transient circuit simulation.

About Lorentz Solution, Inc.
Lorentz Solution, Inc. is the industry leader in supplying electromagnetic (EM) design capabilities to the RF, high-speed analog and high-speed digital design community. PeakView™ EM Design Platform, Lorentz’s flagship product, is widely adopted by top IDM, fabless companies and semiconductor foundries. Based in Santa Clara, California, USA with initial funding from US-based VC firms, Lorentz Solution is continuing its multi-year profitable growth.

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Gobi, the Jewel in Qualcomm’s Crown

Gobi, the Jewel in Qualcomm’s Crown
by Paul McLellan on 03-01-2014 at 5:19 pm

Back in the 1990s in the middle of the 2G GSM era, cell-phone manufacturers would display a “triangle of difficulty” with a large base labeled radio, a middle smaller part labeled baseband and a little triangle on top labelled software. The idea was that the radio was incredibly difficult, then the baseband chip and there wasn’t a lot of work on software since there wasn’t that much in a phone of that era. But they would point out that that was then and now the triangle was inverted. Radio was basically a solved problem, baseband was still a challenge but more and more manpower was being consumed by software. It was true. The radios didn’t change much, a new baseband at each process node with different speed/power tradeoffs, but more and more of the differentiation was moving into software. Plus nobody was yet trying to integrate the radio onto the pure-CMOS baseband chip, that challenge lay in the future.


But that was then. Then came 3G and, not that long after, LTE. Radio went back to being an unsolved problem. Building the radio interface, also known as the modem, was right on the limit of what was possible given the silicon performance. To make things worse, the power budget could not go up much even though the computational load was much higher.

Qualcomm had distinguished themselves in the 1990s by commercializing CDMA but their claim to success in that era was not that they were better at designing modems than anyone else. Then suddenly they were ahead by a long way. The Gobi series of modems started by supporting both CDMA and GSM on the same modem, along with GPRS and EDGE (data standards).


Several teams tried to design LTE modems. When ST-Ericsson was shut down, its LTE modem was one of the few things of value and was kept by Ericsson in the divorce. Intel needed an LTE modem and it had one in design with the Infineon acquisition, and then went and got another one through an acquisition of Fujitsu’s LTE team. As an indication of how difficult it is, Intel has not managed to get its LTE modem onto its own process and has to manufacture it via TSMC. Almost all the other LTE modems were late.

The current version of Qualcomm’s Gobi handles LTE with speeds up to 300 Mb/s and backward compatibility to 3G, EV-DO (data), and GPS.

Initially LTE modems were standalone chips. For some applications that is still desirable. Apple designs its own application processors (A4…A7) but it uses a Qualcomm Gobi modem as a separate chip. One theory is that designing an LTE modem is too hard even for Apple (although with their cash they could buy a modem design team or a whole company). The other is that getting approved by all the different operators is something they would rather leave to Qualcomm who have to do it anyway and if they integrated the modem on the Ax chips they would have to go through that certification process separately. With a separate chip, modem certification goes on in parallel with application processor design.

Very early on, Qualcomm had the Gobi modem integrated onto its own Snapdragon processors as a single chip. They were way out in front doing this. nVidia is just getting there now. Broadcom (after acquiring Renasas LTE line) now has an integrated product. Intel still isn’t there and won’t be any time soon. Mediatek still has separate chips but is apparently sampling an integrated product.

The result: Qualcomm is far and away the market leader in baseband application processor chips (at least the merchant market, both Apple and Samsung create their own). In LTE-based baseband chips, analysts give it 95% market share. After all the other guys didn’t have anything when it was needed and only now (literally, there are daily announcements from MWC in Barcelona this week) are announcing handsets incorporating their products.

Presumably the handset manufacturers will want to make at least one or two of these competitors viable, for security of supply and price negotiation. So Qualcomm’s business will probably grow but the percentage share will probably shrink. But Qualcomm already have Snapdragon sampling in TSMC’s 20nm process, out ahead of everyone else again. Correction: it looks like just the Gobi modem is in 20nm, not yet Snapdragon (although the modem is far harder to port than a pure digital SoC so it shouldn’t be far behind).

Even the competitors are not bullish. As a senior marketing manager of nVidia said:“We are never going to be at the level of Qualcomm. We have to take baby steps.”



Recently Qualcomm announced Octocore versions of Snapdragon with 64 bit processors and a specialized chip for Automotive built in 20nm.

In the 1990s, Qualcomm’s secret weapon was that they understood CDMA better than anyone else, having invented it. In the last 7 or 8 years it has been their Gobi modem technology, first in 3G but especially for LTE along with the fact that they have had a single chip integrated application processor and modem. They have out-executed the rest of the industry.

As always, mobile is a fascinating industry to watch.


More articles by Paul McLellan…


GlobalFoundries Fab 8: Jobs

GlobalFoundries Fab 8: Jobs
by Paul McLellan on 02-28-2014 at 4:26 pm

GlobalFoundries was created by spinning out the manufacturing side of AMD’s semiconductor business. Initially the company was jointly owned by AMD and by the Advanced Technology Investment Company (ATIC) which is an investment arm of the Emirate of Abu Dhabi. A couple of years ago ATIC bought out the remaining share from AMD, so GlobalFoundries just has a single shareholder, ATIC today.

In upstate New York AMD planned a new fab for 20nm. GlobalFoundries renamed it Fab 8 and continued to execute on the plans to build it, starting in July 2009, just 3 months after GlobalFoundries was created. It has a capacity of 60,000 300mm wafers per month which is 135,000 200mm equivalents, which is often the way fab capacity is measured. It is in Malta NY (which is in Saratoga County so sometimes you might hear about it being in Saratoga NY). It is a big investment, initially $6B although recently ATIC committed more money to GlobalFoundries and some will be for Fab 8. It is planned to run 28nm and below there.


There is also a new $2 billion Technology Development Center that GlobalFoundries is building next to its current chip factory, known as Fab 8.1. The College of Nanoscale Engineering and the eventual manufacturing for the G450C consortium working on making 450mm wafers practical is a half-hour drive away in Albany NY.

Supposedly (per Forbes magazine) GlobalFoundries and Samsung have been syncing GlobalFoundries Fab 8 with Samsung’s S2 in Austin. Rumors are that Samsung will offload some Apple production to GlobalFoundries. Perhaps Apple is just keeping its options completely open.

Since breaking ground on Fab 8 in 2009 GlobalFoundries has created approximately 2,000 new direct jobs and that number is expected to grow by approximately another 1,000 employees for a total of about 3,000 new jobs by the end of 2014. Here’s a summary of some of the current job openings in New York:

  • EQUIPMENT ENGINEERS: Etch, Litho, Diffusion, Thin Films, Cleans, CMP/Plating, Metrology
  • PROCESS ENGINEERS: Etch, Litho, Diffusion, Thin Films, Cleans, CMP/Plating, Metrology
  • TECHNICIANS: All Levels supporting all modules listed above
  • FACILITIES ENGINEERS AND TECHNICIANS: Chemical/Slurry, Ultra Pure Water/Waste Water, Gas
  • MANUFACTURING OPERATIONS: All areas
  • YIELD & DEFECT ENGINEERS: Failure Analysis (Physical, Chemical, Electrical), Defect Inspection Process and Equipment Engineers, Test Engineers (Integration, Parametric, Quality, Applications)
  • PROGRAM MANAGEMENT
  • CUSTOMER ENGINEERING
  • PDK DEVELOPMENT ENGINEERING

So it seems that if you know how to do pretty much anything inside a modern fab then GlobalFoundries has openings.

There is also a GlobalFoundries job fair next week in Texas for the sole purpose of meeting the best semiconductor talent in the Dallas area. On March 4th there will an invitation only Meet the Team event with an executive speaker who will talk about GlobalFoundries’s plans, the location, the new Technology Development Center and so on. This will give the candidates an opportunity to learn more about the company and meet members of the team. On March 5th and 6th they will hold 1:1 interviews for current openings and predicted future positions. These interviews will also be by invitation only. To apply for an invitation to the job fair click here.

The GlobalFoundries job opening page for the US is here(there are also openings in Asiaand Europe).


More articles by Paul McLellan…


Locked on FPGA design brand recognition

Locked on FPGA design brand recognition
by Don Dingee on 02-28-2014 at 3:30 pm

Back in the days where computing was dominated by a few big (and now mostly dearly departed) names, there was a saying: “Nobody ever got fired for buying IBM.” The relative safety of immediate brand recognition, especially among non-technical upper management, dissuaded many users from recommending or even seeking out other options. Non-justification was just easier.

Technology changed, but people haven’t. Many users still make tech buying decisions based on risk-aversion instead of innovation, preferring to stand in line with the crowd even if we’re not quite sure what it is we are waiting for – but it must be good, because everyone important is here. Apple uses this effect to cause people to repeatedly stand in queues for iPhone and iPad launches, long after the initial burst of disruption wore off.

Photo credit: Adrees Latif / REUTERS

More often than not, I find myself subscribing to the Yogi Berra counterpoint: “Nobody goes there anymore, it’s too crowded.” But for most tech users, there is safety in numbers, especially considering options with low numbers tend to disappear quickly. The risk of the unknown can trump exploration of new technology.

Fortunately, in the age of the startup, venture capital, fabless technology, and social media, the mainstream choices usually are pretty good because they have to be for long-term survival. No company can afford to sit on their laurels for more than a brief moment of celebration; there are way too many competitors pounding at the gate. Good tech products have to evolve to stay competitive, and bad tech products or lousy customer support get clobbered on social media faster than Ronda Rousey challengers.

I was resolving final comments on a white paper for a client this week. In it, I made a generic statement there are many tools out there for FPGA synthesis, mentioning SystemC as one of the approaches designers may want to consider. The comment, which I greatly appreciate, came back:

[Xilinx] Vivado HLS is much more prevalent than SystemC.

That got me thinking. No disparaging Xilinx or Vivado Design Suite technology or popularity here; it’s a great tool. The latest versions of Vivado do have high level synthesis capability, and most embedded engineers are far more familiar with C/C++ algorithms and probably would like to use them directly if possible in FPGA designs.

We can debate the pros and cons of FPGA synthesis strategies, and the validity of the comment, another time. What I found interesting was the motivation behind it, and the immediate leap from methodology options to a tool choice, a very safe one at that. Nobody ever got fired for using Xilinx tools with Xilinx parts, right?

If your world begins and ends with Xilinx FPGAs, that’s OK. But, like the mainframe biz of yore, things could change. You could change jobs. You could get a new requirement, something exotic like rad hard or some funky interface. Your customer could tell you what FPGA you’re going to use, because changing their IP for another part is risk they don’t want. Or a myriad of other reasons to look at your options. (BTW, this all applies if you use some other FPGA architecture; you may have to switch to Xilinx at some point.)

You’ll walk in the office of some PHB where you work, and the conversation will go like this:
You: “Hey boss, I need you to sign this purchase order for Aldec Active-HDL.”

PHB: “Who’s Aldec? I thought we used Xilinx.”

You: “They’ve been in business 30 years selling vendor independent EDA tools, and they’ve got some great solutions for FPGAs we should try. I downloaded their evaluation and …”

PHB: “Yeah. But, is it safe?” (Google it.)


At this point, you could run before the anesthesia takes effect, or you could try explaining in terms the PHB would likely not understand, or you could whip out the recent SemiWiki article on Active-HDL from Luke Miller. You see, Luke was introduced to Aldec on a concall I was on in January 2014, downloaded the evaluation – and switched tools on the spot. His likelihood to see multiple FPGA architectures in his role as “The FPGA Expert” consulting to the industry at-large is very high, and he’s seen tools from many vendors.

I’m not suggesting to scream and run away from Xilinx or any other FPGA tools here. I think Xilinx Zynq is huge for the industry. This is just an example of how people lock on brand recognition.

All I’m suggesting is don’t ever let the PHB and his cronies dissuade you from looking at options like Aldec because they aren’t the names they are used to hearing. You might miss innovation that could make the difference in your next design – and then you and the PHB could both get fired. Don’t be that guy or gal.

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Synopsys’s Next Generation Emulator, ZeBu Server-3

Synopsys’s Next Generation Emulator, ZeBu Server-3
by Paul McLellan on 02-28-2014 at 12:17 pm

Since Synopsys acquired Eve over a year ago, they haven’t announced anything new in the ZeBu product line. Emulators are not like software where you expect incremental releases a couple of times per year, each new “release” is a complete re-design using new hardware fabric in a new process technology. Earlier this week Synopsys announced Zebu Server-3, currently the industry’s fastest emulation system (to be fair, whenever a new emulation product is announced it tends to be the fastest for a time…). They also announced a collaboration with Imagination Technologies to enable faster emulation, currently for Imagination’s PowerVR GPUs and in the future for the MIPS processor line too. Imagination are achieving clock speeds of 3.5MHz emulating their GPUs, compared to historic speeds closer to 1MHz with earlier generations of emulators.

ZeBu servers come in a 20″ cube weighing 155lbs and consuming less than 2.5KW. Inside there are Zebu modules (boards) that each handle 60 million gates. A cube can hold 5 of them and so each one can handle 300M gates. Ten of the cubes can be chained together to give a total maximum capacity of 3B gates. The underlying fabric is Xilinx Virtex-7 arrays, the ones that you have probably heard a lot about if only because they are 2.5D interposer-based designs using through silicon vias (TSVs). They are built in TSMC’s 28nm process.

Every emulation announcement rides on Moore’s law and is faster and with higher capacity than the previous generation. Perhaps more interestingly is the verification technology that Synopsys has intetgrated in with the Eve emulation technology they acquired. Here are some of the technologies that surround Zebu Server-3:

  • transactor libraries
  • memory models
  • DesignWare
  • Simulator-like debug with Verdi[SUP]3[/SUP]
  • Waveform viewing
  • Autotrace to disk
  • Coverage measurement
  • In-circuit I/O
  • Virtual adaptors
  • Automated software flow: partition, P&R, synthesis, memory compilers


One major challenge they have addressed is hardware/software co-verification. One problem in this environment is that the time between a bug in software and something detecting it might be a couple of billion clock cycles. A problem during a Linux boot might not show up until an attempt is made to access a video encoder, for example. Traditionally, emulators would capture a moving window of a couple of million vectors but that is not enough. Instead, ZeBu captures the state periodically and captures all inputs. To go to any clock cycle requires reloading that state and rerunning the inputs to get to the clock cycle of interest. This way billions of cycles can be stored very efficiently (interestingly, this is almost the same approach as we implemented at Virtutech to enable us to run code backwards. A reverse single-step meant reloading state and running all instructions except one).

They can also do hybrid emulation, with part of the design running on a virtual platform and part in the emulator. Where models exist (especially CPU models) they will typically run faster on the platform. A CPU “model” is a bit of a misnomer, since it is really a JIT compiler that can run the emulated code at close to (sometimes above) the actual performance of the target microprocessor. But emulation seems to be the killer-app for virtual platforms, avoiding the problem of needing to create a lot of models and keep them accurate as the RTL is developed. Just run the actual RTL on the emulator.

I assume you will be able to see a ZeBu Server-3 on the Synopsys booth at DVCon next week. They are at booth 201.

The Zebu press release is here.


More articles by Paul McLellan…


Friday Miscellany: EDAC Mixer, DVCon, DVCon Europe

Friday Miscellany: EDAC Mixer, DVCon, DVCon Europe
by Paul McLellan on 02-28-2014 at 8:31 am

Yesterday evening was EDAC’s first mixer. I assume the first of a regular event. It was held in Mountain View in the old train station which is now the Savvy Cellar wine bar. I had a nice glass of rosé from Provence that reminded me of the years that I lived in the south of France. Some of the money we spent went to charity, to the Mountain View Educational Foundation (MVEF).

To my surprise I discovered another “microprocessor company you’ve never heard of”, this one, like my wine, from the south of France. Montpelier to be exact. It is called Cortus and has been around for nearly 6 years and shipped over half a billion devices (well, its licensees have, it is an IP company). More surprising still was that it is represented in the US by Scott Hills who used to work at VLSI twenty years ago.

There were lots of Jasper people at the event. Not surprising since their offices are just a few blocks down in the middle of Castro Street. Kathryn hadn’t shown by the time I had to leave but everyone assured me she was coming.

I guess there were 30 or 40 people there in total. The wine bar is quite small so it is a good job that hundreds of people didn’t show up. Anyway an enjoyable evening.

One major topic of conversation is that next week is DVCon, the big conference totally focused on verification. With verification being such a bit part of design these days it is starting to feel that verification is all there is. It is in the DoubleTree in San Jose as usual.

The conference kicks off with the annual Accellera Day on Monday, March 3. The day-long event will run from 8:30am-4:30pm and will feature in-depth tutorials from experts and users on the latest in electronic design and intellectual property standards. There will also be a sponsored luncheon from 12:15-1:45 that will discuss The Future of Mixed Signal Verification: From Manual Simulations to Full Regression?

The keynote is at 2pm on Tuesday, given by Lip-Bu Tan, CEO of Cadence: An Executive View of Trends and Technologies in Electronics. Drink every time you hear “internet of things.”

The DVCon Expo will be open for three afternoons: Monday, March 3 from 5:00-7:00pm, including a sponsored booth crawl; Tuesday, March 4 and Wednesday, March 5 from 2:30-6:30pm. There are a record number of 41 exhibitors participating in the Expo.

In addition to the 12 tutorials, 14 papers and record of 30 posters being presented, there will be 2 panels during the conference. The first panel, Is Software the Missing Piece in Verification? will be moderated by Ed Sperling, and will be held on Wednesday, March 5 beginning at 8:30am in the Oak Ballroom. The second panel, traditionally known as the Industry Leaders Panel, is titled, Did We Create the Verification Gap? and will be moderated by John Blyler. It will begin at 1:30pm on Wednesday in the Oak Ballroom.

And DVCon is going international. Not only is there DVCon in the US next week, there is a new (presumably first annual) DVCon Europe. it will be held in Munich on October 14-15th. The detailed program won’t be available until July 1st, although the 50,000 foot (or should that be metres in Europe) is that day 1 is tutorials and exhibition and day 2 is technical sessions and the exhibition. Call for papers is out already and open until April 8th. And potential exhibitors can sign up.


More articles by Paul McLellan…


Mixed-Signal SoC Debugging & IP Integration Made Easy

Mixed-Signal SoC Debugging & IP Integration Made Easy
by Pawan Fangaria on 02-28-2014 at 7:30 am

A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly. Considering today’s large SoC designs with multiple IPs, it’s imperative that effective debugging tools with easy and quick visualization, navigation, annotations etc. are a must for designers to make right decisions during the course of design. The designers should be able to easily analyze different parts of the design which can be in different languages such as Spice, Verilog, VHDL, SystemVerilog etc. and can have different levels of voltages and signals.

Last week I attended a webinaron Mixed Signal SoC Verification hosted by EDA Directwhere they showcased StarVision[SUP]TM[/SUP]tool from Concept Engineeringthat does the job quite elegantly at all levels. Lokesh Akkipeddi of EDA Direct presented interesting capabilities of StarVision[SUP]TM[/SUP] followed by a demonstration. While the video shoot of the webinar can be available in future, I wanted to highlight some of the key capabilities of the tool which appeared very apt for quick and easy debugging of typical scenarios in SoCs, which can otherwise be very cumbersome and time consuming. That enables designers to easily and effectively integrate IPs into an SoC.

The overall semiconductor design can be visualized with its parts at Spice, Gate or RTL level either in schematic or in its source code format. Post layout and netlist interfaces can be easily represented and visualized. Hence any third party IP in available format can be quickly imported into the flexible GUI and then analysed, debugged and integrated into the SoC.

A quick and easy way is to use cone view for debugging AMS designs; cone views provide very clear picture for tracing signals passing through different levels of hierarchy in the design.

In large SoCs, there can be several clocks driving various parts of the overall semiconductor design. It’s very important to check if there is any clock domain crossing issue. The Clock Tree Analyzer in StarVision[SUP]TM[/SUP] presents all clock domains and their interconnections in an easy to view graphical form. By double clicking on any interconnection, designers can view the clock domain crossing in that path.

Timing closure is a major concern in SoC verification; violations need to be appropriately understood before fixing them. StarVision[SUP]TM[/SUP]automatically annotates schematics with timing information from PrimeTime report. Timing violations on any circuit element can be easily spotted and appropriate action taken.


There is an integrated waveform viewer which can show the complete waveform from VCD data. StarVision[SUP]TM[/SUP]also annotates source and cone views with the VCD data as appropriate. The toggling nets at various components in the cone view and the source view are clearly visualized for the designers to get a feel of consistency in functioning of the circuit as desired.

Although there is provision to visualize the circuit with complete parasitics, to recognize a particular circuit with ease, there is provision to hide parasitics and simply view the circuit with only logic components. For recognizing circuits, there are other features as well such as merging of parallel transistors. Again there is provision to view logic symbols as per desired library such as Cadence. In this example circuit, it’s very difficult to recognize the inverter in the RC view which has all resistances and capacitances cluttered along with the transistor symbols. However that is clearly recognized in non-RC view.

It’s very tedious work to do post layout parasitic level analysis. However it’s very important to be able to fix issues at this stage without disturbing the whole circuit and initiating a whole iteration of the costly design flow. StarVision[SUP]TM[/SUP]provides an easy-to-use drag & drop of nets which can be viewed in full parasitic format with the data read from SPEF or DSPF file. Multiple nets can be viewed at a time in different colors.

Overall it was a great session with live interaction with Lokesh. Look for more information about this product or webinar at EDA Direct here. A self-running demo of StarVision[SUP]TM[/SUP]is also available at Concept Engineering website here.

More Articles by Pawan Fangaria…..

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SmartConnect goes five by five for the IoT

SmartConnect goes five by five for the IoT
by Don Dingee on 02-27-2014 at 8:45 pm

OK, enough with octa-core mobile monstrosities for now. Let’s shift gears to Embedded World 2014 and the lower end of the spectrum, one that will make up the vast majority of devices on the Internet of Things: tiny, low power microcontrollers with integrated wireless connectivity.

There still seems to be some stigma about putting RF into designs, and some of it is justified. One of our readers commented this week that Apple “does not have the know-how” in reference to integrated baseband LTE. On the contrary, I’d say: Apple can buy any IP or talent they want. Their reluctance stems more from the realities of supply chains and multiple carrier qualifications facing different requirements in worldwide markets, not a technology issue per se.

RF designs still need proper care and feeding and regulatory clearance. We continue to see strides in RF integration – with attention now turning to the microcontroller level. This is especially true for protocols that can be dropped on chip via an IEEE 802.15.4 radio, such as 6LoWPAN and ZigBee. The challenge for companies is to deliver wireless in a small package, using minimal power, at a low cost – and then, enable solutions with software.

I think most software types recognize the advantages of 32-bit cores for the IoT. This is especially true moving toward the future with needs like IPv6 addressing, advanced protocol stacks like ZigBee Smart Energy Profile 2, and stronger encryption for security which is becoming more important with every passing day.

With all that to consider, one of the bigger “smaller” announcements at Embedded World was Atmel SmartConnect. The SAM R21 is an ARM Cortex-M0+ core with an integrated 802.15.4 radio; the most aggressive version comes in a 32 pin 5x5mm package, and in industrial temperature grades up to 125C, with the family starting at $2.75 in 10K quantities.

Integrating a radio on an MCU isn’t exactly news – Atmel has been at this for a decade, others have followed suit – but IoT-ready software at these package sizes, power consumption, and price points is. The software buzz at #EW14 came from ThingSquare, running their open source Contiki OS and 6LoWPAN on the SAM R21 Xplained PRO board. (For those unfamiliar, the Contiki community refers to itself as “the open source OS for the IoT.”)

Don’t be deceived by the board size, set up for convenience of finger-sized buttons and inexpensive connectors for development use. That’s the SAM R21 in the center (in the slightly larger 48 pin 7x7mm variant), one chip that gets designers on the IoT quickly if the target is ZigBee or 6LoWPAN.

That was the easier part. What about the Wi-Fi version? Press releases sometimes require careful reading between the lines plus an understanding of competitive space. Getting Wi-Fi down into this MCU range of small, low power, and inexpensive is a bit more challenging right now – most MCU implementations today rely on a 4-wire SPI connection to a separate Wi-Fi part. Atmel was somewhat vague referring to a “single package” SmartConnect Wi-Fi module, and their wording suggests a similar two-part approach.

I’m presuming Atmel knows what they are up against for Wi-Fi modules popular with IoT types, and is bringing a solution that saves space and BOM cost in comparison – we’ll see as they release details. We do know they are continuing to work hard on the Studio 6 IDE, supporting the SmartConnect family in wireless “composer” capability with C/C++ modules. As I’ve said before, silicon is only the enabler – code is the product.

The spellbinding story of our time is how embedded is now swinging heavily toward the IoT, an unmistakable takeaway from Embedded World. Microcontrollers are changing to address intelligence plus connectivity to be part of this new tale.

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Celebrating 50 Billion ARM Powered Chips!

Celebrating 50 Billion ARM Powered Chips!
by Daniel Nenni on 02-27-2014 at 12:00 pm

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In case you have not seen it yet there is a website named 50BillionChips where you can follow the journey of ARM. This goes quite well with the brief history of ARM we wrote last year in preparation for our bookFabless: The Transformation of the Semiconductor Industry. ARM was a big part of that transformation of course.
Continue reading “Celebrating 50 Billion ARM Powered Chips!”