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November 27, 2014

Rock for CASA, December 6th

Rock for CASA, December 6th
by Paul McLellan on 11-27-2014 at 7:00 am
Categories: Events

It is the holiday season so time to get together with your friends and colleagues in EDA, IP and semiconductor at the third annual event raising money for Court Appointed Special Advocates (CASA) (www.casaofsantacruz.org). This is the third event that Heart of Technology has worked with CASA. CASA has local organizations and in this case we are working with their Santa Cruz organization.

The event is on Saturday December 6th from noon to 5pm at Doc Auto in Santa Cruz, which is at 908 Ocean Street. There will be a big tent so that the event can take place rain or shine. As always there will be live music, food, drink, silent auctions and raffle drawings. It promises to be a fun afternoon. Cost is just $10 or donate a $10 gift card.

Of and if you are wondering why the event is taking place at an auto shop, there is an EDA connection. Doc Auto is owned by Ken Potts family. He worked for me at Compass way back when and currently is at Cadence.

Santa Cruz is economically very different from San Jose. The statewide median household income is $59,540. The median income for a household in San Jose was $77,000, which is well above median for a Santa Cruz household in the city was $50,605. Many households are having a difficult making it and families are suffering. CASA is about taking care of families going through difficult times. This is especially true around the holidays.

A little more about CASA: Children with a CASA Advocate are…

More stable while in foster care;
Receive more of the physical and emotional resources they need to heal;
Better able to succeed in school;
Less likely to return to the system.
Children with a CASA Advocate are more likely to grow into healthy adults who can break the cycle of abuse and neglect.

This holidays the focus for the event will be teenagers. Often the teenagers are left out. CASA will use proceeds to purchase gift cards for example. These gift cards are very useful by teenagers who want to fit in.

I will be there, hope to see you too.

Court Appointed Special Advocates of Santa Cruz County
As many as 600 local children each year live in the Santa Cruz County dependency system because of parental abuse or neglect. Each day they face uncertainty and trauma, their lives a sea of ever-changing professionals who –although well-meaning- are nonetheless strangers; police, social workers, foster parents, therapists, judges, lawyers and many others. This is where CASA steps in. For more than 200 of these children each year, one person is consistently there; a caring person whose focus is solely on them, a person whose reassuring presence does not change; the child’s volunteer CASA Advocate. Read more.

‘Tis the season for 4K UHD and HEVC

‘Tis the season for 4K UHD and HEVC
by Don Dingee on 11-26-2014 at 4:00 pm
Categories: Foundries, STMicroelectronics

4K UHD TVs were all dressed up at CES 2014 with no content to show. The good news for the 2014 holiday season is the industry has converged on one set of standards for display, interfacing, and encoding, so consumers should not be left marooned in an instant replay of the 3DTV hype-crash cycle. It may be a bit longer before everyone can see 4K, but there has been significant progress. Continue reading “‘Tis the season for 4K UHD and HEVC”

November 26, 2014June 14, 2019

Transistor-Level IC Design is Alive and Thriving

Transistor-Level IC Design is Alive and Thriving
by Daniel Payne on 11-26-2014 at 7:00 am
Categories: EDA, MunEDA

There’s much talk in EDA about High Level Synthesis (HLS), Transaction Level Modeling (TLM) and the Universal Verification Methodology (UVM), however there’s a lower-level of abstraction, the transistor-level, where high-speed digital cell libraries are created, analog circuits are crafted, and AMS designers tweak transistor sizes and choose circuit topologies in order to meet stringent specifications. At the transistor level the IC designers have many challenges, like:

Will my circuit be robust and work across all PVT conditions?
How does process variation effect the yield of my design?
Is my design optimized?
How do I port from 90 nm to 65 nm?
Does this analog topology work with FinFET processes?

One EDA company founded in 2001 has a focus on tools used for interactive, manual, semi- and fully automatic analysis, sizing, design centering and yield optimization of analog and mixed-signal circuits. Their annual user group meetingwas last week in Munich, and I attended to learn first-hand. The company is called MunEDA, pronounced moo-nee-dah.

An Example MOS Op Amp Circuit

The user group meeting started on Monday when Pierluigi Daglio from STMicroelectronics gave an overview of previous years, dating back to 2006. I first met Pierluigi back in 2010 when he was on a panel that I moderated at DACon the topic – Hot and SPICEy: Users Review Different Flavors of SPICE and FastSPICE.

Pierluigi Daglio, STMicroelectronics

Over the next two days we had 29 presentations, complete with Q&A to learn more about getting the best results out of transistor-level designs. Here’s a quick list of presentation titles:

ICScape – Accelerate Design Closure
MunEDA – Statistical Verification and Analysis Tools
SMIC – Process related yield debug and optimization of analog IP with MunEDA WiCKeD
Lantiq – Sign-off flow for RF design with WiCkeD in a 65nm Technology
Novatek – S&H Sample & Hold (ADC) Mismatch Analysis and Sizing using WiCkeD
IPGEN – New layout generation techniques for variation sensitive analog circuits
MunEDA – Reliability & Robustness Based Design Using WiCkeD
STMicroelectronics – I/O Design Optimization Flow for Reliability In Advanced CMOS Nodes
Infineon – Reliability Aware Design of Relaxation Oscillator in Advanced CMOS Technology Nodes with WiCkeD
STMicroelectronics – IOs circuit optimization activities to enhance productivity, circuit robustness and improve existing reliability flow
Sapienza University Rome– Digital standard cell noise margin optimization, also considering aging effects with MunEDA WiCkeD and
Synopsys MOSRA tools (MANON)
Infineon – Safeguarding Hold time Margin for Internal Scan Chain in Multibit-Register Standard cells
Altera – Distributed Memory Design (MLAB) – design optimization and worst case analysis on memory cells, data paths and write pulse
generators with WiCkeD
MunEDA – Advances in Circuit Migration
HLMC – 55nm to 40nm Bandgap porting with SPT & High gain Amp optimization with MunEDA WiCkeD
Fraunhofer – Silicon Proof of the Intelligent Analog IP Design Flow using WiCkeD
MunEDA – Full-Custom Low Power Design Methodology with MunEDA WiCkeD
MunEDA – Ultra High Sigma (6+ Sigma) Analysis – High Sigma is not enough
STMicroelectronics – Corner Verification and Design Optimization in Smart Power & Non-Volatile Memory Technologies
University Frankfurt – FEATS – explorative automated topology synthesis with WiCkeD
Fraunhofer – Advanced measures for OpAmp optimization with WiCkeD
STMicroelectronics – Design validation and development of RF macrocells
ARP Microsystems – High-Voltage Automotive Analog IP Development for SOC using WiCkeD tools
Altera – Full-custom and Semi-custom Clock Trees Optimization using MunEDA WiCkeD – Clock Skew Matching, Clock Insertion Delay
and Duty-Cycle
STMicroelectronics – SMAC – Smart components and Smart Systems integration

Foundry partners included: STMicroelectronics, SMIC and HLMC. I had heard about the first two foundries, but HLMC located in Shanghai was new to me, and they offer 90 nm, 65 nm and 45 nm processes into markets like: standard CMOS, AMS, RF CMOS and NOR Flash.

EDA partners were: ICScape, IPGen. We’ve blogged about ICScape on SemiWiki last year, and then IPGen is a small startup with IC layout generation technology plus services.

Reimund Wittman, CTO, IPGEN

Each of the presentations were made using PowerPoint, and then attendees had a hard-copy handout which will be followed up with an online version with video archives for registered users. We had plenty of time to network and socialize during coffee breaks, lunch and a fabulous dinner on Monday night at the Agustiner Brewery.

Agustiner Brewery

The most creative presentation had to be from the University Frankfurt, where they had an analog synthesis framework that included expert knowledge to produce a wide variety of circuit topologies. They connected their framework to the circuit sizing optimization in the MunEDA WiCkeD tool.

Markus Meissner, University Frankfurt

On the fast digital side was a paper from Altera about how they optimized the transistor sizes for clock trees used inside of their latest FPGA designs.

B.Y. Ng, Altera

Overall I learned that transistor-level IC design is alive and thriving, thanks to the University curriculum on AMS design techniques, commercial practice of circuit design, demand from foundries for libraries, and finally EDA tools that enable analysis and optimization.

November 25, 2014June 14, 2019

What makes the world smart?

What makes the world smart?
by Pawan Fangaria on 11-25-2014 at 4:00 pm
Categories: Coventor, EDA, Foundries, TSMC

The simple answer is when everything in the world is smart. But if you think deeply, you would find that the continuous progression to make things easy in life is what makes the world smarter day-by-day – the sky is the limit. In the world of computing, consider the 17[SUP]th[/SUP] century era when humanbrain was used as a computer and it took ~200 years when in 19[SUP]th[/SUP] century the first mechanical computer was invented by Charles Babbage considered as father of the computer. Today we are in much advanced state and the pace of innovation is pretty fast. Technology definitely makes things smarter, life easier, and pace of doing things faster.

Today we are talking about IoT which makes all devices around us smart enough to sense and act as programmed by us, whenever and from wherever we want. What makes it possible? Sensor is not a synonym of smart, but it is the technology which enables smart things to be done. Various types of sensors can detect every movement, temperature, pressure, light etc. and activate its device to do something. We often hear talk of a world with a ‘Trillion Sensors’ associated with IoT, and we are getting there….

In 2014 MEC(MIG’s MEMS Executive Congress), Chris Wasden, Executive Director, Sorenson Center for Discovery and Innovation, University of Utah talked about the number of internet devices in use: >5 Billion today and is expected to reach 18B by 2018, and the number of sensors crossing 1 Trillion by 2025. And he talked about platform leaders (device, chip, MEMS etc.) to emerge and MEMS to co-create an industry platform to reach the 1T target.

Interestingly, foundry leaders are taking great interest in MEMS. George Liu, Director, TSMCtalked about multiple technology drivers (Personal, Home, City, Automotive and so on) in the context of IoT as against mainly computers in last several decades. He recognized the importance of sensors in making the devices intelligent and smart and also the gaps (material, architecture, low power, integration, packaging, capacity and price) that need to be filled to bring MEMS into main stream. And how can foundry contribute in filling the gap? Of course supply chain, ROI, scaling and so on, but what caught my attention are sensor and MEMS PDKs and joint process & product development between design and foundry. Wow! This can open up big opportunity for fabless MEMS development. This reminds me about one of my blogs (What will drive MEMS to drive I-o-T and I-o-P?) in which there was emphasis on standardization which can bring MEMS into volume production, and GLOBALFOUNDRIES pursuing the path of IC fab-like production discipline for MEMS.

Getting to 1T sensors is not a slam dunk; like EDA enabled fabless IC development, we need highly sophisticated and integrated automation including modeling to accelerate MEMS development. In the days to come we will see newer and newer MEMS devices, which is beyond our imagination today. But that reality has to be complemented by automated tools which can model the MEMS accurately, integrate them at system or IC level and verify accurately as fast as possible.

Taking at look David Cook’sblogat Coventorwebsite where he mentions about CoventorWare and MEMS+for MEMS+IC co-design, modeling, simulation and analysis, and SEMulator3Dfor virtual fabrication of MEMS devices to cut down on long build-and-test cycles through fab and improve yield before production, I concur with him that these tools are very apt in today’s environment to cater to the complexity of a variety of MEMS, yet meet the shrinking time-to-market window. In fact this reminds me about another blog written by Gunar Lorenz on new capabilities in MEMS+ 5.0– Breakthrough MEMS Models for System and IC Designers.

In MEMS+ 5.0, Reduced Order Models (ROMs) of MEMS devices (which allows writing out snap shots of sophisticated nonlinear multi-physics models into Verilog-A protecting the IP) can be exported into Simulink schematics for system designers and circuit schematics for IC designers. Verilog-A ROMs can run up to 100 times faster than full MEMS+ models in CadenceVirtuoso or MATLABSimulink. Users can decide whether to write out ROMs in Verilog-A for circuit schematic or MROM (a new file format) for Simulink. The environment provides good set of controls for users to tradeoff between accuracy and speed. Simulation results from MROMs can be viewed and animated in 3D, just like results from full MEMS+ models.

Smart tools to develop smart MEMS, smart MEMS to develop smart devices and smart devices to make smart eco-system are must to create a smart world!

Coverage Driven Analog Verification

Coverage Driven Analog Verification
by Paul McLellan on 11-25-2014 at 7:00 am
Categories: EDA

Ad hoc digital design verification approaches ran out of steam at least a decade ago when designs got intractably large to make it feasible to keep track of everything with pen and paper and excel. But analog design has remained largely ad hoc to this day. The designer runs spice, looks at the waveforms that come out and decide whether or not they are acceptable. But now even in analog design this sort of undisciplined approach is in turn starting to change away from the traditional methodology in the diagram below.

There are a number of reasons for this. One is that digital design (and the unit test approach to software development) has such clear advantages that it is silly for analog design not to piggyback on the experience. At the same time more and more analog, especially in the more advanced processes, is relatively simple analog design with very complex digital logic used to trim it, sometimes called digital controlled analog or DCA, meaning that the analog and the digital aspects of the design need to be verified together.

Digital design and analog designs are complementary in some ways. Digital is straightforward to design (at least from the RTL onwards we have a working methdology) but verification is very hard due to the impossibly large state space. Analog, on the other hand, is easy to specify but actually designing the blocks is extremely hard. As a result digital designers adopted coverage driven verification (CDV), based on assertions and property checking and verification planning to ensure that verification cycles are not wasted on things that have already been verified.

With the increased complexity of analog designs and IP due to the implementation of an increased number of features and functionalities as well as greater challenges due to the large variation of device characteristics in nanometer technologies, verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This work aims to extend common traits of CDV as used in digital verification to analog verification. This would bring standardization of the analog verification process.

A further driver is that standards for aerospace and automotive, such as ISO 26262, will no longer accept an ad hoc approach to requirements tracking. This too drives towards a much more formal approach:

specification of all requirements, whether analog or digital
a test plan and test cases to verify whether each requirement is met
metrics for measuring coverage of the tests in the test plan
a system for tracking requirements to ensure that they are all met and to reduce duplication of unnecessary tests

Mentor has a new white paper A Complete Analog Design Flow for Verification Planning and Requirement Tracking by Atul Pandey, Guido Clemens, Marius Sida. The whitepaper describes building a flow for CDV based on ICanalyst, Questa and ReqTracer.

You can download the whitepaper here.

Where have all the semiconductor drivers gone?

Where have all the semiconductor drivers gone?
by Bill Jewell on 11-24-2014 at 11:30 pm
Categories: Mobile, Semiconductor Intelligence, Semiconductor Services

Tablets and smartphones have been key drivers of electronics and semiconductor growth for the last few years. However the growth rates for these devices are slowing as they have become more prevalent. Tablet shipments are expected to reach 229 million units in 2014, according to Gartner, equal to 73% of PC units. IDC projects smartphones will exceed 1.2 billion units in 2014, accounting for about two-thirds of total mobile phones. As show in the chart below, shipments of tablets versus a year ago have slowed to about 11% for the last two quarters from growth in the 90% to 160% range in 2012 and early 2013. Smartphone growth has decelerated from the 40% to 50% range through 2012 and most of 2013 to the 20% to 30% range for the last four quarters.

Despite the slowing growth of tablets and smartphones, new categories of devices are emerging to drive growth. Gartner has identified a segment which it calls ultramobile premium PCs – devices which have the functionality of PCs in lightweight and smaller packages similar to tablets. With 71% growth in 2015, Gartner expects these devices to drive 3.6% growth in total PCs in 2015 despite a 5.6% decline in traditional PCs. Gartner projects the tablet market will grow 19% in 2015. Combining tablets and ultraportable premium PCs results in 32% growth in 2015.

IDC has segmented out a high growth product area in smartphones which it calls phablets (combining phone with tablet, although I doubt any self-respecting supplier will use the term for its products). Phablets are smartphones with screens from 5.5 inches to 7.0 inches, thus displacing many of the smaller tablets. IDC forecasts the compound annual growth rate (CAGR) for phablets from 2014 to 2018 will be 36%, driving the total smartphone CAGR to 10.1% despite only a 3.7% CAGR for regular smartphones. IDC projects the CAGR for tablets from 2014 to 2018 will be 6.8%. Combining tablets with phablets drives a CAGR of 22%.

The ultimate winner in the merging of PCs, tablets and smartphones remains to be determined. It is likely that several categories of devices will continue to claim various segments of the market. Most business users will continue to need the full functionality of a PC, but may compromise with an ultramobile to get the portability and flexibility of a tablet. Many young consumers use their smartphones as their primary communication and computing device, but may like the tablet-like functions of a phablet. In many emerging markets, consumers cannot afford multiple devices and will chose the one device which best fits their needs.

November 24, 2014

SIM cards and avoiding stranded IoT assets

SIM cards and avoiding stranded IoT assets
by Don Dingee on 11-24-2014 at 4:00 pm
Categories: IoT, IP, Sidense

Since pennants, drums, smoke, and horses fell out of favor to more advanced communication technology, network operators have struggled to find balance. Too few subscribers interested, and infrastructure investments completely fail. Just the right number of paying users, revenue streams provide profit and ability to invest in growth. Too many connections, and a network clogs, and subscribers curtail use or flee for alternatives.

In the early days of the electrical telegraph, three innovations provided the breakthrough. One wire systems made pulling cable relatively inexpensive compared to early six wire attempts. Relays provided signal boost needed to span more than a few kilometers. Morse code created a compact, standard message format.

With popularity came the next challenge. Operators restricted telegraph messages to a 10 word limit, with overage charges for verboseness. It wasn’t entirely because they were money-grubbing capitalist pigs; there was a practical reason. Only one message could be on a given segment of wire, so longer messages meant increased wait times for network access. Advances in the harmonic telegraph – an early use of frequency division multiplexing – and switching stations providing multiple routes to get to a destination helped.

A similar problem arose with the early generation mobile telephone, “0G” in telecom parlance. There was one big transmit tower with 12 frequency slots for a given city. Perhaps there were a couple thousand people with radios, but only 12 could get on the network at a time. Waits were typically 30 minutes to place a call. Part of the problem was spectrum allocation, and part was computational power needed to encode and decode more connections.

Video content drove 4G, and even with cell tower proliferation, more spectrum, improvements in DSP, and denser LTE encoding, we still don’t have enough bandwidth to keep up. Wi-Fi offload saves users from hitting their data plan cap, but it also keeps the network from total congestion.

Now, all these IoT devices show up. Fixed sensor clusters can use wired gateways. Personal clusters based on smartphones hang on the 4G network. Agile clusters – think connected cars, trucks, buses, trains, airplanes, ships, anything that moves – also rely on a cellular M2M gateway. Wi-Fi does not address mobility, and it does not look like WiMAX will achieve wide scale deployment. With 2G networks sunsetting, individual IoT devices may not need 3G or 4G bandwidth for data, but nonetheless they consume spectrum for a connection to the cloud.

Devices resembling connected cars also need to be portable across markets, for original sale, use, and resale. The solution to that in mobile phone space was the SIM card, and there are now those thinking we need a similar idea for IoT devices. SIMs carry the international subscriber mobile identity (IMSI) and an authentication key plus other info.

courtesy GSMA

A SIM would keep unauthorized IoT devices off the network, and enable services network operators can monetize. The user-installable SIM form factor seen in smartphones is less than ideal for IoT use. A solderable, embedded SIM form factor such as embedded universal integrated circuit card (eUICC), can add SIM-style functions to IoT devices. For instance, there is a Gemalto implementation of an MFF2 machine identity module.

Gemalto MFF2 package for embedded SIM

One-time programmable memory would play a key role in embedded SIMs, just as in mobile SIM cards. It would prevent tampering and enable secure provisioning of IoT devices. However, in cases such as the connected car, transition of service to new ownership is important. OTP can emulate multiple time programmability by using replicated blocks and pointers, allowing reprogramming of keys. Or, creative applications could emerge such as a device locked for a contract period, then unlocked for its remaining life.

The GSMA in conjunction with Beecham Research Ltd. has produced a study on the use cases for eUICC in M2M or IoT markets. Their points on connected cars are well taken; proprietary solutions could slow adoption and reduce portability upon resale or service termination, perhaps to the point of leaving allegedly connected assets “stranded” off a network. The text narrative and reasoning in this study is worth a look, even if the forecasts don’t come to pass as shown. Also worth noting: Apple is all over eUICC.

If network operators are going to embrace IoT devices to the degree people are projecting, the use case for the entire lifecycle needs careful consideration. It would be a shame to lose the benefits of connectivity of a thermostat, car, or other long life IoT device over not incorporating ID/key reprogrammability or unlocking in some form. Embedded SIMs may be part of the answer.

Rekeying the IoT with eMTP

November 24, 2014June 14, 2019

Mentor Aims to Improve Yield and Production Ramp for PCBs

Mentor Aims to Improve Yield and Production Ramp for PCBs
by Tom Simon on 11-24-2014 at 7:00 am
Categories: EDA, Siemens EDA

Getting a printed circuit board from design and into production presents one of the biggest challenges in successfully launching a product. The designer’s job is to anticipate issues that can adversely affect PCB fabrication and assembly. Design rules and component libraries go part of the way, but there is a thicket of things that determine how many iterations will be needed with the manufacturers and how quickly volume production can start at high yield.

I attended a presentation recently that was given by Julian Coates from Mentor’s Valor Division on their NPI (New Product Introduction) offering. Valor products are well known and widely used by PCB fab and assembly houses. But very often designers rely on their vendors to run it to provide feedback. This was confirmed by a friend of mine whose company does contract board design, “I just let them run it and tell me if there are any issues.” But he conceded that Valor provided much needed information to ensure manufacturability. An example of one such issue is where a net touches itself and creates clearance issues for reflow soldering. It’s not a short, but can cause bad solder connections. Valor can spot these kinds of issues easily.

Valor NPI is intended for designers and NPI engineers to run during the design phase. By pulling necessary changes forward in the design process, it reduces costs. Mentor’s Julian Coates cites a study that shows the use of Valor NPI can reduce the average number of design to fab house iterations from 2.8 to 1.5. Given that each turn will have associated costs, this represents a big savings in money and time.

Mentor’s challenge is to get designers and NPI engineers to run the tool themselves. This means leaving Allegro, for instance, and getting into Valor. Mentor explained that they have interactive integration to make this convenient.

Often there are multiple sources for parts and multiple fab and assembly providers. Valor NPI can help with each of these. The PCB editor parts library is actually just shapes for the copper and board, not actual part geometry. If you dig into the inventory parts that might be used for a given SMT device, you will see subtle variations of the terminal geometry. Not all 0402 10K resistors are exactly the same. Locking in to just one supplier could affect the supply chain. Valor NPI addresses this by complimenting the PCB editor library with their physical parts library with thousands of actual device dimensions. This means that for all alternative devices, it is possible to see exactly how the pins will contact the PCB, showing if the pad geometry will work well for all possible inventory parts. The same goes for pad position as well as size. Badly positioned pins on pads will cause bad solder joints and is a leading cause of PCB failure.

Lastly one of the examples I appreciated the most was the case where the solder stencil opening for a pin touched a nearby net. Valor flags this kind of issue, avoiding solder bridges leading to design failure.

DFM rules vary between fab and assembly suppliers. Valor NPI can maintain different DFM rules for each vendor. One of the attendees at the event mentioned that they always use multiple vendors for manufacturing. Being able to run all the vendors’ DFM rules seems like a good capability to ensure manufacturability during design. Valor NPI also adds a qualitative aspect to DFM. It does not just provide pass/fail for DFM checks. It encourages practices to boost yield by advising when certain dimensions are reaching critical values. You might have a reason for 6 mil spacing in specific locations, but you probably want to avoid it where you can even if it is OK within the design rules. Valor NPI will give you a histogram showing red and yellow rule warnings, as well as black hard violations.

Valor NPI also lets designers do their own panelization. It handles all the tricky issues with outline milling with mouse bites, and v-grooves. In addition to fiducals, if rails are deemed necessary they can be added. The Valor parts library is helpful here because it has the physical dimensions for connectors and potentially overhanging components that would cause issues during assembly.

PCB manufacturability is a huge issue. Mentor has impressive expertise in PCB supply chain tools. Valor NPI applies this expertise to provide a compelling solution for the design side of the business. The only question is if they can convince designers and NPI engineers to adopt their proposed process. It seems that the business case for doing so is strong.

They will let you try it free for 5 days. More information about Mentor’s Valor NPI can be found here.

November 24, 2014

Codasip and Coby and Czech

Codasip and Coby and Czech
by Paul McLellan on 11-24-2014 at 12:00 am
Categories: EDA

At ARM TechCon I ran into Coby Hanoch who has just been appointed VP worldwide sales of a comany that I’d not previously heard of called Codasip. As the name implies they supply code, and ASIPs. Well, actually IP source code and ASIP tools. The company is based in Brno (pronounced pretty much like Bruno) in the Czech republic with a sales presense in US, EU, Israel, Japan, China and Korea. They have actually been working on technology in an incubator since 2006 but were spun out as a venture funded company in Q1 this year.

Coby was most recently at Jasper Design Automation where he ran worldwide sales. Of course Jasper was recently acquired by Cadence and so Coby was surplus to requirements.

ASIP stands for application specific instruction-set processor and they fill the gap between standard microprocessors such as ARM or MIPS, and writing RTL (or using HLS) to implement the functionality. You get close to the flexibility of a software-based solution with close to the performance of doing the RTL. ASIPs are typically used for doing very specific functions that require unique performance capabilities that a standard microprocessor cannot deliver, typically either ultra-low-power or else very high performance.

For example the “OK Google” engine above. A very low-power always on ASIP with very limited detection capabilities fronts a second ASIP with a full speech recognition engine to understand the request. Then depending on the request, other parts of the system are woken up (such as a high powered multi-core processor) to perform the tasks.

Codasip have a language, CodAL, for processor description. It supports all processor architectures such as RISC, CISC, DSP and VLIW. This is then run through Codasip Studio to generate all the views required to actually use the processor:

Synthesizable RTL
UVM testbench
Compiler (using LLVM)
Assembler
Debugger
Virtual platform
Profiler
And more…

IOT, wearable devices, automotive and medical products require many specific processors which provide best performance with minimal power consumption. Codasip’s profiler enables the designer to tailor the architecture and optimize the power-performance-area equation They also provide generic IP modules for RISC, DSP and VLIW which users can use to jumpstart the design, adding/removing/modifying them with total flexibility so they are optimal for their needs. They are focused on leveraging standard technologies such as LLVM, GNU, QEMU, etc., so the generated elements can be integrated with the rest of the customers environment.

As an example, look at Sobel edge detection with grayscale output. This takes in a color picture, finds all the edges and outputs a black and white version with all the edges highlighted. By introducing a 128-bit SIMD extension they immediately get a 4X speedup compared to optimization done entirely at the sotware level.

Once the architect defines the Instruction Accurate model, the SW/Firmware team can immediately compile their code, run it on the emulator, and debug it, even before the HW guys developed the microarchitecture and have any RTL. The architects can profile the model and add/remove instructions/registers/memory elements to optimize the architecture. This means that software development and SoC development can proceed in parallel, pulling in the design schedule significantly.

The Codasip website is here.

Leakage Current TCAD Calibration in a-Si TFTs

Leakage Current TCAD Calibration in a-Si TFTs
by Daniel Payne on 11-23-2014 at 4:00 pm
Categories: EDA

Two weeks ago I blogged about amorphous silicon and how that material is well-suited for designing TFTs. Today I’m following up after watching the archived webinarpresented by Nam-Kyun Tak of Silvaco. After clicking on that link you’ll be brought to a brief sign-up page and then can watch the archived webinar in your web browser. This info is most appropriate for TCAD engineers who want to predict semiconductor behavior while gaining insights before actually fabricating a new technology. Continue reading “Leakage Current TCAD Calibration in a-Si TFTs”