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October 13, 2014June 14, 2019

Proving the Power of Virtual Fabrication

Proving the Power of Virtual Fabrication
by Pawan Fangaria on 10-13-2014 at 7:00 am
Categories: Coventor, EDA

There are many facets of our lives that are being driven to a more virtual method of doing things. This is largely due to issues such as scaling due to whatever reason – technical, business, economic. Let’s look at some general cases: In yesteryears people used to travel all the way for face-to-face meetings; today virtual meetings using video conferencing technology happen within couple of clicks on your Smartphone or notebook. Similarly, I completed one of my management courses attending only virtual classes throughout the course on my notebook screen for several months. And people from across the world often attend on-line webinars on important technical topics. These are just a few ways we see technology enabling more efficiency by moving from physical to virtual, saving us significant time and costs. And these virtual solutions are proven to work very well.

These are mainstream examples but we can see the same trends in the semiconductor area which is growing more and more complex by the day as we move towards newer nodes. The design of a chip is by its nature a virtual process driven by EDA tools. The latest examples being virtual prototyping and virtual platform for architecting and optimizing an SoC at the system level. A chip design sees the real world only at the time of fabrication in a foundry, which tells about how close was the design to the reality. This is a very simplistic visualization of this scenario.

Things get really complex and murky when we look at process variation taking place at ultra low nodes. The result then is what you design is not what you get in the actual fab and you end up in several cycles between the design and the fab. In such a situation, the idea of a Virtual Fabrication Platform to quickly experiment, measure process sensitivities and devise process integration steps for the designs to work correctly during actual fabrication proves to be a boon. It saves time and costs for process engineers and design engineers.

I can recall about a blog I had written about a year ago about how 3D NAND Flash development can be accelerated with the use of Virtual Fabrication, in which David Fried, CTO – Semiconductor at Coventorhad provided his great insight into Virtual Fabrication and how SEMulator3D can help.

Read to know more – What Can Accelerate 3D Semiconductor Manufacturing

Today, while reading an articlewritten by Ryan Patz of Applied Materials who earlier worked at Coventor as well, it revived my memories about the business and technical crisis NAND Flash is experiencing. While 3D NAND is still away, 2D NAND needs continuous scaling in order to be profitable for business. And that needs extensive experimentation to build newer process models for smaller feature sizes and higher yields.

Ryan is a known expert in semiconductor fabrication technology. He studied the quadruple spacer patterning technology, slimming of floating gate (FG), and word-line (WL) and bit-line (BL) direction air gap to enable a “Middle-1X nm NAND” (M1X-NAND) flash memory cell announced by SK Hynixat last year’s IEDM 2013 and experimented further on SEMulator3D’s Virtual Fabrication platform to build a process model to understand the bidirectional air gap formation and corresponding process sensitivity because it’s necessary for the ‘quadruple spacer technology’ to overcome the effects of process variation to deliver a narrow distribution of device performance.

The air gap formation in both directions, WL and BL, is extremely sensitive to the conformality of the dielectric deposition process and FG slimming. In the above image, the baseline model is seen to be centered right in the middle of a steep sensitivity with deposition conformality (lateral/vertical) ratio of 0.1. Any small variation in deposition conformality can have large impact on the air gap cross-section area.

This study clearly shows the advantages of process studies in a virtual platform which can be quickly done off fab and used for process optimization and prioritization. The SEMulator3D is quite well-equipped to devise new optimized process integration flows for the newest nodes and help scaling future technologies.

I am happy to see this study done by using SEMulator3D to further prove the power of Virtual Fabrication. Read Ryan’s article to know more about this study here.

CASPA, ARM and the Internet of Things

CASPA, ARM and the Internet of Things
by Paul McLellan on 10-12-2014 at 7:01 am
Categories: Arm, CASPA, IP, Semiconductor Services

Today I was at the Chinese-American Semiconductor Professionals’ Association conference and dinner. Simon Segars, CEO of ARM, gave the dinner keynote. Somewhat surreally, it was in the same room in the same conference center two weeks ago that he gave they keynote at ARM TechCon. In another coincidence, Mike Muller of ARM gave one of the keynotes at TSMC’s OIP conference the day before, and then at ARM TechCon too. October seems to be all ARM all the time.

The CASPA event was titled Intelligent and Secured Living in a Connected World. It was really about the Internet of Things (IoT) with presentations from Broadcom, AMD, Imagination and SnoopWall. The most provocative presentation was the one by Gary Miliefsky of SnoopWall about privacy and security. He talked about how flashlight apps are all malware and hundreds of millions of phones are infected. He was recorded for ABC news (I think it was) and it should be broadcast early next week. When he was asked whether he thought it was possible to build a secure phone he was pessimistic: you can make it a lot better than it is today but the NSA is simply not going to let you build something that they are kept out of. I don’t know all the details but the Blackphone developed in Switzerland was taken off sale for a time and he is sure now that it is back that it has been compromised. There are videos from other news programs on the SnoopWall website.

Simon Segars talked about the impact of IoT on the semiconductor business and on ARM in particular. At ARM TechCon a couple of weeks ago ARM announced two things that are especially important for the IoT market. First, they announced their highest end Cortex M series, the Cortex-M7. It combines a six-stage, superscalar pipeline with flexible system and memory interfaces including AXI, AHB, caches and tightly-coupled memories, and delivers high integer, floating point and DSP performance in an MCU. Between the M0 and the M7 there is a huge range of performance and these processors are ideal for many IoT projects.

They also announced the ARM mbed IoT device platform. This consists of 3 products:

the mbed OS. This is an operating system for the Cortex-M series that is free for use on theose processors. It consolidates the fundamental building blocks of the IoT in one integrated set of software components. It contains security, communication and device management features to enable the development of production-grade, energy-efficient IoT devices
the mbed Device erver to connect and manage devices in a secure way. It also provides a bridge between the protocols designed for use on IoT devices and the APIs that are used by web developers. This simplifies the integration of IoT devices that provide “little data” into cloud frameworks that deploy “big data” analytics on the aggregated information.
mbed.org The website provides a comprehensive database of hardware development kits, a repository for reusable software components, reference applications, documentation and web-based development tools.

The idea is to make it straightforward to build IoT projects with the mbed OS running on the sensor/compute/communicate chip, the mbed Device Server running on a web server or in the cloud, and mbed.org to create a strong community of developers. The mbed.org website is not new, it already has 70,000 developers using it.

TSMC ♥ Cadence!

TSMC ♥ Cadence!
by Daniel Nenni on 10-11-2014 at 4:30 pm
Categories: Cadence, EDA, IP, TSMC

One of the questions I routinely ask amongst the fabless semiconductor ecosystem is, “How are the EDA vendors doing?” There are always complaints because, let’s face it, we all like to complain. On occasion however I do hear about a vendor who goes above and beyond the call of duty and it really brightens my day.

Of late, the highest praise has gone to Cadence. I was working in Silicon Valley in the early 1980s when EDA began to flourish. It was mostly DMV (Daisy, Mentor, Valid) when two smaller start-ups merged (ECAD and SDA) in 1988 to create Cadence. I credit Joe Costello with making EDA an exciting place to work. Unfortunately, after Joe left in 1997 Cadence seemed to lose its way. In January 2009 Lip-Bu Tan joined Cadence as President and CEO after serving on the Cadence Board of Directors for five years. To me that was a turning point for Cadence which brought them back to what they are today, an industry leader. Cadence stock agrees as it has more than tripled since Lip-Bu took over as President and CEO.

20nm was a defining node as it required much closer collaboration amongst the fabless semiconductor ecosystem. Double patterning is one example but there are plenty of others. At 16nm we have FinFETs and even more challenges ahead especially for analog and mixed signal design and as we all know Cadence is the AMS design market leader. 10nm is well underway and Cadence is a key player in the development of IP and PDKs to which TSMC acknowledged during their Open Innovation Platform Forum:

Cadence Wins Two TSMC Partner of the Year Awards for Soft IP and 16FF+ Solutions

“We presented the awards to Cadence based on the quality results delivered through its Soft IP and 16FF+ solutions,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Cadence has demonstrated its commitment to working closely with us to bring the highest quality design capabilities to IC designers around the world, and we look forward to continuing our partnership in the years to come.”

Dr. Chi-Ping Hsu, senior vice president, chief strategy officer, EDA, and chief of staff to the CEO at Cadence, commented on the awards, saying, “The award recognition from TSMC reflects our long-standing relationship and further demonstrates our ongoing commitment to delivering a strong IP portfolio and advanced-node technology for next-generation SoC designs.”

Dr. Hsu from Cadence further commented, “Customers that create chips for the world’s newest mobile devices are already tapping into the benefits of the 16FF+ design flows and can start to adopt 10nm FinFET solutions to overcome design complexity and get to market faster.”

This did not come as a surprise to me because of the many EDA people I see in Hsinchu. One of the more critical components of collaboration is the willingness to “show up” and during my travels I most often see Cadence executives. Contrary to unpopular belief, there is no such thing as tossing semiconductor designs over the wall to manufacturing so if you want to know who the key players are in modern semiconductor design and manufacturing spend time at the Hotel Royal, The Sheraton, and the Ambassador Hotel in Hsinchu. Or just hang out in the lobby of TSMC Fab 12.

And yes I know Synopsys and other partners were recognized by TSMC, and rightly so, but I give the SemiWiki award for Most Improved EDA Vendor to Cadence, hands down. Ha ha, you thought I was going to say “absolutely” didn’t you?

What’s next in test compression?

What’s next in test compression?
by Beth Martin on 10-10-2014 at 4:45 pm
Categories: Events, Siemens EDA

If you’ll be at ITC TestWeek in Seattle (Oct 20-23), here’s one event you don’t want to miss: a technology reception hosted by Mentor, with Janusz Rajski and Nilanjan Mukherjee as the featured speakers. It is free to ITC attendees and you can register here. [If for some crazy reason you haven’t registered for ITC yet, do that here.]

If you are involved with DFT, you’ll recognize Rajski as the inventor of the embedded deterministic test (EDT) technology that is the basis for ATPG compression. He is a chief scientist and the director of engineering, but you can think of him as Mr. Compression. Mukherjee is the engineering director for the test synthesis group at Mentor Graphics.

EDT has scaled to 100x compression, but new technology nodes and new fault models targeting defects within standard cells are driving the need for even greater compression levels. Rajski and Mukherjee will introduce a novel technology they developed specifically to work with embedded compression to further reduce pattern volume for compressed patterns. You will also learn how Mentor’s customers are using this new technology.

The presentation starts at 7:00pm and should last 40 minutes. After that, they will open the bar, pass the finger foods, and turn on the disco ball. Actually, I made up the disco ball part. See you there!

What: Seminar and Reception, The Next Big Thing in Test Compression (Register)
When: Monday, October 20. 6:45pm Doors open
7:00pm Presentation begins
7:40pm Drinking and dancing begins

Where: WSCC North Galleria, Room 2B

International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

October 10, 2014

Full-Chip Electromigration Analysis

Full-Chip Electromigration Analysis
by Daniel Payne on 10-10-2014 at 7:00 am
Categories: EDA

I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine how much more important EM analysis is today on chips using 20 nm and smaller geometries, with 10+ metal layers, and even 3D stacking. Valeriy Sukharev, Ph.D. of Mentor Graphics just wrote an 8 page White Paper titled: Electromigration Analysis At Advanced Nodes, so I read it today to learn what the new EM challenges are all about.

Sukharev earned his master’s degree in solid state electronics and a Ph.D. in physical chemistry of solids and interfaces. He’s been a principal engineer at Mentor since 2008, and before that was at Ponte Solutions as a chief scientist.

The power and ground nets in an IC are prone to EM effects because current flows only in one direction, and the interconnect of either aluminum or copper are subject to EM because the materials have high self-diffusivity. As current flows in a net there is atom depletion and accumulation caused by EM, creating voids and hillocks respectively:

Void and hillock formation

Using a Tunneling Electron Microscope (TEM), researchers at E. Zshech of Fraunhofer IZFP-D showed what voids look like:

Can two identical metal lines with the same electrical load have different EM characteristics? Yes, because there is variation in grain boundaries and atomic diffusivities. The Time To Failure (TTF) is a distribution function, so here’s a chart showing electrical resistance change as a function of time:

Effect of voiding on line resistance

Ideal equations for EM behavior are well understood and come from James Black and Blech calculated some 50 years ago. These equations don’t take into account new effects, like:

Dependency of MTTF on residual stress
Across-die variation
Layout dependent variables

Sukharev is proposing a new physics-based MTTF compact model, which does take into account the new effects listed above. This new model takes into account:

Temperature and current density effects
Impact of residual stress
Process variation

As an example, consider the following table where the time to create a void (the void nucleation time) inside of a 100um length line is a function of the current density and temperature of the stressing test. Values in yellow are immortal, meaning they will not have EM failure. The left column (J/test) has the conditioning temperature responsible for thermal stress-induced voiding.

Expect the next generation of EM tools to take into account a more optimistic approach that more closely model the actual physics of corner current densities and temperatures in the presence of variations. Residual stress effects will also be included in EM calculations for more accurate predictions. Read the complete White Paper here, after a brief registration process.

October 9, 2014July 18, 2025

Maker Movement Embraced by Major Semiconductor Companies

Maker Movement Embraced by Major Semiconductor Companies
by Tom Simon on 10-09-2014 at 10:00 pm
Categories: Arm, Foundries, Intel Foundry, IP, Synopsys

How the Arduino Changed Embedded System Development Forever

In 2005 with the development of the Arduino, everything changed for people building things that required a microcontroller. The Arduino brought with it a low price standard, and open, hardware platform and an easy to use open source development environment. It was not without its limitations, but it opened the doors for literally thousands of people who had ideas and did not want putting together the platform to take most of their time. According to Wikipedia, it is estimated that there are over 700,000 Arduino boards in developer hands.

It used to be that you needed to have a hardware programmer and had to master a long complex tool chain to develop, compile, link and load your code. On the hardware side, the Arduino brought a standard form factor and pin-outs, but more importantly standard libraries for things like digital IO, PWM, SPI and I2C. All of this was wrapped in an easy to install and use free development environment based on GNU tools, including a code editor and requiring no command line input. More information and the IDE are available at www.arduino.cc. The programming is made easy to use by simply connecting a USB cable to the board.

Once there was a ‘standard’ many compatible interface boards, called shields, and devices were developed. The libraries for accessing them were openly available in usable source code format for download and reuse. Sensors like MEMS gyroscopes or accelerometers, and proximity, light, temperature, image, touch, etc. became easy to use. Added to this mix were servos, motor controllers, addressable LEDs, and many other devices. Of course hobbyists picked up on this and it became a rapidly growing cottage industry. Just go to retailer sites like www.adafruit.com or www.sparkfun.com to see what is available.

The first Arduino used an Atmel microcontroller from the AVR series. They are 8 bit CPUs running at a modest 8 or 16MHz, digital IOs, and analog inputs. There is also flash storage on-chip for code storage, RAM for program data storage, and EEPROM. Flash and RAM are limited, but enough to get by for small projects. To give you an idea, all the data in your code was typically limited to 2K bytes. But there is no operating system and the program code can be loaded into the flash using a USB cable. The on-chip flash and EEPROM means that these chips were fabricated using older process nodes and proprietary processes.

Despite the initial limitations people became more ambitious with what they built. If you look today at almost any 3D printer or quadcopter, you will see an Arduino hidden inside. Thus the Arduino has become an enabling technology for a new wave of products. One notable example is the OtherMillthat can be used to fabricate custom PCBs at home.

Arduino clones appeared, many of them using the open source schematics from the Arduino Project. This meant that they were compatible with the Arduino IDE, making it easy for people to adopt. Often their code worked without any changes. New form factors were introduced by the Arduino Project, and other new boards appeared from other sources. Even non Arduino boards and non AVR processors could be supported by additions to the Arduino IDE. Today if you go look for Arduino compatible and ‘like’ development boards, you will be confronted by a large array of choices. Large semiconductor companies with their own processors, some of them ARM based, took noticed and developed their own boards and started bringing them the Maker Faire, which draws over 120,000 people in one weekend, in the San Francisco Bay area.

At the recent ARM TechCon, ST was handing out free development STM32L032 boards that use the ARM Cortex M0 core, a low power processor. However this board uses a non-Arduino tool chain, and setting it up requires some effort. This might be fine or someone who wants to develop a Cortex M0 system for a product and does not need the community of knowledge and code that the Arduino has. But the boards are attractively priced and it looks like there are some independent projects to build an Arduino compatible IDE.

Intel has not been absent from this market. They along with ST, Freescale, and others see the potential in this market. This is especially true as these boards gain wireless connectivity, like Bluetooth and even Wifi. Intel has just release a very small form factor board, called Edison, with a 22nm multi core processor using 2 ATOM cores running at 500Mhz. While it is running Yocto Linux, it offers the option of being programmed with the Arduino IDE. Of course you might prefer to write C++ or node.js for the Linux environment, but for getting started the Arduino IDE is hard to beat. This is not their first effort; they have had another board called Galileo out for some time.

But the new Edison board is different. For about $50 it has built in Bluetooth and Wifi, all in an extremely small, but non-standard, form factor. However Intel partnered with one of the well-known Maker retailers, SparkFun.com, to develop carrier boards that do offer the standard Arduino pin-out geometry. It comes with generous code and data space, 4 GB EMMC and 1GB LPDDR3 respectively. Also one of the cores on the die is a 100MHz Quark core that will run an RTOS developed by Intel’s Wind River subsidiary. Presumably serious IoT and wearable product developers will look to this platform as a powerful, low power and compact vehicle for their designs.

We are in the midst of a rapidly growing and changing landscape for small, powerful and easy to integrate and develop for embedded systems. Not even the Arduino Project is standing still. Their first ARM based board was the Due, and used an ATMEL ARM Cortex M3 core. They have already introduced the Yun, which in addition to the traditional 8 bit AVR processor, has an Atheros AR9331 core with an Open-Wrt based Linux along with Wifi to support a REST protocol interface API in the Arduino IDE. And an even newer offering from the Arduino Project has an ATMEL 32 bit ARM Cortex M0+ core to do both the user code execution and manage wireless interfaces. And of course the Arduino IDE can be used for the software development, just like the original 8 bit Arduino boards.

October 9, 2014June 14, 2019

StarVision to Debug and Analyze Designs at All Levels

StarVision to Debug and Analyze Designs at All Levels
by Pawan Fangaria on 10-09-2014 at 4:00 pm
Categories: Concept Engineering, EDA

In today’s SoC world where multiple analog and digital blocks along with IPs at different levels of abstractions are placed together on a single chip, debugging at all levels becomes quite difficult and clumsy. While one is working at the top level and needs to investigate a particular connection at an intermediate hierarchical level, she has to pass through several steps. Similarly one has to go through specified procedures when merging blocks at different levels of abstraction in a design. What if we have an automated tool which provides an integrated environment for all levels (e.g. RTL, Gate and Transistor) in mixed-signal designs in a single cockpit which can also be customized according to designers’ need? It will significantly improve designers’ productivity in integrating, analyzing and debugging SoC designs.

Yesterday, I came across a five minutes video demoon Concept Engineering’sStarVision tool posted on EDA Directwebsite. Although I have signed-up for Concept’s upcoming webinar on 21[SUP]st[/SUP] Oct, I just dived down this video. It was awesome in introducing the integration and navigation part of StarVision with a real example on how an RTL or a Spice level block can be merged into a design while staying in the same GUI and then stepping through several levels of hierarchy, views, cross probing etc. I could easily visualize how easy it would be for designers to analyze and debug the design using this environment.

This is an example of an IP; the top level is in Verilog with three instances – CPU, SYS and Parity. On the right side is the image of the CPU block which is loaded into the design. Any level of hierarchy inside the CPU block can be easily descended and probed against its code in Verilog.

Driving down the CPU block one can see the content coming from Verilog netlist. Above is the image of a multiplier instance inside the CPU. Its Verilog code view can be opened and probed against the schematic. The probing can be done from both sides.

Now let’s say SYS block which is at RTL level in Verilog has to be loaded and merged with the design.

The above picture shows the Verilog merge option and the top level view after SYS block loaded. The SYS block can again be navigated through for viewing and analyzing its contents down the whole hierarchy.

The Parity block is at transistor netlist level and has the Spice code view. This block is also loaded through hspice merge option as shown above. The demo shows driving down this block as well and cross probing between transistor level schematic and Spice netlist at any point in the hierarchy.

Cone window is an excellent feature through which any signal can be picked from the schematic at any level and clicked through to load objects connected to it. One can navigate through multiple levels of hierarchy at the same time staying in the same GUI and display all the different levels of inputs in the same view.

This is just a small demo which shows loading and navigating through different views of the design. There are host of other important features which makes a designer’s life easy in debugging complex SoC and IC design in complete transparent manner. To mention a few of them are – extraction of circuit fragments and saving as Spice netlists for investigation and re-use, easy design exploration by symbol creation from Spice netlists, dragging & dropping of selected components between all design views, analysis of parasitic networks and creation of Spice netlist for critical path simulation, ERC checking, and many more.

EDA Direct is organizing a free webinar which will provide complete details about Concept Engineering’s StarVision[SUP]TM[/SUP] PROcapabilities along with its usage of in-built utilities to provide a versatile environment for easily analyzing, debugging and integrating SoCs and ICs. The webinar’s schedule is as follows –

Date: 21 October, 2014
Time: 10:00 AM – 11:00 AM PDT
Media: Online via WebEx

Today, 16 out of top 20 semiconductor companies are using Concept Engineering visual debugging technologies. It will be worth spending one hour to know about actual details of this debugging environment.

Contact info@concept.de and sales@edadirect.com for any more information.

Xilinx Vivado: Faster and Better

Xilinx Vivado: Faster and Better
by Paul McLellan on 10-09-2014 at 7:01 am
Categories: FPGA, Xilinx

When you think of Xilinx the word FPGA is the first that comes to mind. But Xilinx has really moved beyond the sort of simple glue-logic arrays that their first success was built on. A modern array contains processors as well as programmable fabric, hence the Xilinx tag-line “all programmable”. But another area that doesn’t always get as much recognition as it should is Xilinx’s software toolchain. Today they announced a new version of their Vivado tool suite, 2014.3. The headline news is that it is significantly faster and so allows users to focus on the differentiated part of doing their design and less on the routine of getting the design into silicon. There is also an increased focus on high-level synthesis (HLS), basically programming your design in C rather than RTL.

SEMICON Europa

SEMICON Europa
by Paul McLellan on 10-08-2014 at 1:26 pm
Categories: ESD Alliance, Semiconductor Services

This week it is SEMICON Europa in Grenoble in the heart of the French Alps.

SEMICON Europa 2014 opened yesterday at ALPEXPO in Grenoble with more than 400 exhibiting companies. Learn about the latest innovative technologies, products, applications and business opportunities both within the European community and globally. Companies like Applied Materials, Intel, Infineon, Microsoft, Philips, Samsung, Sony, STMicroelectronics, and Tokyo Electron will present their strategies and requirements in SEMICON Europa programs and on the exhibition floor. SEMICON Europa 2014 (7-9 October) also features the new “Allée des Clusters” and Innovation Village, which will showcase more than 35 start-up companies and their innovative products and capabilities.

SEMICON Europa offers semiconductor Front-End manufacturing programs, including the 18th annual Fab Managers Forum, as well as programs on the Internet of Things, Automation Level in Fabs, and Smart Connected Sensor Devices. Consumers continue to drive an ever increasing demand for mobile electronics and interconnectivity — for both work and play. New devices are being developed and sensor applications are soaring to meet future requirements for processing and transmitting data/information across a variety of applications (i.e. healthcare, industrial, security, entertainment, energy efficiency, etc.). SEMICON Europa highlights include Electronic Applications (Imaging Conference and Nanoelectronics for Healthcare Session) and Electronic Components (Low Power Conference and Power Electronics Conference).

Other conference programs at SEMICON Europa will explore 450mm wafer processing and other critical issues in Fab Management, Advanced Packaging, 3D IC, Test and MEMS. Now in its third decade, SEMICON Europa’s new location leverages the growing strengths of Grenoble’s technology businesses, academia and institutions to showcase a diverse array of products, solutions and opportunities spanning the most advanced innovations in the European nano-manufacturing industry.

Also, at SEMICON yesterday, Albert Theuwissen, CEO of Harvest Imaging and professor at Delft University of Technology, received the European SEMI Award 2014. The Award, which recognizes Theuwissen’s outstanding contribution to the continuing education of engineers, was presented during the SEMICON Europa Executive Summit in Grenoble.

Albert Theuwissen is a highly regarded specialist in solid-state image sensors and digital imaging. He worked for nearly 20 years at Philips Research and then at DALSA in lead engineering and management roles. In 2001, Theuwissen became a part-time professor at Delft University of Technology. In 1995, he wrote the textbook “Solid-State Imaging with Charge-Coupled Devices” which is now a standard reference work in the field of solid-state imaging.

After “retiring” in 2007, Theuwissen founded Harvest Imaging and has played a major role in the continuing education of engineers in the field of solid-state imaging and digital cameras. He has taught and trained over 3,000 engineers at image sensor companies (such as Kodak, Sony, Samsung, Aptina, ST Microelectronics, Micron, Intel, Philips, Canon, DALSA, and Panasonic) and consumer product companies (such as Nokia, Sony-Ericsson, Motorola, Siemens, Research InMotion, Thomson, and many others). In addition, he has conducted short courses at IEEE’s IEDM, ISSCC, ICIP and SPIE’s Electronic Imaging Conference.

Full details of SEMICON Europa are here.

iPhone or Wallet – Which one do you go back for?

iPhone or Wallet – Which one do you go back for?
by Daniel Nenni on 10-08-2014 at 7:00 am
Categories: CASPA, Mobile

As a professional conference attendee I see a direct correlation between the number of people attending and the quality of the keynotes. Let’s face it, it’s all about the keynotes so you had better get some big names if you want more than your friends and family to show up. In this regards the upcoming CASPA event will probably be one of the most attended of its kind, absolutely. My beautiful wife and I will be there and I hope to see you there too. It would be a pleasure to meet you and be sure and tell my wife how famous I am because sometimes she forgets.

Also Read: Bouncing Between iPhone and Android

Today CASPA hosted a lunch for the press and speakers which I greatly appreciated. A free lunch is always nice but networking with the speakers prior to the event is truly enlightening. Candid conversations are the best way to understand what people are saying but also why they are saying it. One of the more interesting questions asked was: “If you left home without your wallet or your phone which would you go back for?” This has happened to me more than once and I always go back for my phone but not my wallet. Other than a driver’s license, everything is in my phone which brings us to the topic of this weekend’s conference:

Intelligent and Secured Living in a Connected World

Keynote Speakers:

[LIST=1]

Michael Hurlston, Executive Vice President, Broadcom – ” Powering the Internet of Things: Wireless Connectivity”

Raja Koduri, Corporate Vice President, Visual Computing, AMD – ” Visual Computing and Applications for Surround Computing”

Jim Finch, Vice President Business Development, Imagination Technologies – “Virtualization Enhances Security in Sensor Nodes”

Gary Miliefsky, CEO, SnoopWall LLC – “Is Digital Privacy Possible?”

Panel Speakers:

[LIST=1]

Gary Miliefsky, CEO, SnoopWall LLC

Tareq Bustami, Vice President & General Manager, Product Management, Freescale – “Solving the Networking Puzzle From IoT to SDN and Everything in Between”

Rakesh Mehrotra, Advisory Principal, Semiconductors, PwC – “The Impact of IoT on Semiconductor Companies”

Dr. Omkaram (Om) Nalamasu, Senior Vice President & Chief Technology Officer, Applied Materials, Inc. & – “Energy Storage and Energy Harvesting Technologies for Sensors and IoT”

Dinner Speaker:

Executive Keynote: Simon Segars, CEO, ARM
–“Choice, Collaboration, and Innovation”

In a world with billions of connected devices, the proliferation of intelligent devices has created a market for entirely new solutions based on the Internet of Things (IoT). This rapid growth in the number of intelligent devices presents many challenges, including significant impact on the architecture of M2M (machine to machine) services. There are many opportunities to extract value from the data generated in the connected world, but with these come possible risks to personal and enterprise security. Valuable data must be protected, from the data center to the network’s edge, while still being instantly available to users.

Our line up of distinguished industry experts will provide us greater insight into how their respective companies are addressing these challenges to enable all of us to enjoy “Intelligent and Secured Living in a Connected World”.

Date/Time: October 11, 2014 (Saturday), 12:00 pm – 5:15 pm
Location: Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA
Conference Registration: Here, Open to all, cost = FREE

Founded in 1991, CASPAhas developed into the largest Chinese American semiconductor professional organization worldwide. CASPA consists of individual members, corporate sponsors, board of directors, board of advisors, board of volunteers, and honorary advisors. Headquartered in Silicon Valley, California, CASPA has 9 local chapters worldwide: Austin & Dallas Texas; Phoenix Arizona; Portland Oregon; HsinChu Taiwan, Pearl River Delta (Hong Kong, ShenZhen), Shanghai, Beijing and Singapore. CASPA also forms alliance with other associations to promote welfare of its members.