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TSMC Gets Ready for IoT

TSMC Gets Ready for IoT
by Paul McLellan on 12-10-2014 at 11:36 am

With all the talk about 14/16nm and 10nm it is important to realize that older processes are still important. Eventually 16nm may end up being cheaper than 28nm but for the time being 28nm seems to be a sort of sweet spot, not just cheaper than every process that came before it (which was true for every new node) but also cheaper than every process that will come after it (which is new territory for the semiconductor industry). If you are designing an application processor for a smartphone then you will move to the new nodes as fast as you can. But other markets, in particular products for the internet of things (IoT) don’t need that. They need low power, digital/analog/RF integration and so on. This creates new opportunities in the non-bleeding-edge process geometries.

With the explosive growth phase of smartphones over, IoT is expected to provide a lot of the high growth consumption of semiconductor for the coming few years. PC is nearly flat, smartphone growth will mostly be at the low end of the market with the high end now being mostly a replacement market.


TSMC has introduced ultra-low power versions of some of its mature processes. The current status is that ultra low power versions of 0.18um and 90nm are in production and 50nm, 45nm and 28nm ULP processes will take risk production in 2015. There is also integrated RF and flash. These are especially attractive for IoT designs that need extremely low power and connectivity. Some IoT applications (such as automotive) are not all that power sensitive since there is a large battery available, but others such as wearables require very long periods between recharges, and still others are predicted to need a battery that lasts for the life of the product or they scavenge power from their local environment.


Some details of the process. First they operate at a lower Vdd which reduces both standby and active power (and leakage). They are optimized for the 0.5-0.7V range. The tailored eHVT device enables an over 70% reduction in standby power. However they can also work at higher voltages at 1.1V (40LP) and 1.2V (55LP).

Most IoT designs don’t seem to need really high performance nor billions of transistors since both would consume too much power. But they need the combination of very lower power operation, especially in standby where they will spend most of their life, and RF (since they need connectivity through cellular, WiFi, Bluetooth or some other radio interface).


So the bottom line is that the new processes are compatible with the existing eco-system at 28HPC. But the operating voltage is reduce by over 20%, active power by over 30%, standby power by over 70% and the capability to build an SoC that includes RF and embedded flash, perfect for the IoT market.


Intel has Another First for 14nm Production!

Intel has Another First for 14nm Production!
by Daniel Nenni on 12-10-2014 at 7:00 am

An interesting thing happened while I was researching a slide from Bill Holt’s “Advancing Moore’s Law” presentation at last month’s analyst meeting. Slide #19 mentioned that Intel was the first to use “air gap” dielectric spaces to improve performance in a digital logic flow for microprocessors. I know a certain foundry that is actively researching air gapping but for production this is a pretty major announcement that did not get the proper accolades in my opinion. The benefit of using the “ultimate” low-K dielectric can be huge however the devil is in the details.

To clarify I’m hoping the esteemed members of SemiWiki can help with the following questions:

[LIST=1]

  • What (additional) design restrictions does this impose?
  • What are the metal width and space options, to enable the “sealing” dielectric to surround the air gap?
  • What happens around vias?
  • What % of a typical wire could have a surrounding air gap?
  • Are general SoC designers ready for the additional tradeoffs (less wiring flexibility for reduced RC interconnect delays and noise coupling)?

    The first mention of this I found was from a paper at the 2010 International Interconnect Technology Conference. Researchers from Intel confirmed that the design constraint of a fixed spacing between interconnect lines allows for the use of air gaps in manufacturing to increase circuit speeds. Coincidentally one of the other references that came up when Googling around is a blog on the Coventor website “Got Air Gaps?” from Ryan Patz of Applied Materials which is definitely worth a read. “Coincidentally” because I will be moderating a panel with Coventor at IEDM next week in San Francisco on process variation:

    Survivor: Variation in the 3D Era
    It’s a jungle out there. The era of 3D semiconductors, 3D NAND Flash, FinFETS and unprecedented process complexity introduces new pitfalls for the cunning engineer to overcome. Find out how the best and the brightest are outwitting the competition with creative ways to navigate the treacherous landscape of advanced IC design and manufacturing. They know the key to survival in dealing with process variation is to …

    Reduce It. Contain It. Understand it.
    Join a group of rugged survivors at an interactive panel discussion, moderated by one of the original castaways from the IC island, Daniel Nenni of SemiWiki, and featuring:

    • Rich Wise, Lam Research
    • Jeffery Smith, TEL America
    • Tomasz Brozek, PDF Solutions
    • Tom Dillinger, Oracle Corporation
    • Jan Hoentschel, GlobalFoundries
    • David Fried, Coventor

    Location: “Carmel Room” at Hotel Nikko, San Francisco
    Date: Tuesday, December 16, 2014
    Time: 5:30pm -8:30pm (Cocktails and hors d’oeuvres) Panel begins at 6:00pm

    MORE INFO HERE

    You do not need an IEDM badge for this so please stop by if you can and meet the people behind the semiconductors that make modern life, well, modern.

    About Coventor

    Coventor, Inc. is the market leader in automated design solutions for developing semiconductor process technology, as well as micro-electromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, memory suppliers, fabless design houses, independent foundries, and R&D organizations. Its SEMulator3D modeling and analysis platform is used for fast and accurate ‘virtual fabrication’ of advanced manufacturing processes, allowing engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles. Its MEMS design solutions are used to develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, and gaming systems. The company is headquartered in Cary, North Carolina and has offices in California’s Silicon Valley, Waltham, Massachusetts, and Paris, France. More information is available at http://www.coventor.com.


  • CTO Interview with Dr. Wim Schoenmaker of Magwel

    CTO Interview with Dr. Wim Schoenmaker of Magwel
    by Daniel Payne on 12-09-2014 at 7:00 pm

    I visited the Magwel booth at DAC in June and chatted with Dundar Dumlugol the CEO about their EDA tools that enable 3D co-simulation and extraction. Since then I’ve made contact with their CTO, Dr. Wim Schoenmaker to better understand what it’s like to start up and run an EDA company. Magwel’s history goes back to 2003 when Wim Schoenmaker and Peter Meuris founded the company based on their research work at IMEC to analyze and simulate the entire layer stack of a semiconductor structure.


    Wim Schoenmaker, Ph.D.

    Related: EDA for Power Management ICs at DAC

    Q&A

    Q: Why did you start Magwel and what challenges were you trying to solve?

    Around 2000 at IMEC I was involved in characterization of on-chip passive structures and it was not clear (in those days) what the impact of semiconductor junctions might have on the quality factors of integrated passives. Partial solutions existed in which the semiconducting regions were replaced by metals with high permittivity and moderate conductance or insulating regions. During the last three decades (1970-2000) technology CAD or TCAD being the discipline to model semiconductor processes and devices became a mature field. The situation at that time was that there existed two worlds of modeling: the TCAD world for devices (and processes) and the Maxwell field solvers world that originally was an out spin of accelerator and wave guide design. My ambition was to set up a merge between both views. I decided to rethink the TCAD device modeling approach from scratch but this time to include the full electromagnetic picture and not merely the electric-only view. Being the TCAD team leader at IMEC and having a background in lattice gauge theories I was well equipped to take on such a job.

    Moreover, resolving the problem of on-chip passives was strongly supported by several leading persons at IMEC such that seed funding could be accessed to start MAGWEL.

    Q: What do you like best about being a CTO?

    Being a CTO at an SME (Small or Medium Enterprise) of the scale of MAGWEL, the meaning of this title is more a formality than a manual for filling daily activities. In practice I am still very much involved in the actual development of our products and this is the kind of work I enjoy the most. A serious part of my activity goes into setting up collaborative research and development projects. These projects serve as stepping stones towards mature products. For example, we have currently running EU funded FP7 project to explore novel routes to extract SPICE and Spectre compatible models for electron charge and heat transport. This project also addresses uncertainty quantification (variability).

    The common denominator of such projects is that advanced research results in the mathematical and computer science community are applied in microelectronic engineering. More recently, together with ON Semiconductorwe are cooperating in a research project on ESD network verification, funded by the national institute of science and technology (IWT). In general, my job is to perform feasibility studies of novel approaches to deal with yet unsolved design challenges. In general, such exploratory activities consume budget that is not recovered in a short term by product sales and therefore these funding channels must be tapped. This requires writing convincing
    and well structured research proposals, for which I am the key responsible.

    Q: What trends in semiconductor design and EDA are you most concerned about these days?

    Over the last years I have witnessed a decline of generic in-house scientific expertise within the large-scale IDMs. I mean, nowadays there is less room for research by looking over the fence. The clear cut between core business and the scientific developments that take place in neighboring fields has become sharper. There is an outsourcing of tool development and the consequence is that SMEs will take over the job to enter into unknown territory of adapting novel developments asillustrated above. It is not really a concern since it opens possibilities. Needless to say that a substantial risk is involved since not all ideas turn out to work as nice as one could forecast at start. Nevertheless, over the years one develops a six sense for what may have a good change to succeed and what is doomed to fail.

    Q: What kind of advise would you give to someone starting up a technology company today?

    This is a hard one.

    First of all, convince yourself that you have a product that is really different from what is already out there and that the product deserves to be put in the market. If you are not really enthusiastic about it, nobody else will be. It may turn out that you are the only one that is enthusiastic, so be it. The next advice is to be prepared for good times as well as bad times.

    The worst motivation to start a technology company is the ambition to become rich overnight. Next, of course, it is crucial to listen to the customers. They should tell you what is important and needed. Do not take the attitude to tell customers what they should need.

    Q: What is your best accomplishment at Magwel so far?

    One of my qualities is probably ‘persistence’. I keep on hammering on a problem until it crumbles and a solution is found. With STmicroelectronicswe have developed a version of our electromagnetic TCAD solver in the transient regime. (The results were published in IEEE Transaction on CAD and IEEE Transactions on Electron Devices in June 2014). It was applied to deal with fast transient and high current surges in ESD protection devices. I completed the inclusion of Lorentz force effects in the solver at ST’s request. The results were the cherry on the pie of many years of research. The permanent confrontation with measurement results were deterministic for the quality of the tool. This is the guideline of all our products. We are not satisfied if our products match outcomes of other simulation tools. The true comparison is by matching Silicon data.

    Q: Why is it that start-ups tend to have more innovation than the big three in EDA?

    I think it intrinsic to the EDA business: start-ups are like evolutionary experiments in nature: some species survive and others perish. When they do survive and turn out to be valuable, there comes a big load of marketing costs and sales costs with it. Such costs have not much to do with the intrinsic technology and it is a better business model to share these costs. Here come the big three into the picture. It is a matter of efficiency to distribute the marketing, sales and other costs over a large product folio.

    Related: Ensuring ESD Integrity

    Q: How do the advances in foundry processes create new challenges for Magwel?

    Processes get more complex and down-scaling makes devices more vulnerable. Therefore, physical mechanisms that were harmless on coarse devices and layouts can be deteriorating at down-scaled devices. As a consequence, rule-based designs must be replaced by physical designs taking into account more subtle aspects of the underlying physics. Building simulation tools that are capable of doing so is a challenge, especially if you want to apply it to the big layouts. New foundry processes are a blessing for MAGWEL since they trigger the need for our products. MAGWEL is rooted in the physical approach of design problems.

    Looking back we can say that sometimes it was an overkill by incorporating too much physics but we learned important lessons. There is a healthy friction between accuracy (the physics approach to understand what is going on) and efficiency (the engineering approach to make things work). Our product development team is a mixture of engineers, physicists and computer scientists complemented with collaboration with mathematicians leading to the best results.

    Q: What will success look like at Magwel in twelve months?

    This year (2014) turns out to be very successful in terms of growth of revenue thanks to product sales. We have new products coming up that are now in development with core partners such as SPX, our product for extracting substrate parasitic Bipolar transistors.SPX is a unique tool that can simulate and extract substrate parasitic Bipolars at the chip level, which is a quantum leap over what TCAD tools can do. Our ESDitool which includes the modeling of the highly non-linear response of protection devices clearly fills a need. Our product PTM-ET, the power transistor modeler with electro-thermal transient simulations will be upgraded in the next release to deal with much larger (full) chip heat capabilities. Our electromagnetic TCAD solver, which was originally developed in the frequency regime is now also available in the transient regime to simulate ultra-fast large signals.

    My expectations are high for next year in terms of increase of revenue and additional hiring to realize the developments that are requested by our customers. We expect a growth of over 50% in 2014, following a 55% growth in 2013. Magwel has entered an accelerating growth phase thanks to the success of its products in the marketplace.

     


    SPX: Substrate Parasitic Bipolar Extraction, chip-level 3D substrate noise integrity analysis

    Related: Electro-Thermal Simulation of Power Transistors

    Also Read:

    IROC Technologies CEO on Semiconductor Reliability

    CEO Interview: Jens Andersen of Invarian

    CEO Interview: Jason Xing of ICScape Inc.


    Synthesizing rad-tolerant RTL for FPGAs

    Synthesizing rad-tolerant RTL for FPGAs
    by Don Dingee on 12-09-2014 at 4:00 pm

    The maiden voyage of NASA’s Orion spacecraft brought a raft of articles about how the flight computer inside is “no smarter than your phone,” running on wheezing IBM PowerPC 750FX processors. NASA’s deputy manager for Orion avionics, Matt Lemke, admits the configuration is already obsolete – at least in commercial terms. Continue reading “Synthesizing rad-tolerant RTL for FPGAs”


    What Will Drive Smartphone Market Now?

    What Will Drive Smartphone Market Now?
    by Pawan Fangaria on 12-09-2014 at 7:00 am

    Whenever a market matures, either it gets plagued by substitutes or it looks for complementary products or technologies which can fuel its maturation curve into further growth opportunities. While PCs and Notebooks got substituted by smartphones, there is no other device in foresight to substitute smartphones. The reason is smartphones have inherited many functions from other devices including communication, computing and consumer applications. Communication and computing being two powerful functions ‘on the go’ have provided huge boost to smartphones in the hands of consumer which has attracted other applications to get into smartphones. Now smartphones are ready to further displace other devices such as remote controls for TVs, ACs, and Cars and so on. People are tired of having so many remote control devices; they would prefer to use just their smartphones from anywhere they like!

    Guess, what will drive smartphones to take control of their own destiny – it’s IoT. IoT will enable smartphones to control all other devices in consumer, home, personal, security, automotive, healthcare and other spaces.

    IC Insights is correctly predicting cellphones to be the largest driver for IC sales; and wireless and IoT to exhibit the fastest growth for next five years.

    In its reportfor 2013-2018, IC Insights predicts strongest IC sales growth in subsystems for IoT and wireless networks; while IoT is expected to grow at CAGR of 22.3%, wireless ICs can grow at CAGR of 19.7%. Similarly, the systems sales associated with IoT are expected to rise at the fastest CAGR of 21.1% (in another graph). And cellphone ICs will continue to top the IC sales share at $70.7B.

    This foresighted trend is being reflected in the strategies of leading semiconductor companies. Last week, I was studying about Samsung’s plans after major fall in their profit from phone business. Samsung is putting major emphasis on IoT which will stitch together most of their other businesses and generate benefits across their product lines – Smartphones, TVs, computers, watches, cameras, fridges, washers and dryers and so on.

    Lee Jae Yong of Samsung has established collaboration with Intelto develop and strengthen its own operating system, Tizen; joined Thread Group, led by Google’s Nest Labsto build home automation; and signed global patent licensing agreement with Ciscoto strengthen connected devices systems. They acquired SmartThings who specializes in developing mobile applications that remotely control household devices.

    Samsung has massive plans to setup chip manufacturing for wearable and connected devices. They have already setup a large Innovation Museum (in a five storied, glass walled building) that signifies smart living and inspiring. There are booths to demonstrate connected life in hotels, shopping malls, offices, living rooms in homes, airplanes and so on. And everything is controlled through your Smartphone; for example, you can check-in into the hotel by pressing a key on your Smartphone without waiting in the queue, warm your oven or clean your room before coming home, check all security and condition of your home even after leaving from there, all from your Smartphone.

    Samsung is not alone; Qualcommhas low power wi-fi platform that connects major home appliances to the network; IntelQuark plans SoCs that are smaller and low power than atom to support IoT; Applehas HomeKit and HealthKit; Google Nest provides thermostats and smoke detectors that can be managed through smartphones. GEforays into industrial internet with portfolio including equipments, internet-linked sensors and software to monitor and control performance. Cisco provides network convergence system that enables fabric suitable for IoT.

    Next era will be for IoT enabled smartphones; IoT will drive Smartphone market into a new growth trajectory and retain the fortunes of these phone and wireless companies as well as those which enable smart things to be done through IoT and smartphones. Comments welcome!

    More Articles by PawanFangaria…..


    A brief history of the Internet of Things

    A brief history of the Internet of Things
    by Majeed Ahmad on 12-08-2014 at 2:00 pm

    The Internet of Things (IoT) is apparently the next big thing, but it tends to appear in different ways to different people. To some it’s all about connectivity of the web of devices and to other it’s synonymous with sensors and wearable devices. And the scope of IoT is expanding by the day—to smart lighting, smart thermostats, smart homes, and smart buildings. Even cameras and cars are increasingly being seen under the IoT fold.

    To understand the larger concept, and get clarity on the IoT bandwagon, it’d be worthwhile to take a brief history detour. Where are the technology origins? What was it initially aimed for? How the concept evolved over the years?

    The vision thing

    The Internet of Things was not a new idea. In 1988, Mark Weiser, a technologist at the Computer Science Lab of Xerox Palo Alto Research Center (PARC), put forward the notion of ubiquitous computing as information technology’s next wave after mainframe and personal computers. In this new world, what he called “calm technology” would reside around us, interacting with users in natural ways to anticipate their needs.

    Weiser coined the term “ubiquitous computing” to describe a future in which personal computers would be replaced with invisible computers embedded in everyday objects. He believed that this would lead to an era of computing in which technology, rather than panicking people, would help them focus on what was really important.

    Weiser’s work—based on research on human-computer interaction and PARC’s earlier work on computing—initially sparked efforts in areas such as mobile tablets and software agents. Subsequently, these efforts morphed into pursuing intelligent buildings packed with wireless sensor networks and displays, where information follows wherever people go. Weiser’s vision was shared by many in the PC industry.


    Mark Weiser

    The first practical manifestation of ubiquitous computing emerged in the early 1990s when John Doerr, the legendary venture capitalist at Kleiner Perkins Caufield & Byer, started the pen-computing frenzy by funding Go Corp. By 1991, the pen-based computing wave had become the “next big thing” in technology world. Yet, despite this pen-based computing rush, only a single product became commercially available from GRiD Systems, a small computer outfit on the east of the San Francisco Bay.

    But then Apple Computer’s chief executive officer, John Scully, fanned the flames of pen-based computing in a speech about a handheld computer he called the personal digital assistant or PDA. “Palmtop computing devices will be as ubiquitous as calculators by the end of this decade,” he told his audience. Scully echoed Weiser’s vision touting that computing would eventually go a step farther in the journey that started from mainframe to minicomputer to personal computer. In May 1992, Apple CEO announced the Newton, an amazingly ambitious handheld computer. Scully set the computer world on fire with his prediction that PDAs such as Apple’s Newton would soon contribute a trillion-dollar market. He professed that this gadget would launch the “mother of all markets.”

    Newton failed to connect with the rest of the computing world, and five years after its launch, the newly arrived chief executive Steve Jobs abandoned the product to focus on Apple’s core Macintosh lineup. But the Newton debacle proved a kind of start-over that led to a new generation of PDAs that would focus on more practical features. A plethora of such products sprang up—offering some sort of interactive capability—and among them was Palm Pilot, a simple, no-frills compact device which hit the market in February 1996. Palm Pilot became one of the fastest-selling high-tech toys of the decade. The elegant little computer became an American icon; one million Palm Pilots were sold in the first eighteen months.

    The rise of the machines

    Next up, the cellular-centric machine-to-machine (M2M) communications industry emerged in 1995 when Siemens set up a dedicated department inside its mobile phones business unit to develop and launch a GSM data module called M1. It was based on the Siemens mobile phone S6 for M2M industrial applications and enabled machines to communicate over wireless networks.


    Siemens’ M1 module was used by Adshel to transmit data wirelessly via a GSM network

    Among these network-centric innovations, the most prominent early contributions came from mobile phone companies who had been using their 2G and 3G networks to connect everything from juke boxes to ice machines since the late 1990s. The use of the mobile technology as a payment gateway had started in Helsinki in 1997 when a company owned by Coca-Cola installed two mobile-optimized vending machines. These machines accepted payment via text messages.

    The companies like General Motors and Hughes Electronics were also among the early implementers of the M2M technology.

    What’s in the name?

    PDAs and M2M continued their slow and modest journey toward gaining interactivity and getting assimilated into the network. Meanwhile, a British technologist Kevin Ashton became interested in incorporating radio frequency identification (RFID) chips into products with smaller form factors while he was working as an assistant brand manager at Procter & Gamble in 1997.

    After a couple of years’ of work, he proposed using RFID chips to help manage P&G’s supply chain problems. He argued in an article that having humans input data was incredibly clumsy and inefficient. On the other hand, semiconductor chips and sensors were becoming smaller, cheaper and less power hungry, so they could be incorporated into just about anything.

    Ashton suggested that getting information from objects themselves could revolutionize the supply chain. The “Internet of Things” was born. The use of an RFID chip within a miniature device connected wirelessly was akin to a simple SIM card, and it expanded the reach of the Internet of Things to healthcare, automobile, energy, and more.


    Kevin Ashton

    Vision becomes reality

    In 2000, LG Electronics announced plans to launch the first Internet refrigerator. Later, in 2005, the notion of theInternet of Things got official recognition from the communications world when the International Telecommunications Union (ITU) published its first report on this emerging industry discipline.

    The report acknowledged, “A new dimension has been added to the world of information and communication technologies (ICTs): from anytime, anyplace connectivity for anyone, we will now have connectivity for anything. Connections will multiply and create an entirely new dynamic network of networks—an Internet of Things.”

    In the 1990s, the concept of remotely monitoring and controlling distributed assets and devices a.k.a. the Internet of Things was mostly reserved for large and expensive investments like power plants and dams. Fast forward to 2013, connected products are expanding to e-books, cars, home appliances, smart grids, manufacturing, fast food, security, healthcare, and more. By 2020, billions of things—from clothes to cars and from body sensors to tracking tags—are forecast to be part of the Internet of Things bandwagon.

    Image credit: Xerox PARC and Slideshare.net

    The content of this article is based on the excerpts from The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future. The article was originally written for The Smartrphone World.


    TSMC Bringing EUV Into Production

    TSMC Bringing EUV Into Production
    by Paul McLellan on 12-08-2014 at 7:00 am

    Last week was ASML’s investor day. I wasn’t there and they haven’t yet got the material posted on their website, so this is all second hand information. As you know, if you have read any of my comments on EUV, I have been dubious about whether EUV would ever work for production.

    The three big problems seem to be:

    • source power and photoresist sensitivity
    • cleaning masks and/or pellicles
    • lack of defect free masks

    I have heard other issues too, such as line-edge-roughness, but these seem more like the regular HVM ramp issues that greadually get fixed just by running a lot of wafers.


    ASML announced that TSMC has ordered two more EUV scanners. They already have two and they will be upgraded with the new light sources. These are apparently on course to achieving 120W of output early next year and so can support 1000 wafers per day throughput (currently it is 80W and around 500 wafers per day). They claim 1500 in 2016 but schedules for anything to do with EUV have been notoriously unreliable.

    They said that TSMC will be using these for 10nm production. I don’t think TSMC is going to try and introduce EUV at the same time as a new process node (nor 450mm if that ever happens). The initial PDKs for 10nm are already out and they involve multiple patterning. So I presume TSMC will actually introduce EUV for 16nm (probably not for production), do the HVM ramp for 10nm and then brings EUV in as an option there. Intel, by the way, have said they will not use EUV at 10nm.

    In fact ASML’s CEO Peter Wennink conirmed this:We are working with a customer[presumably TSMC] towards a mid-node insertion of EUV at the 10nm logic node expected in late 2016. Other customers are preparing for initial learning in a manufacturing environment.


    The next big problem has been mask contamination. The masks for EUV are reflective mirrors (actually not even all that reflective, ordinary mirrors absorb EUV just like almost anything). Without a pellicle, a thin covering for the mask, any contamination on the mask is in the focal plane and will print (see the above diagram). So masks need to be cleaned but there are a limited number of times a mask can be cleaned before the pattern starts to degrade. Intel has already said that they don’t see how to use EUV for volume manufacturing without a pellicle.


    The challenge with a pellicle is that any material absorbs EUV with pSi being the best material by far. ASML said that they will manufacture pellicles too, so presumably striking that problem off the list.


    I don’t know if progress has been made on the mask defect issue. The masks (and the mirrors in the optical path) are actually built up with multiple layers of Mo/Si. One of the challenges is that defects on the base layer can be too small to see with optical inspection (plus the size makes it equivalent to searching for a golfball in the whole of California). However, when the multi-layer mirror is build up the defect gets magnified to the point that it will print. There has been some work done on aligning the pattern on the mask so the defects are under the pattern, so irrelevant, but I’ve not seen anything about it recently. Anyway, I think mask inspection and mitigation are still an open issue.


    More articles by Paul McLellan…


    Xilinx the EDA Company

    Xilinx the EDA Company
    by Luke Miller on 12-07-2014 at 7:00 pm

    Like you I cannot believe 2015 is upon us. 15 years ago I remember the Y2K panic. I remember watching the news and noticed the liberal media (they were liberal back then too) just waiting for the first fail somewhere. Ended up like Geraldo at the opening of Al Capone’s Vault. Remember that one? As I persist on with this word salad may I be the first to wish you a Merry Christmas?

    I just witnessed again, Uncle Billy giving the 8 grand to Mr. Potter (It’s a Wonderful Life), drives me nuts every time. I better write something techy here, I’m losing you. Happy New Year as well!

    In 2014, Xilinx quietly solidified its global lead for the next decade by finalizing what I would call a morph from a fabless FPGA company, to a fabless SoC + EDA company. Did you catch that morph? It has been an ongoing execution since Moshe became CEO of Xilinx in 2008. Moshe took the helm of a great company with the challenge of making Xilinx even greater. Having an EDA background (which Moshe had coming from Cadence) did not hurt.

    Not by chance but by Xilinx strategy they acquired AutoESL (which developed a tool called Autopilot; the 1[SUP]st[/SUP] ‘C to gates’ tool that worked great in my opinion). Xilinx rolled AutoPilot into Vivado calling it Vivado HLS. I keep banging this drum but here is where an FPGA could ‘really’ be programmed using C/C++. The figure below is not marketing propaganda but reality. Xilinx had the foresight that a programming model beyond RTL would be needed.

    While all this is going on Xilinx ISE circa 1995 (plus many updates along the years) was not going to get a face lift but a morph as well (or burial of sorts). It started by throwing the ISE Place and Router (P&R) away and designing a new one from scratch just like grandma did. There was just no way simulated annealing was going to yield reliable P&R times nor efficient FPGA usage with 4M+ Logic Cells in view. Vivado was born using analytic place and route which yields this fantastic before and after as shown below.

    Speaking of another birth, the Millers are expecting another in March 2015, of the male kind. For earned value I have already taken credit for the birth in the FYI 2014. For those of you counting this will be Child number 8, Lord willing.

    2015 will be the year of ‘16’, nanometer that is. But more than that, Xilinx recently announced ‘SDAccel’:

    · First Architecturally Optimizing Compiler for OpenCL, C, and C++
    · First Complete CPU/GPU Like Development Experience on FPGAs
    · First Complete CPU/GPU Like Run-time Experience on FPGAs

    This video does a great job on explaining what SDAccel is all about.

    Xilinx brought to the world the first ARM SoC FPGA named Zynq. Software engineers once alienated from FPGAs found themselves where hardware engineers lived, except from a different view. This is the grand unification of Xilinx FPGAs into all systems, and I mean all. SDAccel is not just another ‘tool’ in the ‘tool box’ but the very fabric that will allow Xilinx FPGAs to live in data centers, IoT, Military Systems and where CPUs/GPUs are embedded but no longer are affordable options. The table below from theLinley Group does a great job highlighting the Xilinx SDAccel significant advantages. Like I said in July, RIP CPU.

    The C/C++, OpenCL programming model for FPGAs is here to stay and Xilinx has the edge not only in silicon but with tools as well. Wait ’til you see 2015 from Xilinx…. I cannot wait!


    eSilicon’s IP Marketplace

    eSilicon’s IP Marketplace
    by Paul McLellan on 12-07-2014 at 9:00 am

    eSilicon engages with customers in many different ways, from providing a full menu of design services down to simply manufacturing parts. Increasingly, they have been automating a lot of this on their website. It started with automatic quotes for MPW shuttles and more recently they have a full production quote system for parts that will be manufactured by TSMC. Presumably more foundries will come.

    See Getting a Quote Without Talking to a Salesman

    eSilicon also provide IP, primarily memories and specialized I/Os. They have two development groups in Vietnam (in Ho Chi Minh City and Da Nang) where most of this work is done. They have now started to put their IP portfolio online too, allowing customers to serve themselves. This first version of what they have named IP Marketplace is available now, allows you to try IP before you buy it, and the second version which should be available in March next year, will also allow the actual procurement to be done online too.


    The current version allows you to find out power, performance and area (PPA) for any item of IP. This can be displayed graphically, in a table, or downloaded to Excel. The system supports all eSilicon developed IP (in the future 3rd party IP will also be available) including memory compilers, standard and specialty I/Os and across multiple foundries, currently TSMC, GlobalFoundries, Dongbu and LFoundry at a range of different process nodes. You only need to pay for the IP when the chip tapes out.


    The marketplace makes it easy to compare PPA across different potential process nodes at different foundries, and also try different configurations of memories at different operating points (PVT). See the diagram above. You can download a complete chip memory subsystem for free, giving you the full capability to “try before you buy” and without needing to have eSilicon personnel in the loop slowing the process down. But it is not just the specification data that is free to download, you can get all the front-end views to actually do the design (or do an even more detailed analysis). You purchase the layout (GDS II) only when you are ready to tapeout and, of course, only for the IP blocks that you actually ended up using.

    If you are using TSMC, you can now get all the IP you need and get a legally binding prototype and production quote, all online. All you have to do is actually design the chip!

    eSilicon’s IP Marketplace page is here, where you can find out more, login or create a new account.


    More articles by Paul McLellan…


    TSMC Sees More Growth in 2015!

    TSMC Sees More Growth in 2015!
    by Daniel Nenni on 12-06-2014 at 8:00 pm

    As I wait for my plane to Taiwan I’m wondering what the New Year has in store for the fabless semiconductor ecosystem. Good things I hope but to make sure let’s take another look at one of my trusted economic bellwethers (TSMC) which I’m guessing will break the $25B revenue mark this year. That is more than a 25% growth rate year over year. What an amazing road this company has paved for us!

    Here are some interesting snippets from the TSMC 14th Annual Supply Chain Management Forum held in Hschinsu last week:

    • Next year the global semiconductor industry will grow 4%-5%
    • We do not foresee any unusual inventory supply chain adjustment
    • The global foundry industry is expected to expand 12% in revenue next year from this year
    • TSMC’s foundry market share will rise to 53% of the global market this year, compared with 49% last year
    • 20 nanometer chips will account for 20% of the firm’s total revenue this quarter
    • Revenue from 20nm chips should be more than double next year
    • TSMC is scheduled to begin pilot production of its advanced 10nm technology in Q4 2014 and to ramp up production at the end of 2016
    • Manufacturing capacity will increase by 12% from last year, with total annual capacity expected to reach 8.2 million 12-inch equivalent wafers in 2014

    “TSMC’s success comes from collaborating with our customers and suppliers through our Grand Alliance so that we magnify each others’ innovations and stand together as a most powerful competitive force in the semiconductor industry,” said TSMC Co-Chief Executive Officer Dr. Mark Liu. “Our supplier partners are a critical part of this alliance, and we look forward to reaping the rewards of many years of strong growth together.”

    The Outstanding Contribution Award went to Applied Materials for EPI/PVD Equipment and Local Service. From what I heard this is in direct response to the success of the 16FF+ process but more on that later.

    One of the things I have enjoyed over the years is the candid nature of Morris Chang’s comments. Even on the quarterly conference calls which are usually scripted. So far I have experienced the same from heir apparent Mark Lui. Take a look at Mark’s resume on the TSMC website:

    Dr. Mark Liu is currently President and Co-Chief Executive Officer at Taiwan Semiconductor Manufacturing Company (TSMC). Prior to this, he was Co-Chief Operating Officer from March 2012 to November 2013. Before that, he was Senior Vice President of Operations from 2009 to 2012. From 2006 to 2009, he was a Senior Vice President responsible for the Advanced Technology Business at TSMC. From 1999 to 2000, he was the President of Worldwide Semiconductor Manufacturing Company.

    Prior to joining TSMC, from 1987 to 1993, he was with AT&T Bell Laboratory, Holmdel, NJ, as a research manager for the High Speed Electronics Research Laboratory, working on optical fiber communication systems. From 1983 to 1987, he was a process integration manager of CMOS technology development at Intel Corporation, Santa Clara, CA, developing silicon process technologies for Intel microprocessor.

    Ph.D., Electrical Engineering and Computer Science, University of California, Berkeley

    Some people say filling the shoes of Morris Chang will be difficult but I do not see a problem here. I would hold Mark’s credentials up against any other CEO in the semiconductor industry, absolutely.

    Also Read: Intel is NOT Quitting Mobile!