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December 6, 2014

Which IP for FD-SOI Ecosystem?

Which IP for FD-SOI Ecosystem?
by Eric Esteve on 12-06-2014 at 3:00 pm
Categories: FD-SOI, Foundries, STMicroelectronics

We know that the best technology or product, even if it exhibits best in class and unmatched features, is almost of no use if lacking an ecosystem. If you think about a processor core, you will expect to find compatible communication bus and memories (inside the SoC) and operating system, compiler, debugger, etc. When dealing with a disruptive ASIC technology like FD-SOI, you will expect to have multiple sources for raw SOI wafers, at least double sourcing capability for processing these wafers and, last but not least, a solid IP ecosystem. If you can’t decree the creation of this IP ecosystem, you (the foundry or ASIC vendor) can certainly invest resource to internally develop the foundation IP (standard cell library or memory compiler). Your involvement in supporting or initiating the development of complexes IP by the best in class IP vendors will make the difference too.

Taking a look at this FD-SOI roadmap, extracted from the presentation made by Patrick Blouet from ST during IP-SoC “Which IP from FDSOI Ecosystem”, give you an idea of the additional features and related IP to be added to the current offer at 28nm FDSOI. Today the status is that you can design a complete digital SoC (for example an Application Processor), including high performance CPU and GPU (from ARM or Imagination Technologies), internal memories for cache, DDR4 memory controller (from Cadence) and the various IP to support interface protocols like USB, HDMI, MIPI and probably more.

The 28nm roadmap feature path gives you some interesting indication too. If RF IP can be available on the same IC to support WiFi, Smart BT or WigBee as well as some advanced mixed-signal function, you are close to build a dedicated IoT chip supporting smart watch or metering application. Then the designer could take full advantage of the power efficiency inherent to FD-SOI technology, and release to the IoT market an application offering strong differentiators in term of cost (monochip solution) and power consumption, thanks to FDSOI. On the below picture, ST claims for a power consumption improvement better than 3X between 40LP and 28 FDSOI.

This example of a SoC integrating RF and mixed-signal illustrate an IoT application, but a building a complete IP ecosystem will require to port many existing functions to FDSOI. At SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration, for example from 45nm to 40nm. In other words, it brings very worthwhile benefits at reasonable efforts. A typical approach could be:

CPU and GPU: the main objective is maximum peak performance and the design is re-worked, making the most of Forward Body Bias (FBB);
Other SOC blocks: the main objective is power savings, by reaching the target operating frequencies at lower Vdd; there is no change to block design, Timing Analysis is re-run and ECO (Engineering Change Order) is performed to fix violations if needed.
Other IP such as IOs and PHY blocks are swapped for their planar FD counterpart.

During the presentation at IP-SoC, Patrick Blouet has unveiled THINGS2DO, the program supporting the FDSOI ecosystem creation:

The partners rank from Silicon suppliers, tools providers, IP & Design Houses, System integrators and research organizations. Developing IP supporting FD-SOI is a business driven decision, and we know that the more IP will be available, the higher will be the number of FD-SOI ASIC design-win. “Somebody“ has to initiate this virtuous cycle, and ST has decided to do it with THINGS2DO initiative. This decision is certainly the best THING to do at the moment, like giving a kick to start a motor, the market following when the business will become attractive enough. Because Samsung and Global Foundries are also in the loop, we have no doubt that this IP ecosystem will grow…

From Eric Esteve from IPNEST

December 6, 2014July 18, 2025

Synopsys Q4 Earnings

Synopsys Q4 Earnings
by Paul McLellan on 12-06-2014 at 11:02 am
Categories: EDA, Synopsys

Synopsys announced their earnings a couple of days ago. This is actually also the end of their fiscal year. They had quarterly earnings of $539M meaning that they did just over $2B for the year. Their guidance for fiscal 2015 is revenue between $2.185B to $2.225B. They said that about 80% of that revenue is already in backlog.

But it is some of the color that I think is more interesting if you are looking at the whole industry and not just trying to decide if Synopsys stock is going up or down. For example, Aart said that they have 170 active FinFET designs and tapeouts all the way down to 10nm. Designs in more mature nodes such as 20nm, 28nm and 40/45nm are increasing in complexity since many designs don’t need the absolute most advanced node and the cost of these older nodes seems to be lower.

Aart went on to put Synopsys strategy down explicitly. The headline is to continue to invest in EDA but also broaden the product portfolio to address a more diversified set of customers.

Priority number 1: Maintain clear technical, business and support leadership in core EDA. This will mostly be through organic growth, rather than acquisitions. Synopsys introduced several major developments this year such as verification compiler and IC Compiler II, and there are more to come in 2015.

Priority number 2: Drive continued growth in IP and Systems, leveraging the confluence of increased outsourcing of IP, growing technical complexity, and the essential customer need for trust and reliance on its partner suppliers. Synopsys is already the #2 supplier in IP (ARM is #1) and the trend towards design being a combination of IP assembly and software has them in a good spot.

Priority number 3: Expand our presence in the software-quality, test and security space by building on the excellent technology from Coverity. This is a two-pronged strategy, firstly selling software quality products into the software groups associated with chip designs, where obviously Synopsys is already engaged. But also sell into:the large untapped software-applications market that reaches from financial to health, energy, retail, social media to virtually any company doing sophisticated software and having quality, security and testing issues.

Core EDA is relatively slow growing (“single digit”), despite the huge investment required to create leading edge tools that keep up with the process node transitions. Like the queen in Alice Through The Looking Glass, it takes all the running you can do to stay in the same place. Or as Aart put it in the Q&A:So, one hand same old, same old. On the other hand, same old has always meant very rapid progress.

IP is growing faster (“double digit”) and getting increasingly profitable. In Q4 Synopsys closed a multi-year agreement for 16, 14 and 10nm IP outsourcing with AMD and hired 150 of their engineers into their IP team. They already have some 10nm IP wins.

The Coverity space is a huge new market. About half of Coverity’s business is in embedded software but the other half are in pure application software markets. Coverity should be breakeven by middle of 2015 with revenues of over $100M in 2016.

This was Brian Beattie’s last call as CFO since he has been promoted to run all the adminstrative operations of Synopsys, including IT, HR and strategy. Trac Pham is the new CFO.

In the Q&A Synopsys was asked about their largest customer since they hadn’t said it was over 10% as they usually do. Everyone knows the customer has to be Intel although nobody is allowed to say that word. And it was just over 10% as usual.

Variation at IEDM

Variation at IEDM
by Paul McLellan on 12-05-2014 at 7:01 am
Categories: Coventor, EDA

IEDM (technically the International Electron Devices Meeting although I’ve never heard anyone use the full name) is in a couple of weeks time, in San Francisco. It is December 15-17th at the Hilton Union Square (which is not actually at Union Square but nearby at 333 O’Farrell Street).

For the last few years on the Tuesday evening Coventor have sponsored an event (with appetizers and drinks). Last year it was all about collaboration. This year the topic is variation, Survivor, Variation in the 3D Era. It is at the Hotel Nikko from 5.30pm to 8.30pm on Tuesday December 16th in the Carmel Room. Hotel Nikko is 222 Mason Street just around the corner from the Hilton.

The format is a panel session moderated by our very own superstar Dan Nenni, who will be just back from Taiwan surrounded by his fan-club of hot Chinese babes and senior foundry executives. Or not.

I talked to David Fried today to get a little more background. The panel consists of:

David Fried himself, who is Coventor’s CTO
Rich Wise who is now at Lam Research after years as a distinguished engineer at IBM
Jeff Smith of TEL America, who is a guru on etch development
Tom Brozak of PDF Solutions who is a fellow there
Jan Hoentschel of GlobalFoundries where he is responsible for 28nm in Dresden, Germany
Tom Dillinger of Oracle (think Sun) where he is responsible for a lot of desigh methodology development

The slogan of the session is taken from Survivor, but instead of being Outwit, Outplay, Outlast it is Reduce, Contain, Understand. Or as the Coventor flyer says:It’s a jungle out there. The era of 3D semiconductors, 3D NAND Flash, FinFETS and unprecedented process complexity introduces new pitfalls for the cunning engineer to overcome. Find out how the best and the brightest are outwitting the competition with creative ways to navigate the treacherous landscape of advanced IC design and manufacturing. They know the key to survival in dealing with process variation is to … Reduce It. Contain It. Understand it.

There are two people from each segment. Lam Research and TEL America need to reduce variation. In the meantime Oracle and GlobalFoundries need to contain it. And Coventor and PDF Solutions to understand it. Or something like that, in reality, everyone needs to worry about all aspects of variation.

Even before double patterning, variation was becoming an issue, since it made the traditional approach of worst-casing timing ineffective. The worst case barely moved even though the typical case was much improved, so if the investment in new process technology was going to be worthwhile, a new approach was needed with increasing accuracy replacing the brute force approach of just assuming the worst. But now we have double patterning which means that for those layers there is even more variation since the two exposures are not (usually) self-aligned meaning that, for example, the sidewall capacitances of interconnect can vary a lot depending on how perfectly aligned the two exposures are. But also in a predictable way, if some capacitances are up then others are down.

Anyway, we will see what these experts have to say about it all in a couple of weeks. There is no requirement to register, you won’t get a name-badge, but if you want to go then tell Coventor (so they know how much beer and food they need). Just send an email to rsvp-to-coventor@coventor.com saying you will be there.

I will be. See you there!

Intel is NOT Quitting Mobile!

Intel is NOT Quitting Mobile!
by Daniel Nenni on 12-04-2014 at 9:00 pm
Categories: Foundries, Intel Foundry, Mobile

Judging from the presentation Hermann Eul did at NASDAQ this week Intel is still in mobile. This presentation was probably inked before Intel Mobile was folded into the PC Group however. The first clue is Hermann’s title was listed as “General Manager and Vice President, Mobile Communications Group” which he is no longer. Even so, I found the presentation to be very interesting and the positioning of Intel in mobile solid. But first let’s talk about Prof. Dr. Hermann Eul (I’m a big fan of his from the Infineon days so this comes with some bias).

If you look at the Intel website the executive hierarchy is:

[LIST=1]

Three in the Executive Office

Four Executive Vice Presidents

Eight Senior Vice Presidents

Twenty Nine Corporate Vice Presidents

Last November Intel announced a “new” mobile strategy which put Hermann Eul on the front page with the SoFIA family SoCs. Hermann joined Intel in 2011 when Infineon’s Wireless group was acquired (SoFIA is from Infineon). At first he was President and General Manager of the newly formed Intel Mobile which was responsible for developing wireless products for connected devices (phones and tablets).

IoT Financial Outlook

IoT Financial Outlook
by Tom Simon on 12-04-2014 at 7:00 am
Categories: IoT

As exciting as the Internet of Things (IoT) is, the question of how and which companies stand to make money in this market remains. From previous waves of internet markets we have seen surprising wins and epic loses. How is the IoT market shaping up? And what are the real business drivers? According to a Silicon Valley Bank analysis, it’s important to look at IoT company market segmentation, and also to look at the relative size of these companies.

There are three areas of advancement that are fueling the current generation of IoT. First off is the increasing affordability of MCU’s, wireless devices and other hardware needed. Second is the ability to power back-end analytics needed to properly harness the information collected at the edge of the IoT. Lastly, are the economies provided by increasing numbers of connected devices. Metcalf’s Law asserts that the value of a communications network increases as the square of the number of attached devices.

Each of the drivers however faces potential hurdles. At some point decreasing hardware costs flatten out. For instance older nodes are used for a lot of RF and IoT devices. They will not see big costs per function cost decreases due to Moore’s Law. Big data and cloud resources used for analytics may need to be updated to deal with ever larger amounts of edge data collected. Ambiguity exists concerning whether a lot of connected devices have the same effect as ‘users’ for the purposes of valuing a communications network. Also we see the need to harmonize LTE networks, and make sure that other connectivity is easy to set up, secure and deploy.

Additionally other risk factors for business growth are power sources, software architectures and the brute force cost of adding connectivity to our existing ‘things’.

But the real question the SVB report raises is where will the pull for IoT business come from. Many large companies have been promulgating use scenarios for their IoT products and services, but are not seeing return on their investment. At the same time smaller companies are making inroads into markets and seeing real growth. Their challenge of course is to scale their growth so it becomes significant. VC investors are looking closely at their IoT funding. The SVB report states that angel money is supporting many more start-ups than the available series A funds from VCs can support in the long term. This means there will be a pruning.

Even within the start-up segment, critical mass is necessary for financial success. Early stage IoT companies making over $10M are seeing better sales growth than others in their peer group. It takes a big investment to get an IoT company to a higher valuation. The SVB report shows that series D rounds are most likely to be Up-Rounds for IoT companies. C rounds are the most perilous with close to 40% of companies having decreased valuations. If investors can stomach on average of $30M so a company can get past series C, those companies will have a better chance of giving their investors a good return.

The most interesting information in the report showed which market segments within IoT are prospering. Not surprisingly the IoT enablement category is performing well, with good growth, but hindered by higher costs of goods sold (COGS) and operating expenses. This category includes the hardware and software that is used as a foundation for IoT products.

The healthcare market seems to be a made to order market segment for IoT. Despite long leads times for product certification and extra effort required to meet the security requirements, healthcare has a growing demographic and many drivers for growth. Improved care levels and lowered costs for all kinds of medical monitoring, both at home and in hospitals are a big win. There is a clear cut ROI benefit for IoT devices in this market. Presently lack of scale is holding some of these companies back, but increasing demand can remedy this.

The third market segment featured in the SVB report is energy. Once again we see a very strong ROI for utilities and consumers. And in a less tangible manner there is a large ROI for our planet. Most of us already have smart meters and can monitor our power usage with increased granularity and almost in real time. This has ripple effects that go beyond reduced bills, to things like lower capital infrastructure costs from optimizing power plant utilization. By monitoring and controlling power consuming devices consumers can take advantage of dynamic rate structures that help manage power grid efficiency. This is a great example of how the IoT has grown from a simple point to point connection to a multi node multi directional system that can provide big leverage. But it also will require all the elements listed above, such as big data, connectivity, and sophisticated edge technology in the form of MCUs and communications devices.

As the IoT matures many people will be looking to see where there is growth and potential for profit. The development of real high value use cases will be essential. As is the case with disruptive technology shifts the winners and losers will be hard to predict this early in the game. But investors have learned to proceed cautiously, so hopefully we will not see a bubble, but rather rational growth and expansion.

December 3, 2014

No IoT No Justice!

No IoT No Justice!
by Daniel Nenni on 12-03-2014 at 9:00 am
Categories: IoT

It looks like even President Obama is on the IoT bandwagon now with his $263M in matching funds for state and local police body cameras and training. It is a shame that it took a tragic event to spur this type of Government investment in semiconductor technology but I appreciate it just the same.

As I have mentioned before, when I read something I do my best to understand what the author is saying but also why they are saying it. After following the media frenzy surrounding the events in Ferguson, Missouri I’m having trouble understanding either one in this case. Was the media’s intent to pour gasoline on a fire causing millions of dollars of damage? One thing I can tell you, as a result of this event all sorts of video surveillance equipment containing our precious semiconductor devices will be flying off the shelves, absolutely.

If you read the Grand Jury transcripts and the autopsy (yes the autopsy report is public) the so called eyewitness reports and media accounts are seriously conflicting. In case you are interested there is a Wikipedia page which does a decent job of capturing everything I have read thus far:

http://en.wikipedia.org/wiki/Shooting_of_Michael_Brown

We will probably never know what really happened that day which is why we will all be wearing personal video systems in the not too distant future. I do have an opinion on WHY it happened however which I will share with you now.

In the words of Iron Mike Tyson, one of the most feared boxers of my time, “Everyone has a plan until they get punched in the mouth.” As a former fighter I know this by experience. Do you remember the second Evander Holyfield fight where Tyson bit off part of Holyfield’s ear? I can assure you that was not Mike’s “plan” before he was hit in the face repeatedly. I’m also confident it was not Officer Darren Wilson’s plan to shoot an unarmed man six or more times that fateful day but as reported he was also hit in the face.

From what I have read I agree with the Grand Jury about criminal charges not being brought against Officer Darren Wilson. I do however think he should have been fired immediately for his careless approach to this situation which also opens up civil action. This man is an experienced Police Officer with no previous complaints lodged against him for anything. He had also never used his service weapon in the line of duty. So I ask you, just what was his plan exactly confronting two men through his car window without backup?

Hearing the world’s take on American current events first hand is very interesting to me. I was in Europe during the 9/11 attacks and was amazed at the response from people around me. Some good, some bad, enlightening just the same. I also remember being in Japan when the remake of the Pearl Harbor movie was released. Now that was interesting. Since SemiWiki is an international community of semiconductor professionals I would be interested to hear your opinions on this tragic event in Ferguson, MO and what I have written here.

December 3, 2014

Getting up close and personal with symmetric session key exchange

Getting up close and personal with symmetric session key exchange
by Bill Boldt on 12-03-2014 at 2:00 am
Categories: Foundries

In today’s world, the three pillars of security are confidentiality, integrity (of the data), and authentication (i.e. “C.I.A.”). Fortunately, Atmel CryptoAuthentication crypto engines with secure key storage can be used in systems to provide all three of these.

Focusing on the confidentiality pillar, in a symmetric system it is advantageous to have the encryption and decryption key shared on each side go through a change for every encryption/decryption session. This process, which is called symmetric session key exchange, helps to provide a higher level of security. Makes sense, right?

So, let’s look at how to use the capabilities of the ATSHA204A CryptoAuthentication device to create exactly such a changing cryptographic key. The way a key can be changed with each session is by the use of a new (and unique) random number for each session that gets hashed with a stored secret key (number 1 in the diagram below). While the stored key in the ATSHA204A devices never changes, the key used in each session (the session key) does. Meaning, no two sessions are alike by definition.

The video below will walk you through the steps, or you can simply look at the diagram which breaks down the process.

http://www.youtube.com/watch?v=_WNxFtI5A9E

The session key created by the hashing of the stored key and random number gets sent to the MCU (number 2) and used as the AES encryption key by the MCU to encrypt the data (number 3) using the AES algorithm. The encrypted data and the random number are then sent (number 4) to the other side.

Let’s explore a few more details before going on. The session key is a 32 byte Message Authentication Code or “MAC.” (A MAC is defined as a hash of a key and message.) 16 bytes of that 32 byte (256 bit) MAC becomes the AES session key that gets sent to the MCU to run the AES encryption algorithm over the data that is to be encrypted.

It is obvious why the encrypted code is sent, but why is the random number as well? That is the magic of this process. The random number is used to recreate the session key by running the random number through the same SHA-256 hashing algorithm together with the key stored on the decryption side’s ATSHA204A (number 5). Because this is a symmetric operation, the secret keys stored on both of the ATSHA204A devices are identical, so when the same random number is hashed with the same secret key using the same algorithm, the 32 byte digest that results will be exactly the same on the decrypting side and on the encrypting side. Just like on the encrypting side, only 16 bytes of that hash value (i.e. the MAC) are needed to represent the AES encryption/decryption key (number 6). At this point these 16 bytes can be used on the receiving side’s MCU to decrypt the message(number 7). And, that’s it!

Note how easy the ATSHA204A makes this process because it stores the key, generates the random number, and creates the digest. There’s a reason why we call it a crypto engine! It does the heavy cryptographic work, yet is simple to configure the SHA204A using Atmel’s wide range of tools.

http://www.youtube.com/watch?v=rGethCEF3C8

Not to mention, the devices are tiny, low-power, cost-effective, work with any micro, and most of all, store the keys in ultra-secure hardware for robust security. By offering easy-to-use, highly-secure hardware key storage crypto engines, it’s simple to see how Atmel has you covered.

Bill Boldt, Sr. Marketing Manager, Crypto Products Atmel Corporation

December 2, 2014

HLS – Major Improvement through Generations

HLS – Major Improvement through Generations
by Pawan Fangaria on 12-02-2014 at 6:30 pm
Categories: EDA

I am a believer of continuous improvement in anything we do; it’s pleasant to see rapid innovation in technology these days, especially in semiconductor space – technology, design, tools, methodologies… Imagine a 100K gates up to 1M gates design running at a few hundred MHz frequency and at technology node in the range of .18 to .35 microns in late 1990s and early 2000 when designers were struggling to optimize PPA and shorten design cycle time. Synopsys pioneered RTL to gate level synthesis which proved to be very successful. Today, with a billion gates SoC, operating at GHz frequencies, fabricated at cutting edge technology nodes, it is imperative one has to optimize PPA at system level. True, FinFET technology at 14nm provides excellent PPA, but that has huge cost and dynamic power implications. SoC verification cost has gone up tremendously. It’s time; we look at ways to optimize power and other critical success criteria at system level (not necessarily for FinFET nodes) and also reduce burgeoning design and verification cost including that of running huge regressions through large server farms.

I admire, people did have foresight on High Level Synthesis (HLS) in the form of behavioral compiler in 1990s. Then in 2004, Mentorunveiled Catapult which synthesized pipelined, multi-block subsystems from C/C++. During the same period, Forteintroduced Cynthesizer which synthesized hardware from SystemC. Continuous refinements went down the line to address design issues such as control logic improvements, power optimization, levels of timing abstractions (TLM standard came up) and so on. Other HLS tools such as CadenceC-to-Silicon also came up. These tools actually demonstrated the value of high level synthesis in terms of top-down design methodology from system level that optimized design architecture and cut down design time significantly. However, wider adoption of the HLS tools in design community was distant because they catered to specific type of hardware designs that exhibited mostly one-way data movement. The other reason was lame economic and business push to adopt HLS amid several issues to be resolved there.

Calyptowhich was excelling in SLEC (Sequential Logic Equivalence Check) and PowerPro (Power optimization tool at RTL) found complementary value in Catapult and acquired it from Mentorin 2011 to provide a comprehensive HLS solution. Since then Catapult is proving well in providing value for differentiated IP in video processing, image processing and advanced communication area. Recently by using Catapult Googlewas able to reduce the design time by half for their VP9 video decoder design and further they collaborated with VeriSiliconwhere it was very easy to share C code between them.. Now there is critical mass of designers seeing value in HLS that can optimize design architecture for best PPA at system level, reduce design time by large extent, accelerate verification and debugging at C/SystemC level, and facilitate collaboration and reuse through sharing of technology and architecture neutral designs. By using Catapult, customers have seen significant saving in area (up to 18%) and time (up to 16x) at best QoR of their designs.

However, HLS is still not a mainstreamdesign methodology, why? Recent surveyconducted by Calypto shows that designers need more control for design closure and seamless flow with their RTL verification, choice of C++ or SystemC and also learning through use of HLS. What’s Calypto doing to address these issues now?

The first of its kind in the 3[SUP]rd[/SUP] generation of HLS, Calypto announced Catapult 8 Platform that has unmatched capabilities to make designers more productive through HLS. In my brief telephonic call with Sanjiv Kaul, CEO at Calypto, Mark Milligan, VP of Marketing and Bryan Bowyer, Catapult 8 Product Engineering, I learnt that this newly architected product is a result of multi-year investment in Catapult since 2011. Interestingly, before this full production release, Calypto migrated its major partner customers to Catapult 8 through limited access release in 2014. Naturally, the active key designers’ input has been taken to architect this platform! What’s new?

Unlike older generation of HLS where any incremental change in C++/SystemC could lead to a very different RTL, now with configurable hierarchical design architecture of Catapult 8, designers will have full control over design hierarchy where they can assemble the design in top-down or bottom-up fashion, synthesize and verify individual blocks at a time while keeping rest of the design locked and import Verilog or VHDL IP as needed. This methodology provides automatic as well as designer controlled synthesis that provides 10x capacity improvement in design assembly and synthesis.

Catapult 8 moves the verification up and addresses designers’ major concern about C and RTL mismatches by synthesizing assertions and cover points, identifying and guaranteeing key equivalent points, providing cross-probing between RTL and C++/SystemC and using integrated formal tools to identify unreachable states. With Catapult 8, designers are able to obtain full RTL verification coverage, that has been a requirement for wide spread adoption of HLS. The methodology provides full functional coverage at much reduced (100x to 1000x) server need and smaller code to debug. Also it provides integration with verification flows based on industry standard methodologies such as UVM.

The platform is flexible to accept C++ or SystemC; designers may use both on different projects. Catapult LP, available on Catapult 8 platform provides power optimized RTL which uses Calypto’s patented deep sequential analysis technology and also enables designers to try different microarchitectures to explore low power.

What’s more? Catapult 8 includes a brand new Catapult Catware library of pre-built, synthesizable components that can be used for faster deployment and adoption of HLS. Expect widespread adoption of HLS with this new innovative platform! Stay tuned to hear more details on the specific state-of-the-art capabilities in Catapult 8.

Design Rule Checking (DRC) Meets New Challenges

Design Rule Checking (DRC) Meets New Challenges
by Daniel Payne on 12-02-2014 at 7:00 am
Categories: EDA, Synopsys

The traditional batch-oriented DRC process run as a final check to ensure compliance with foundry yield goals is quickly moving toward a concurrent DRC process performed early and often throughout design, especially at the 28 nm and smaller process nodes. What are the technology factors causing this change?

Increasing number of rules and their complexity
Coloring – the multi-pattern mask requirements
Metal fill is more complex and impacts timing results
Place and Route (P&R) has to be concurrent with DRC to get closure

FinFET transistors starting at the 22 nm node added some complexity to the DRC process, however the double patterning technology (DPT) required at 20 nm caused more computational complexity than FinFET for DRC jobs. Having to comply with 1,000 design rules at 10 nm does not look fun to me. Finally, keeping the CMOS process planar by adding fill patterns has mushroomed in effort required.

DRC Challenges

Related – FinFETs for your Next SoC

DRC tools can identify and automatically fix odd-cycle loops found with DPT, but when we start using Triple Patterning at the 10 nm node you will initially just get a warning and have to make the fixes yourself.

DPT Auto Repair

The computational effort required on verifying the coloring on triple patterning is increasing, so changing the approach to include heuristics is one way to keep run times down. There could even be quad patterning required for the 7 nm node.

Triple Patterning coloring conflict

Metal fill insertion now has to deal with coloring, alignment with signal direction, uni-directional track-based fill and balancing out the density to avoid large gradients:

Metal Fill Insertion

A side effect of adding metal fill is that it adds extra capacitors, thus affecting the timing on nearby nets. Metal fill always degrades Worst-case Negative Slack (WNS) and Total Negative Slack (TNS), causing iterations to get timing fixed. A smart approach is to identify these effects early, fixing them prior to tape out by mitigating the effect.

Related – Challenges of 20 nm IC Design

The latest DRC tool from Synopsysis called IC Validator and it has features to address each of the new challenges talked about so far. Concurrent DRC during P&R is called In-Design, saving you on turn around time.

Traditional vs In-Design Flows

Starting at the 28 nm node is where you see the biggest benefit of using In-Design instead of the older, iterative flow. Something like 20 of the top 25 IC Compiler customers are already using In-Design. Have a single database between IC Compiler and IC Validator means that there is no data streaming, tool setup or translation steps required. IC Validator runs natively incremental on just the changed areas, saving more time over tools that are forced to run on the whole IC layout. One Synopsys customer used the automatic DRC repair feature on their 28 nm design and actually saved 2 weeks in their schedule.

Many of the DPT errors that are identified can be automatically repaired, and the router is part of making the needed repairs. This tight integration between P&R and DRC is really needed to cut down iteration times.

Related – Enabling 14 nm FinFET Design

Critical nets can meet their timing requirements by having the metal fill insertion add spacing on the same layer, which lowers the parasitic capacitance values.

Critical nets with metal fill spacing

IC designers can be somewhat sheltered from coloring and fill, but to get the best chip performance they may adopt a DRC methodology that is concurrent with P&R, run early and often. Using IC Validator is straight forward because the leading foundries (TSMC, UMC, SMIC) and Intel Custom Foundry all support the run sets for their process nodes. You can even work with the FD-SOI process at 28 nm from ST today, and smaller nodes coming soon.

December 1, 2014

Fitness Watch Anyone?

Fitness Watch Anyone?
by mbriggs on 12-01-2014 at 4:30 pm
Categories: Mobile

I’m an exercise junkie. I’m also not a spring chicken so I like having the time on my wrist. I’ve been anxiously awaiting an iWatch to go with my iPhone 6. As patience is not a virtue of mine, and the iWatch is rumored to be expensive ($400-500). I decided to try a fitness watch.

This is a crowded area that includes activity trackers and runner’s watches with GPS. Fitbit and Nike seem to be leading the way in the activity tracker space, with the GPS companies such as Garmin the Magellan trying to stay relevant with GPS enabled runner’s watches.

For me, a key component of a fitness watch is the heart rate monitor. Many of the fitness devices, including the iWatch, use optical sensors. These are generally green LEDs which shine through the skin. This seems to be a technology that hasn’t quite been perfected as active monitoring is a power drain, and the signal/accuracy is sometimes suspect. The runner’s watches on the other hand connect to a chest strap for heart rate monitoring. This is more reliable, but of course bulky and inconvenient.

Jawbone recently introduced a different technology they call Bioimpedance. The sensor technology comes from BodyMedia, a health-monitoring startup Jawbone bought last year. It measures the resistance of body tissue to tiny electric current to enable the capture of a wide range of physiological signals including your heart rate. If you’ve ever measured your body composition such as fat content, this is very similar. There are metal studs inside that conduct electrical bioimpedance measurements. The bad news is that Jawbone’s newest band the UP3 still doesn’t have a display, just a few LEDs.

I read all the reviews I could find, and several publications really liked the Basis Peak. To cut to the chase, the reviewer on re/code got it mostly right with her comment, “I think it earns the title of One of the Best Activity Trackers Available While We All Wait to See What the Heck the Apple Watch Is Really Like. But there are a few areas where it falls short.“

I really wanted to love the Basis Peak. A fitness tracker, that is also a watch is right up my alley. The experience started well, the packaging was extremely well done, even Apple like. The problems started the morning after, and every morning after that. I wore the watch to bed, but do not charge my phone in the same room. It was a struggle to resync with my iPhone 6. It required quitting the app, unpairing Bluetooth, and restarting the watch. I struggle with almost all my Bluetooth devices, including the car and headsets. My Logitech keyboard is my only Bluetooth device that is anywhere close to reliable.

The heart rate monitor often took a long time to get going, as in a minute or two. I shaved the hair off my wrist thinking a better connection with my skin was the problem, but it didn’t help.There were also times when the heart rate shown on the watch was obviously inaccurate.

The calorie reading seemed to be right on, even though an exercise bike is considered walking, so you don’t get credit for steps. The Stairmaster 6000 (the real steps) is considered walking. The straw that broke the camel’s back is when water seeped into the watch during a hot tub incident and now it doesn’t work at all.

Net, net is that the concept is great, but I think seamless operation is a generation or two away. I haven’t quite decided if I’ll try the Withings, Garmin, Fitbit, or wait for the iWatch. My top contender as of this moment is the Fitbit Surge, available in early 2015.

Suggestions anyone?