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October 19, 2014August 22, 2024

GlobalFoundries and IBM

GlobalFoundries and IBM
by Paul McLellan on 10-19-2014 at 9:12 pm
Categories: Foundries, GlobalFoundries

So it’s true. IBM is selling its semiconductor division to GlobalFoundries. Actually, selling is a sort of euphemism for paying them $1.5B to take it off their hands. At least according to Bloomberg. There have been rumors for weeks that IBM wanted to pay $1B to get rid of the division, but GF wanted $2B. Looks like they split the difference.

Dan wrote about this recently. But he was wrong. But only in the small print. He predicted early October (it is now late) and $2B (it is only $1.5B). But pretty close. Read his earlier post here GlobalFoundries Acquire IBM Semiconductor Unit

Is it all true? Probably:IBM will also receive $200 million worth of assets, making the net value of the deal $1.3 billion, said the people who asked not to be identified because the agreement is private. The companies plan to announce the deal tomorrow morning, the people said. IBM put out a statement today saying it planned to make a “major business announcement” tomorrow.

So we need to wait until tomorrow to know for sure. But the background is true. IBM has been trying to find a buyer for their semiconductor business which has been losing a lot of money. GlobalFoundries would like some more research power in technology development (process). But I predict there will be problems because IBM employees are paid at a very high rate, much higher than GF probably pays people in the same position.

So what is the deal likely to be:In a 10-year partnership, Globalfoundries will supply IBM with Power processors in exchange for access to IBM’s intellectual property, the people said. That would allow Globalfoundries to access key chipmaking technology and guarantee supply of chips that IBM needs for its systems, like mainframe computers and its Watson data-analytics technology.

It will remain in the future to tell if this is a good deal. GlobalFoundries currently gets its process from Samsung so all those IBM researchers are duplicate. But that is only at 14nm. I don’t know if the Samsung deal goes to 10nm, or if IBM have any secret sauce for future processes that would make GF competitive. For the time being (meaning 28nm) they are an also-ran to TSMC. But at 14/16nm with Samsung’s help that could change. And at 10nm, with the IBM expertise, maybe they could pull ahead.

UPDATE: here is the first paragraph of the press release, which, apart from financial terms, is the heart of the agreement:GLOBALFOUNDRIES today announced that they have signed a Definitive Agreement under which GLOBALFOUNDRIES plans to acquire IBM’s global commercial semiconductor technology business, including intellectual property, world-class technologists and technologies related to IBM Microelectronics, subject to completion of applicable regulatory reviews. GLOBALFOUNDRIES will also become IBM’s exclusive server processor semiconductor technology provider for 22 nanometer (nm), 14nm and 10nm semiconductors for the next 10 years.

October 19, 2014

Semiconductor Startups on Kickstarter!

Semiconductor Startups on Kickstarter!
by Daniel Nenni on 10-19-2014 at 4:00 pm
Categories: Mobile

One of the challenges for the fabless semiconductor ecosystem is raising funds for new ventures. Of the things I do as a consultant, working with entrepreneurs on business and funding plans is by far the most interesting. Raising money is a big challenge since venture capitalists have largely ignored our industry of late. Kickstarter however offers a new source of funding and you do NOT have to give up 60% of your company!

According to Wikipedia:
Kickstarter is a globalcrowdfundingplatform based in the United States. The company’s stated mission is to help bring creative projects to life. Kickstarter has reportedly received over $1 billion in pledges from 5.7 million donors to fund 135,000 projects, which include films, music, stage shows, comics, journalism, video games, and food-related projects. People who back Kickstarter projects are offered tangible rewards and special experiences in exchange for their pledges. This model traces its roots to subscription model of arts patronage, where artists would go directly to their audiences to fund their work.

The most notable Kickstarter campaign is the Coolest Cooler, which raised more than $13M from 62,462 backers in 52 days. The initial goal was only $50k! In the semiconductor realm the most recent Kickstarter project is ProfileMyRun: Run the Right Way, Run the Natural Way by Palo Alto Scientific:

“As an avid runner, I love to run. But I don’t enjoy the pain associated during the run. I started to ask myself, “There must be a better way to achieve a more natural and enjoyable run, less prone to pain and injury.” I looked around at the available solutions of how to improve runner’s performance, but found these programs to be either too expensive and accessible only to professional runners ($100K)…or too basic, providing only information about your steps and calories ($99), which really doesn’t help the runner attain an optimal run. That’s what inspired me to develop ProfileMyRun…The patented system that takes full advantage of the latest technology in running science, and brings it to everyday people, like you.” – CK Lam, Creator of ProfileMyRun

Full disclusoure: SemiWiki is an ardent supporter of this project. As I have mentioned many times before, IoT and the wearable market is the source of many new design starts, the lifeblood of the fabless semiconductor ecosystem, so I am pleased to do anything I can to help.

This specific project is near and dear to my feet. During my triathlete years running was always my weakest event. My one and only marathon time is 4:20 which barely beat Oprah Winfrey’s time of 4:29. There was no way I was going to lose to Oprah. Like many Baby Boomers I decided to “Just Do It!” without any professional training whatsoever and paid the price with a serious case of shin splints. In fact, just today I ran three miles and now I sit in not so silent pain and suffering. During my six mile Iron Horse Trail walk this morning I discovered my wallet had fallen out of my pocket so I literally sprinted three miles to retrieve it. I leave for Taiwan tonight so losing my wallet was not an option!

Please show your support for ProFileMyRun and the fabless semiconductor ecosystem. We have changed the world and will continue to do so with creative funding sources like Kickstarter, absolutely.

Xilinx: Revenue on Target, Profit Above

Xilinx: Revenue on Target, Profit Above
by Paul McLellan on 10-19-2014 at 7:00 am
Categories: FPGA, Xilinx

Xilinx announced their quarterly results a couple of days ago. Technically it is their Q2 2015. Sales were $604M and profitability was significantly higher than expected at $0.62/share. But that is not the most interesting thing about these calls. There is the Xilinx vs Altera story. And then there are tealeaves to be read about TSMC (Xilinx exclusively manufactures at TSMC).

To me, one of the most amazing numbers, having myself worked within a semiconductor company for years, is that gross margins were 71.9%. A record for the company. As a comparison point, that is way above Intel, never mind other semiconductor companies. That means that for a part that Xilinx sells for $10 they give less than $3 to TSMC. Of course they have other costs but out of $604M of sales they had operating income of $200M.

Jon Olson the CFO summarized the business:28-nanometer sales were flat and 40-nanometer sales declined as anticipated, reflecting an overall decline in our new products category. Our base category, which is comprised of our oldest products, increased significantly during the quarter, driven primarily by the timing of programs in the aerospace and defense end-market that we discussed with you last quarter. On a year-on-year basis, new products were up 21%, mainstream down 8%, and base products down 14%.

It is clear that the results could have been even better since there are limitations on the rollout of LTE in China due to supply chain issues (i.e. shortage of components that are not Xilinx FPGAs). Since China has about 500,000 base stations this has the potential to be a big deal. In the Q&A Jon said that 3G was a steep ramp, then flat, and a fast falloff. LTE is more patchy due to these issues, plus the Chinese economy is not as strong as it was in the 3G rollout period. In the Q&A:We’ve had large wireless OEM customers say we would be taking more FPGAs if we had more power amplifiers…We don’t produce those, so therefore I can’t give you a good reading on when that is going to be alleviated.

Then it was Moshe Gavrielov, the CEO’s turn:28-nanometer product generation is without doubt the most successful node in our history, will serve as the growth driver for the company for several years going forward. Our 28-nanometer sales target in fiscal year 2015 is $600 million, an increase of approximately 60% from the previous fiscal year.

It is clear from Xilinx and everyone else that 28nm is going to be a very long-lived node. It seems to hit some sort of sweet spot on ease of design (although that is less important with an FPGA), cost of manufacture and available capacity. And in the Q&A they were very explicit:our product offering in 20 is very broad. It has the midrange and it has a high-end and super-high-end component to it. So we’re very bullish on what it will provide. But clearly it won’t be as good as 28, which for a variety of reasons actually is broader and will have a longer life due to some cost-related elements.

Moshe commented on the Xilinx vs Altera story too. Although, of course, he never said the word Altera:At the 20-nanometer node, independent customer feedback indicates that we have approximately a one-year lead over the competition, both in terms of our ultra-scale silicon maturity and quality of results. This significant technology leadership is delivered in the broadest and most compelling midrange product family, complemented by the industry’s only high-end family. This is manifested in the largest FPGA in the industry which delivers over 4x the capacity of competitive devices.

A one year lead over your competition is huge, of course. But the big transition is coming up at 14/16nm with the added interest of Altera switching to Intel as a foundry. I don’t believe I’ve seen any official statement about when Xilinx might start shipping 16nm, but word on the street is in Q2 of next year. After all, foundries like to use FPGAs as a process driver so they are always early in the cycle. Altera said they would tape out in Intel 14nm in Q1 of next year (this was over a year ago so things might have changed a bit). With fab cycle times and device qualification times it is hard to imagine Altera will start shipping 14nm parts until Q4 or even 2016. That would put Xilinx still being 6 months to a year ahead of Altera.

But Moshe is even more bullish. As he said in the Q&A:We expect the sum of 20nm and 16nm to approach what 28nm will be. And it’s difficult for us to make the division between the two. Fundamentally, 20nm for us will be two years ahead of 16nm and two years ahead of any competing product in an advanced node.

And a final read of the TSMC tea-leaves:With regards to defect density and maturity of the products, it’s [20nm] ahead of where we were at the same point in time at 28-nanometer. And 28-nanometer was very smooth introduction for us. But 20-nanometer, and this is the second-generation we have done with TSMC, has been extremely smooth.

MIPI Soundwire IP Sounds Innovative

MIPI Soundwire IP Sounds Innovative
by Eric Esteve on 10-19-2014 at 3:07 am
Categories: Cadence, IP

MIPI SoundWire specification will be integrated into mobiles systems, like smartphone or media tablet. In fact some of the well-known chip makers have already decided to integrate MIPI SoundWire into their last application processor release. MIPI SoundWire is also the type of specification which could be used in many other applications even if the primary target is smartphone, features phones and media tablet. According with Cadence: “SoundWire is a new digital audio interface specification from the MIPI Alliance that enables bi-directional digital communication with a focus on low complexity and low gate count, making it attractive to many mobile design applications.” The important words are low complexity and low gate count. An application processor for mobile count billion transistors, so the gate count is not an issue, but if we consider the IC devices controlling the peripheral (earpiece, speaker, internal micro, etc.), these are probably designed in more mature technologies, up to 130nm or even more. Such chips are targeting consumer or mobile applications, implying very high production volume and the cost is a key driver. Thus, benefiting from an efficient interface protocol is attractive at the condition that the cost impact is kept as low as possible.

MIPI SoundWire Controller IP is master/slave interface protocol. The master register can be accessed internally from a 32-bit AHB client interface. All registers are mapped to host memory space. Certain timing critical registers are banked to allow synchronous switching without interruption to data streams. We understand from the system level block diagram above pictured that the master could be either integrated in the application processor (mobile system), either in a DSP based audio ASSP. Both types of chips integrate a processor, so the choice of an AMBA AHB bus to access the master is judicious. The Slave Controller IP contains only a small subset of the logic.
MIPI SoundWire is Feature-rich IP solution: it was important to offer high level of configurability. In fact, the master can be configured with the following options:

PDI count and width
PDI type
PDI FIFO depth
Command FIFO depth
Data lane count
Source input clocks

MIPI SoundWire is a layered interface protocol, and the physical layer definition is an important part of the specification. MIPI SoundWire protocol doesn’t use MIPI D-PHY or even C-PHY, but the PHY uses modified NRZI. The PHY logic drives or detects multi-lane capable SoundWire IO interface. The master controller contains a clock generator that drives the clock signal to all slaves. The clock frequency is derived using a configurable gear box and a reference clock input. Clock stop handshake protocol is supported by the PHY layer. Clock can be stopped and resumed with precise synchronization to SSP interval. Once clock is stopped, the master controller enables asynchronous slave or self wakeup detection.

“With a complete solution targeted specifically for MIPI SoundWire, including verification IP released in March, we are fully enabling designers to integrate the latest technologies into their SoC designs for the mobile and consumer market” said Martin Lund, senior vice president of the IP Group at Cadence. Providing the related verification IP should facilitate early adoption of the new SoundWire spec. In fact, Cadence is a longtime supporter of MIPI specifications, as in the early days of the MIPI Alliance, the company was offering Verification IP for the various MIPI specification like DSI or CSI-2. The release of MIPI SoundWire Verification IP well in advance (March 2014) and Design IP now is a clear sign that Cadence send to the competition: Cadence has invested a lot to develop IP supporting MIPI specifications and the company will be present on this front.

Eric Esteve from IPNEST –

October 18, 2014July 18, 2025

Linux and the ARC of the Coherent

Linux and the ARC of the Coherent
by Don Dingee on 10-18-2014 at 7:00 am
Categories: IP, Synopsys

Remember that thing called “real-time Linux”? Yeah, nobody else does either. As builds became configurable and clock speeds increased, embedded Linux manifested itself as fast enough for many applications – if a few other SoC details are addressed.

Most obvious for SoCs to run Linux is the need for a fully integrated MMU implementation. Continue reading “Linux and the ARC of the Coherent”

October 17, 2014

Recap of the Apple iPad Announcement

Recap of the Apple iPad Announcement
by Daniel Payne on 10-17-2014 at 2:00 pm
Categories: Mobile, TSMC

I watched the live stream product announcements yesterday from Apple and will give you a quick recap of what I gleaned. First off, Apple live stream requires that you use the Safari browser, so that meant that I couldn’t use Google Chrome, so much for adopting web standards.

Apple Products Talked about

iPhone 6 and 6 Plus
This was the biggest and fastest product launch in the history of Apple, which is quite the feat. We’ve been blogging that the A8 SoC used in these products is manufactured byTSMC, using some 2 billion transistors at the 20nm node. The 5.5″ display iPhone 6 Plus now sells about 24% of total iPhone sales, the 4.7″ display iPhone 6 at 62%, and remaining iPhones at 11% (Source: Consumer Intelligence Research Partners). The iPhone 6 starts selling in China today, which is expected to be another growing and emerging market for Apple.

ApplePay
The ApplePay allows for easier purchasing by using the NFC (Near Field Communication) feature in iPhones, and will start in retail stores on Monday. I use NFC and Google Wallet on my Galaxy Note 2, but find that most stores aren’t setup yet for NFC support, so I expect this will be a gradual ramp for ApplyPay as well. Oddly enough my local Best Buy store has NFC-ready checkout, but their software isn’t installed yet so cannot be used. ApplePay will start appearing on web sites as well, competing with the likes of PayPal and Google Pay.

Apple Watch
It’s coming, but you have to wait until early 2015 to buy one. Independent software developers will get an Apple Watch SDK in November, so that will start the race to build new apps that are watch centric.

iOS8, OS X Yosemite
Apple has two operating systems – one for touch devices called iOS8 and the other for mouse-based devices called OS X Yosemite. The latest release of iOS8.1 fixes bugs, adds new features like ApplePay support and is ready on Monday. OS X Yosemite is mostly a cosmetic facelift along with hundreds of incremental improvements, is free, and the 5.1 GB downloads started yesterday. I’ve started using OS X Yosemite on my MacBook Pro and was surprised that during the upgrade the default was set to turn on file encryption, aka FileVault, although I kept it turned off. Mac Mail now also has an annoying bug in it where the From field will occasionally show up with the wrong name in it.

Customer adoption of iOS8 quickly reached 48% of the installed base on iPad and iPhone devices, way ahead of what Android users experience. My iPad 3 and iPad Air are upgraded and working well with iOS8, so far so good.

iPad Air 2, iPad Mini 3
It’s a thinner iPad, slimmed down to just 6.1mm, the world’s thinnest. The display is less reflective, which is a step in the right direction for users that don’t want to look at themselves all day. To me the big news was that this device uses an A8X chip, reported to have 3 billion transistors. We could assume that the manufacturing is TSMC again, because they fabricated the A8 chip, too bad for Samsung this round.

The smaller screen product iPad Mini 3 has the touch ID feature, comes in three colors and is priced from $399 to $599. The Apple marketing folks continue the tradition of offering previous generation iPads at reduced prices, giving consumers multiple price points to choose from.

iMac Retina 5K
Bigger is better when it comes to desktop computing, and the new iMac has a 27″ display with 5K, which is 5,120 x 2,880 pixels. Priced lower than a 4K TV set, this iMac starts at $2,499 and uses the 3.5 GHz quad-core Intel Core i5 chip. We’re still waiting for the day that Apple uses the A-series chips for all of the devices, breaking ties with Intel completely.

Mac Mini
This diminutive Mac Mini box finally got updated with latest Intel processor, faster Thunderbolt 2 ports (20 Gbps speeds) – enabling video streaming to one 4K monitor or dual QHD displays.

Continuity
As you can imagine Apple wants you to own all of their devices, however with two different operating systems how do you share files or apps? They talked a lot about continuity in the latest iOS8 and Mac OS X Yosemite, that now allow you to work between devices on the same app like Keynote. In the demo they started a Keynote presentation on an iPad, then moved over to iMac to continue editing right where they left off, and finally controlled the presentation using Apple Watch and streaming to Apple TV.

Full Disclosure – I own AAPL stock, have Apple products, and use the Samsung Galaxy Note 2.

October 17, 2014

Atmel’s New Microcontrollers and IoT, Wearables

Atmel’s New Microcontrollers and IoT, Wearables
by Paul McLellan on 10-17-2014 at 7:00 am
Categories: Foundries

More and more companies, regardless of their vertical, are trying to get closer to their customers and see various aspects of the internet of things (IoT) as the way to do so. For a good example, here is Salesforce Wear Developer Pack which, as they say:..is a collection of open-source starter apps that let you quickly design and build wearable apps that connect to the Salesforce1 Platform. Millions of wearable devices connected to the cloud will create amazing new application opportunities.

Since salesforce.com cuts across all industries this has potential impact in many different market segments.

And the wearable devices that they list are Google Glass, Android Wear, Samsung Gear Watch, Myo Armband, Nymi Bionym, Pebble Watch, Jawbone UP, Epson Moverio, Vuzix Smart Glasses, Oculus Rift, Meta Glasses.

This combination brings home that the internet of things isn’t just about the things, it is about connecting the things back to the cloud so that the data generated can be aggregated where it has much greater value.

I am sure that people will design SoCs for various aspects of IoT, but even if they do I think it will be in old processes, not even 28nm, so they can integrate sensors and analog and wireless on the same chip. But more likely a lot of these will be small boards with microcontrollers, wireless and sensors on different chips. For example, take a look at the iFixit teardown of the Fitbit, which in its current incarnation is about one inch by quarter of an inch.

An important aspect of doing this sort of design is having enough microcontrollers with the right combination of features. You can’t afford to have twice as much flash as you need or too many unused functions. The Atmel microcontroller product finder shows that at present they have 506 different ones to choose from.

The most recent two are SAMA5D4, and SAMD21 which are specifically targeted towards wearables and IoT projects. These are the latest two products in the Atmel SAM D family.

One area of especial concern in this market is security since it is too dangerous to simply try and do everything in software on the microcontroller. Keys can be stolen. Software can be compromised if it is in external RAM. An area of particular security concern is to make sure that any JTAG debug port is secure or it can be used to compromise almost anything on the chip.

So what are these chips?

The SAMA5D4 is an ARM Cortex-A5 device with a 720p hardware video decoder. It has high security with on-the-fly capability to run encrypted code straight out of external memory, tamper detection, secret key storage in hardware, hardware private and public key cryptography and ARM TrustZone. It supports both 16 and 32 bit memory interfaces for maximum flexibility. It is targeted at applications that require displays, such as home and industrial automation, vending machines, elevator displays with ads, or surveillance camera playback.

The SAMD21 is the latest Atmel microcontroller based on the ARM Cortex-M0+ but in addition to the features on earlier cores it also has

Full Speed USB Device and Embedded Host
DMA
Enhanced Timer/counters for high end PWM in Lighting and motor control – I2S
Increased I2C speed to 3.4Mbit/S
Fractional PLL for audio streaming

As you can deduce from the feature set it is target at medium end industrial and consumer applications, possibly involving audio and high power management .

And to show that this sort of market is starting to become real, at the salesforce Dreamforce event earlier in the week a keynote was given by Will.i.am of the Black Eyed Peas (and a founder of Beats that Apple recently acquired). In a chat with Marc Benoiff, CEO of salesforce.com, he has already leaked that he will introduce a wearable wrist computer that doesn’t require a phone to piggy-back on (unlike the Apple Watch).

Or watch the chat:

More information on the SAMA5D4 is here.

TSMC Breaks More Records in Q3 2014!

TSMC Breaks More Records in Q3 2014!
by Daniel Nenni on 10-16-2014 at 4:00 pm
Categories: Foundries, TSMC

As previously predicted TSMC is having another record breaking SoC quarter. TSMC is my favorite economic bellwether and from what I can see the semiconductor industry will continue to grow this year and next at a rapid rate thanks to TSMC and the fabless semiconductor ecosystem:

We have set a new record of revenue and profitability thanks to strong demand and our successful ramp of 20nm. Our revenue increased 14% sequentially and 29% on a year-over-year basis to reach $209 billionNT. Our gross margin exceeded 50% to reach 50.5% which is also a record since the second half 2006.

20nm is the focus of this quarter and rightly so. Let’s not forget that a famed semiconductor analyst, Dr. Handel Jones of IBS, predicted at the beginning of this year that:

20nm will be a high volume technology node in 2015 but mostly 2016.
16/14nm will provide low cost gates with volume production only in 2017.
10nm will be postponed. Cost per gate will be prohibitive and unclear where demand will come from outside high-speed processors and FPGAs.

Also Read:Handel Jones Predicts Process Roadmap Slips

To be clear, 20nm is in high volume production TODAY and 14nm/16nm will be in high volume production in 2015. In regards to 10nm:

On 10 nanometer development our 10 nanometer development is progressing according to plan. Currently we are working on early customer collaboration for product tape outs in 4Q of 2015. The risk production date remains targeted at the end of 2015. Our goal is to enable our customers’ production in 2016.

To meet this goal we are getting our 10 nanometer design ecosystem ready now. We have completed certification of over 35 EDA tools using ARM CPU core as a vehicle. In addition we have started the IP validation process six months earlier than previous nodes with our IP partners.

TSMC has a dozen 10nm early access customers designing SoCs, baseband/LTE chips, CPUs, GPUs, network processors, FPGAs, and game consoles. So, rather than postponing, TSMC has pulled in 10nm to better align with the Intel 10nm road map. The famed Intel process lead, in regards to SoCs, has slowed since 22nm. The Intel Bay Trail 22nm SoC was released in Q3 2013 while Apple’s 20nm A8 was released in Q3 2014. The Intel 14nm Cherry Trail SoC has now been delayed to Q1 2015 and the Intel 14nm Broxton SoC targeting phones is no longer being discussed publicly.

We are happy to say that 16 nanometer has achieved the best technology maturity at the same corresponding stage as compared to all TSMC’s previous nodes. On the yield the progress is much better than our original plan. This is because the 16 nanometer uses similar process to 20 SoC except for the transistors and since 20 SoC has been in mass production with good yield.

On the performance side compared with the 20 SoC, 16 FinFET is greater than 40% speed, faster than the 20 SoC at the same total power or consume less than 50% power at the same speed. Our data shows that in high-speed application it can run up to 2.3 GHz or on the other hand for low power application it consumes as low as 75 milliwatts per core.

Samsung still seems to have a production lead over TSMC at 14nm. My expectation is that Samsung 14nm SOCs will start revenue in Q2 2015 and TSMC 16nm FF+ SoCs will start in Q3 2015, so Intel’s process lead is narrowing. At 10nm I expect the foundries to be lockstep with Intel (for SoCs). Just my opinion of course.

You can find TSMC quarterly result and presentation materials HERE.

October 16, 2014

Finding Logic Issues Early that Impact Physical Implementation

Finding Logic Issues Early that Impact Physical Implementation
by Daniel Payne on 10-16-2014 at 7:00 am
Categories: EDA

Complex SoC project teams typically use a divide and conquer approach where specialized engineers work in separate domains, like front-end or back-end. The five major engineering tasks for IC design can be described as: RTL design, synthesis, floor planning, place and route, then finally design analysis.

What if you could detect physical implementation bottlenecks earlier in the design process, like during RTL design? That ability would save you not only design time, but also reduce the number of iterations in trying to reach design closure and sign-off. Here’s what the design iteration cycle looks like if you wait until physical implementation and then analyze for design closure:

The steps in red show that engineering has to review the results of Static Timing Analysis (STA), identify the critical paths that are limiting the clock rate, rework the floor plan, try various design optimizations, re-run STA, then maybe go all the way back to RTL and try refactoring code to eliminate the logic creating the bottleneck for closure. One EDA vendor that has studied this issue is Atrenta, and their approach to reduce design closure iterations is called Physical Lint – a step used during RTL coding that predicts the physical implementation effects of logic at an early stage:

There are logic structures identified during RTL analysis known to cause physical implementation issues, like:

Large logic cones
Large muxes
Registers or memories
Excessive register count
Unintended black boxes for physical implementation

During physical lint the SpyGlass tool applies rules based on your actual technology mapped design to improve accuracy. For the rule about large logic cones their tool can automatically identify flip-flops with high fan-in cones, then show you how to split them up. Likewise, for flip-flops with high fan-out, the fix is to add a pipeline:

For muxes the SpyGlass Physical tool identifies both wide and deep muxes and can show you where to refactor the RTL by mux spreading, thereby reducing physical congestion.

All of the rule violations identified by SpyGlass Physical are presented in a spreadsheet viewer, and ranked based upon their physical impact so that engineers can quickly identify the RTL source code. Modifications are suggested for each rule violation, keeping the designer in control of all changes.

Mark Baker of Atrenta presented the approach of SpyGlass Physical in a 29 minute webinar, now archived and available online. The basic premise is that an ounce of prevention is worth a pound of cure, so why not use the physical lint approach in your next IC project.

Q&A

Q: Will SpyGlass Physical attempt to update my RTL?

A: Today we identify the RTL code, then suggest how to change your RTL.

Q: What physical data is required to run Physical Lint?

A: We’re using the standard Liberty format for your cell library along with the RTL source code.

Q: How does SpyGlass compare to actual logic synthesis results?

A: In physical lint we’re doing a fast synthesis process, and there’s not a need for heavy timing optimizations.

Q: How does the actual implementation compare to what SpyGlass predicts?

A: We see excellent correlation in identifying physical congestion.

October 15, 2014

Demler: Quad Core is Just For Marketing; Intel Will Not Succeed in Mobile

Demler: Quad Core is Just For Marketing; Intel Will Not Succeed in Mobile
by Paul McLellan on 10-15-2014 at 9:00 pm
Categories: Arm, Intel Foundry, IP, Mobile

At Memcon today Mike Demler of the Linley Group (and coincidentally someone who used to work for me back at Cadence and who now run Memcon, small world) gave an interesting presentation on Trends in Mobile Processors. A mobile application processor (AP) is a highly integrated SoC to run the applications in a mobile device. Mostly they run Android or iOS although there are a few other mobile operating systems around. The AP always contains MMU, GPU, ISP and VPU but increasingly they might contain cellular baseband (typically LTE these days), Bluetooth, Wi-Fi and GPS although sometimes those are on separate chips. The power is 2W or less in a phone, 4-5W in a tablet.

Starting with Samsung’s Exynos Octa these often contain four main cores or up to 8 in the ARM big.LITTLE configurations. All cores get counted since all can be running at the same time (initially big.LITTLE could only run the big or the little out of each pair). The smallest cores are slower but consume a lot less power (and area). For example, Cortex-A7 is 3.5x more efficient in MIPS/W and 2x in MIPS/mm2.

But there is a dirty secret. When the Chinese smartphone test service Testin measure multicore utilization on a Qualcomm APQ8064 (it is a quadcore Snapdragon AP) the utilization was 58% on the first one (actually the zeroth one, computer scientists like to start counting at zero) was 58%, on core 1 it was 49% but on cores 2 and 3 it was 2% and 1%. The numbers vary a little with the benchmark but the basic fact remains true. Only two cores are really getting any use.

Also Read: Samsung Profits Fall 60%

So if 4 cores are not even being used then why 8 cores. Basically marketing. One thing that I’d not thought of is that in Chinese culture 8 is a symbol for prosperity (because it sounds like the word for wealth) and 4 only differs from the word for death in the tone. My ex-father-in-law used to work for Wedgwood and for the Chinese market they had to ship a tea-service, say, with 5 cups and saucers not 4. Some games can use 4 cores but the improvement over 2 is minimal.

So where are we? Single core is pretty much gone. Quadcore is the most common configuration, the average will be 4 next year. It is also all going to be 64-bit. Apple designed the first 64-bit ARM (before ARM) followed by Qualcomm (they both have architectural licenses so don’t have to wait to get the IP from ARM). Same for the Intel processors: quadcore Baytrail for tablets and quadcore Moorefield for smartphones (although so far only used for phablets). But again the transition is driven more by marketing than technology since it is not needed until devices with 4GB of DRAM appear. There is actually a performance advantage since A53 is faster than A7 even on 32 bit code and the area penalty is minimal.

Having written yesterday about Intel losing $1B/quarter in mobile, Linley’s projection is not optimistic that this will change. They predict rapid decline in 32-bit ARM APs, rapid growth in ARM 64-bit APs (A57 at high end and A53 at low end + Apple and Qualcomm doing their own thing) and nothing significant in x86.

Graphics will get a lot more powerful driven by games and the transition to what is called 4K video (4000 pixel horizontal resolution approx). The drive for this is not so much that phone screens will have that resolution but people will want to connect their phones/tablets to high-resolution TVs, if and when we have them (which remains to be seen).

Next week is the Linley Processor Conference on October 22nd to 23rd. I’ll be there (so will Mike Demler). It is in the Hyatt Santa Clara (yes, in the hotel not the conference center). Details here. This is not the mobile processor conference which is in the spring, this one is focused on networking and base-station. But note, registration closes at 5pm today.

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