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How Sonics Uses Jasper Formal Verification

How Sonics Uses Jasper Formal Verification
by Paul McLellan on 11-11-2014 at 7:00 am

The Jasper part of Cadence announced jointly with Sonics a relationship whereby Sonics uses JasperGold Apps as part of their verification. I talked to Drew Wingard, the CTO, about how they use it.

One way is during the day when their design engineers use Jasper as part of their verification arsenal. Interestingly it is the design engineers that use it, not the verification engineers.

Formal verification is especially good at finding corner case problems that simulation misses. It is almost impossible to build a cache-coherent network without formal since you will never think of everything to simulate, for example. It finds deep bugs in multiprocessor systems, which is pretty much what a modern SoC is. Sonics have a bigger problem than an SoC in that it is so configurable so it is not just a matter of running formal to prove something about a static design. It goes without saying that it is not possible to generate exhaustively all the possible configurations or even anything close, any more than you can exhaustively simulate all conditions on a modern SoC.

But the big motivation for using JasperGold was at night when they run their nightly regressions. Sonics have discovered in the past that almost any error in the design eventually shows up as a protocol error, in much the same way that stuck-at faults are surprisingly powerful in testing ICs even though many faults are technically something else. The value in a network-on-chip (NoC) is often being able to mix and match protocols: ARM, AXI, OCP, old VSIA stuff even. For a long time Sonics have developed protocol checkers that make sure that they are executed properly. They even distribute these to their customers and always the first question when a customer reports a bug is to ask if they have turned the protocol checkers on. Often the customer is soon back: “my bad.”

So the first requirement to adopt JasperGold was that the protocol checkers could be used to generate formal constraints and assertions with only minimal incremental effort, otherwise adoption would be too time-consuming and expensive. That would then make it easy to run formal techniques in the nightly regressions alongside simulation.

The Sonics nightly regressions work by generating constrained random configurations and then running constrained random simulations on them, and now JasperGold too. There is a tradeoff between how many random configurations are generated and how deeply they are exercised, either in the number of vectors or the amount formal proof time that is allowed. After all, there is a fixed size regression farm and the nightly regressions have to run in a night, by definition. That way problems can be fixed the next day and licenses are freed up for use by engineers when they arrive at work.

Sonics have discovered that it is much better to generate lots of configurations and then do relatively shallow testing on them. After all, a bug that shows up after 21 transfers but doesn’t create any issues in the first 20 is not highly likely. Better to generate more configurations and do some constrained random testing using different starting seeds. In fact Sonics generate thousands every night.

With limited modifications they could reuse their existing protocol checkers (which are standard SystemVerilog constraints). The worst case was a protocol checker requiring about 15% rewrite. So the Sonics verification approach is to generate a huge number of configurations of the NoC(s). Test them a bit with all the protocol checkers using either simulation or now formal proof techniques. The fact that the same protocol checkers work in both environments makes this very powerful.


What is up with CEVA?!?!?!

What is up with CEVA?!?!?!
by Daniel Nenni on 11-10-2014 at 7:00 pm

Semiconductor IP is definitely driving the rapid mobile expansion we are experiencing today and CEVA is a glaring example of that. Mobile design cycles are a fraction of what they used to be so who has time to create, integrate, AND validate your own IP blocks, especially at multiple foundries?


Just a little background, CEVA is really a DSP core and software company. Digital Signal Processors are big in cellular and other data dependent markets (mobile, digital home, networking, and infrastructure). The CEVA cores are synthesizable so you can customize them for performance, power, and cost which gives them access to a broad range of applications and customers. They are also programmable and can be quickly upgraded through software which is a big deal. We have been working withCEVA on SemiWiki for 2+ years now and I can tell you they are a very easy company to get along with, absolutely.

Check out the CEVA Virtual Demo Showroom and see some of the clever applications. Very cool indeed!

What I do not know however is how they posted such a monster quarter:

  • Total revenue for the third quarter of 2014 was $14.1 million
  • An increase of 41% compared to $10.0 million for Q3 of 2013
  • Licensing and related revenue for the third quarter of 2014 was $8.7 million
  • An increase of 121% compared to $3.9 million reported for Q3 of 2013
  • Royalty revenue for the third quarter of 2014 was $5.4 million
  • A decrease of 11% compared to $6.1 million reported for the third quarter of 2013
  • CEVA signed ten new license agreements. Four of the agreements were for CEVA DSP cores, platforms and software, and six were for CEVA connectivity IPs.
  • Target applications for customer deployment are LTE-Advanced handsets, mobile infrastructure, vision for surveillance equipment and digital cameras, access points and wearables
  • Geographically, six of the agreements signed were in the APAC, including Japan, three were in the U.S. and one was in Europe.

“Our third quarter results were driven by the strongest licensing quarter in the company’s history. We continue to experience a healthy demand for our products from new customers targeting a broad range of end markets. We are encouraged by our customers’ progress in LTE and low cost smartphone shipments, both of which delivered quarter-over-quarter and year-over-year unit growth.” Gideon Wertheizer, Chief Executive Officer

CEVA even did a nice infographic to help us digest all of this:http://www.ceva-dsp.com/infographic

Can someone out there shed some light on this for me? As soon as I can gather more data I will schedule a call with a CEVA executive so post some questions that will make me sound smart or send them in private SemiWiki email.

More Articles by Daniel Nenni…..

About CEVA, Inc.
CEVA is the world’s leading licensor of DSP-based IP platforms for vision, audio, communications and connectivity. CEVA’s IP portfolio includes comprehensive technologies for computer vision and computational photography, advanced audio and voice processing, wireless baseband (2G, 3G & 4G LTE/LTE-A), connectivity (Wi-Fi & Bluetooth) and serial storage (SATA & SAS). In 2013, CEVA’s IP was shipped in more than one billion devices, including 40% of handsets shipped worldwide, powering smartphones from many of the world’s leading OEMs such as Coolpad, HTC, Huawei, Lenovo, LG, Nokia, Samsung, TCL, Xiaomi and ZTE. For more information, visit www.ceva-dsp.com. Follow CEVA on twitter at www.twitter.com/cevadsp


Power-Aware Verification in Mixed-Signal Simulation

Power-Aware Verification in Mixed-Signal Simulation
by Daniel Payne on 11-10-2014 at 7:00 am

My Samsung Galaxy Note 2 phone lasts about 1.5 days on a single battery charge, thanks in part to the clever power conservation approaches like when the screen is automatically dimmed then turned off after no activity. Mobile phones and many other battery-powered devices used today all need power-saving designs, which then means that engineers needs to verify the power management approaches. The Unified Power Format (UPF) standardized as IEEE 1801-2009 or 1801-2013 is a popular way to annotate your design with both the power and power control intentions.

What if you wanted to take into account the analog effects of the power management blocks? UPF doesn’t cover that, so you’re still open to errors in the design and verification of your power distribution network and verification of power states. Engineers at Infineon and Mentor Graphics have created a methodology to extend UPF to include mixed-signal verification, presenting a paper at DVCon Europeon October 14, 2014 and also in a recentWhite Paper.

Here’s the proposed power-aware mixed-signal verification environment:

With this type of verification environment the analog power supplies get synchronized with the power state of the UPF power domain, so it’s possible to reuse the standard UPF constructs. The mixed-signal verification tool elaborates the analog-UPF boundary, and then inserts the Power-Electrical (P2E) and Electrical-Power (E2P) connect elements.

Tire Pressure Monitoring System

Infineon engineers used the power-aware, mixed-signal verification on a tire pressure monitoring system (TPMS), shown in the following block diagram:


Design blocks of TPMS

This product has ten power domains, multiple operating modes, and multiple power states like:

  • Low-frequency
  • Low-power
  • Ultra-low power
  • High performance (micro Amps)
  • Power down mode (a few hundred nan Amps)
  • Standby mode

UPF helps define the power intent during physical implementation of the digital parts of the TPMS design. The on-chip voltage regulators create and regulate voltages ranging from 1V to 5V.

Related – Transceiver Verification of a 20nm Altera FPGA Device

Previous Approach

A manual modeling approach was used previously where the digital part of the design was wrapped in a model (blue areas), then digital signals interfaced to analog with power-conversion models (pentagon shapes).

Manually editing a netlist and inserting power conversion model instances takes time, is error prone, and may not even match the actual power distribution network used by UPF. With this approach you couldn’t check for proper level shifting, or isolation and retention cell placement.

New Approach

With the Mentor simulator Questa ADMS you can use a power-aware mixed-signal verification flow. The simulator inserts the boundary elements between UPF and analog ports, keeping the power state and value in sync between the analog and digital domains. During verification of DVFS (Dynamic Voltage and Frequency Scaling) states of the design, the A2D and D2A logic boundary element include the primary power and ground port state plus the value of power domain logic signal belongs to.

Here’s what the power-aware logical boundary elements look like:

With this approach we don’t need the power conversion models, because the power information comes straight from UPF instead. With an analog-on-top methodology there is still a wrapper used.

Related – Coverage Driving Verification for Analog? Yes, it’s Possible

For the highest verification accuracy a SPICE netlist was used for the custom power switches in order to see the voltage switching and control sequence timing.

An E2P boundary element helps define the power net state:

Simulation results show the transition from a High Performance state to Power Shutoff, and then to a Low Power state:

With this new approach we can verify that:

  • Correct level shifter units are inserted
  • Proper isolation behavior
  • Proper retention behavior
  • Assertions are working

Summary

It’s now possible to use a power-aware, mixed-signal verification methodology by extending a UPF flow. Benefits of this flow include faster verification times, higher accuracy of analog design units, verification of the actual power architecture, verification of the power states, and verification of power state transitions.

Read the complete White Paper here.

Related: Improving Verification by Combining Emulation with ABV


Money for data and your MEMS for free

Money for data and your MEMS for free
by Don Dingee on 11-10-2014 at 12:00 am

An ongoing IoT debate centers on the notion that just because we can do something does not mean we should. From discussions at the recent MEMS Executive Congress, looking at what TSMC and some others see as the endgame for a trillion sensors signals possible trouble ahead. Continue reading “Money for data and your MEMS for free”


Getting a Quote Without Talking to a Salesman

Getting a Quote Without Talking to a Salesman
by Paul McLellan on 11-09-2014 at 4:00 pm

VLSI Technology, for those of you not of a certain age, was one of the companies that, along with LSI Logic, created the ASIC business. One challenge in ASIC is that the customer needs to decide which ASIC company to use (since the libraries and technologies are all different) meaning they needed to get quotes from several companies. The procedure was tortuous. The customer would contact a VLSI salesperson who would collect the relevant data about the design. This would then be passed to the design center (later technology center) that was going to support the design who would estimate the cost of the design in manufacturing (and any services that were to be provided). The design center manager, who was essentially local marketing, would manually work out the die size and then use our cost model (hopelessly bad in the early days) to work out the cost. Margined up he (I don’t think we had any female design center managers) would then tell the salesperson the price. There would sometimes be a negotiation, often along the lines of Japanese semiconductor company X quoted half as much, to which we would point out that they didn’t actually have the capability to do a design that complex (usually true). LSI Logic would usually quote around the same price as we did. If the customer was sensible they would pick LSI if they decided to do a gate-array and VLSI if they decided to do a cell-based design. If they picked Japanese semiconductor X they would usually be back 6 months later when everything had gone pear-shaped (where does that phrase come from?).

The whole process might take weeks. By the way, the salesperson was never told the estimated cost, just the price, so that they didn’t assume that they had more flexibility in negotiation than their instructions. As an aside that is one reason that software negotiations are so different from hardware, the salesperson knows that the actual marginal cost is basically zero. And so does the customer.

Given that the process took weeks, it was really hard to handle the customer who came back and said “the price is too high”, what if I halve the size of the RAM and put it in a cheaper package. More weeks.

Until comparatively recently, getting a quote from anyone was basically the same process. Yes, the cost models had improved. Yes, spreadsheets had become ubiquitous. But it was basically the same: tell us about the design, here’s a price. And it still took weeks.

At its peak, VLSI Technology roughly brought 200 designs into production a year, which probably means 250 design starts (including ones that got canceled) meaning maybe 700 quotes since customers would typically get 2-3 quotes before picking a supplier. That is a lot of work, much of it busy work. The designs we won obviously also had to cover all the costs of quoting the designs we lost.

eSilicon is a fabless ASIC company. Well, and more. It does designs starting from all sorts of points depending on what the customer wants, and then delivers (usually) packaged parts to a price. Sometimes the customer does all the design and just uses eSilicon for manufacturing. Sometimes they use eSilicon IP. Sometimes eSilicon provides some level of design services. And sometimes, companies just get eSilicon to manage their production operations.

Internally, they realized that the manual process of estimating what they should quote the customer was too slow (still measured in weeks) and so they automated the process. They created a system that their experts could use to turn a quote in a day. Not only that, it meant that the internal cost of a quote to eSilicon was pretty low.

But eSilicon realized they could go one step further. Why involve their own experts at all? If they put the quote system on their website then customers could do all the work (self-service gas stations or ATMs anyone?) and get their own quotes. Not only that, since iteration was so much easier, customers could home in on the sweet-spot of their functionality/price point. They started just with MPW shuttles but then they extended it to full volume production (at this point just with TSMC). That’s right, you can go online and get a quote from eSilicon for your design in TSMC production untouched by human hand. And iterate that quote a dozen times for different configurations, packages, volumes and so on. Its online, nobody is going to complain about how much quote busy work you are creating any more than the gas station will complain if you only put in 1 gallon each day.

I’ve actually used their quote system for my (hypothetical, obviously) design. It works just like it says on the can. There is a design entry phase where you give all the parameters of the design. The actual quote takes less than a minute to generate. And it is probably worth emphasizing that it is a quote. A real binding quote. If you sign it, then eSilicon will honor the price.

See eSilicon and the 10 minute quote

If you want to know more, there is a webinar next Wednesday at 9am Pacific. Mike Gianfagna is moderating a panel so I can’t claim there is absolutely no marketing but it is mostly about people’s experience at using the quote system. The panelists are:

  • Bil Brennan from Credo Semiconductor
  • Trevor Hyatt from IDT
  • Mahesh Tirupattur from Analog Bits

For more details and to register for the webinar go here.


More articles by Paul McLellan…


Who is Using Samsung 14nm?

Who is Using Samsung 14nm?
by Daniel Nenni on 11-09-2014 at 7:00 am

As I have mentioned before, there are very few secrets in Silicon Valley. Just last week I was minding my own business at a Starbucks when I overheard two engineers complaining about Samsung 14nm shuttles being delayed. They had badges on but I won’t out them because it could have easily been any of the fabless companies in Silicon Valley since just about all of them are working with Samsung this time around, even Apple.

Another good source on who is using what foundry at 14nm and 16nm is LinkedIn. If you are a premium member you can do advanced searches for the fabless company of choice with “14nm”, “16nm” or “FinFET” as key search terms. Good thing TSMC chose a different path and named it 16nm so we can get better search results. You will find Apple, Qualcomm, Broadcom, Marvell, Nvidia, AMD, Cisco, LSI, Avago, Oracle, Freescale, Jupiter, SanDisk, etc… all of the leading edge fabless semiconductor companies.

Of course I have > 20k connections so it makes it a bit easier since hundreds of my 1[SUP]st[/SUP] connections are doing FinFETs. I’m told that LinkedIn caps connections at 30k so if you want to connect to me you had better not delay. I’m linked to the majority of the SemiWiki fan base so you can do the math on that one if you really want to know how many registered members we have.

Based on the LinkedIn searches I did, all companies designing with FinFETs are using TSMC 16nm. Most are also using Samsung 14nm but some are TSMC loyal customers, Broadcom, Oracle, and Xilinx to name a few. I couldn’t find a company that is only Samsung 14nm which supports my opinion that Samsung is being used as a price lever against TSMC. Of course when I say Samsung 14nm it includes GlobalFoundries as they have a “copy exact” version running up there in Malta, NY.

Try a “10nm” search and you may be surprised at how many people are working on it already. There is also mention of work at 7nm. You can search “Intel 14nm” and see that only Altera, Tabula, and Achronix are working on it. The other Intel Custom Foundry customers must not be doing the actual AMS and layout work yet or Intel is doing it for them.

The nice thing about Apple is that they have a set annual release schedule which is in September. In order to get wafers in time for a September 2015 iProduct refresh the designs must be taped out in Q4 2014 so fabless semiconductor professionals like myself now know for sure which foundry gets what iProduct next year. It is still fun however to watch the regular journalists go all tabloid on this to get cheap clicks for their advertisements. Some of those same journalists are STILL saying Samsung is providing Apple with 20nm parts which is not true.

Where will Apple Manufacture the next iPhone Brain?
by Daniel Nenni Published on 07-17-2013

The not so nice thing about Apple is that they seem to take unfair advantage of the supply chain. This comes from the legal action between Apple and GTAT over a VERY one sided sapphire display contract that may bankrupt GTAT:

“When GTAT’s management expressed their obvious concerns to Apple regarding the deal terms during the contract negotiations, Apple responded that similar terms are required for other Apple suppliers and that GTAT should: ‘Put on your big boy pants and accept the agreement.’”

Disclaimer: The LinkedIn search engine is not great so results may vary depending on who you are connected to and what type of membership you have.


Look who is Leading the World Semiconductor Business

Look who is Leading the World Semiconductor Business
by Pawan Fangaria on 11-08-2014 at 7:00 pm

A couple of days ago I was reading a news article which said how long the world economy will be dependent on a single engine to drive it; obviously that single engine is USA. If we consider the overall economy, definitely USA is driving it, and semiconductor is a large part of it. The semiconductor is driving electronics and that is attracting other countries across the globe to setup semiconductor shops, fabs to be specific; first to be self reliant and then to be able to supply to neighbouring countries. Sometime ago I had learnt that Chinese Govt has planned to spend ~$170B in 5 – 10 years to support chip industry within the country to reduce their import bill on semiconductor chips. India’s electronics import bill is also bulging and it has been planning since long to setup foundries to reduce chip import and develop electronics in-house. Anyway, that’s not the point; the point is who is leading this space.

What caught my attention when I looked at the IC Insights’ 2014 forecast preview reportof top 20 semiconductor companies’ sales figures for 2013 and 2014? While semiconductor industry is seeing robust growth of 9% with top 20 companies, 9 companies out of those are set to register double digit growth, and 3 companies, TSMCand Media Tekin Taiwan and SK Hynixin South Korea are set to register highest >20% growth.

Taking a closure look, I found interesting data; combine the three companies in Taiwan (TSMC, Media Tek and UMC) and two companies in South Korea (Samsungand SK Hynix) and you see ~34.5% of total sales ($89627M) of top 20 in 2014 are here! So what does it convey, with highest growth and lion’s share in total sales of top 20 semiconductor companies? Are these two countries set to drive the world semiconductor business?

Looking from a different angle, among the pure-play foundries, TSMC is the top manufacturer and supplier of chips. The only other pure-play foundry in top 20 companies is UMC, so can we say Taiwan is the leader in pure-play foundry business? They are the top suppliers for fabless companies around the world, and fabless, in my view, is the main driver of semiconductor industry today.

I see Intelat the top with 6% growth in ‘pure-play IDM’ category. Do we see Intel transforming more into pure-play now? Is IDM business sustainable?

I guess we may be able to see more detailed data when the final report gets published by the end of this month. It will be interesting to see the break up foundry, design and other businesses of Samsung and Intel, provided they publish those with break-up view.

I see that 2015 McClean Report is also scheduled to be released in Jan 2015 which has 400+ tables and graphs and there are seminars on the report scheduled in Jan, next year. It will be interesting to know about those details.

More Articles by PawanFangaria…..


Xiaomi Already #3 in Smartphones Behind Samsung and Apple

Xiaomi Already #3 in Smartphones Behind Samsung and Apple
by Paul McLellan on 11-08-2014 at 7:00 am

The Q3 results are mostly in now and there are two big stories. The iPhone 6 of course, which started shipping just before the end of the quarter. The other story is China, now the #1 mobile market in the world. These have led to very different stories for different companies.

Samsung is basically flat with Q2, but that was a big drop. Smartphones are such a large part of Samsung’s business it has affected overall corporate earnings. They are down a full 50% on revenues that are down around 20%. “its smartphone business lost ground in an intensely competitive global market”. They are still #1 with almost 25% market share (but they were over 30% recently) shipping around 78M smartphones.

Apple is still #2 of course, and they have said that they are shipping everything they can build. They sold 10M phones in just the first week of the iPhone 6 launch. Since they launched on 19th September that was all in this quarter. In total they shipped nearly 50M phones and very slightly gained market share. Q4 will probably be up since it will be the first full quarter with iPhone 6 and then, assuming Apple stick to making only one new phone per year, will creep down until this time next year.


The most amazing result is that #3 is Xiaomi, shipping 18M phones for close to 6% market share. Considering how recently they were created, this is amazing. All those phones sold in Asia, mostly China. They are eating Samsung’s lunch.

Chinese manufacturers also hold #4 #5 #7 #8 positions. Lenovo is #4 (and this is still without the Motorola Mobility acquisition from Google, which hasn’t closed yet). If it closes in Q4 and the numbers are all merged I assume they will be #3 in Q4, but Xiaomi is growing fast. Lenovo shipped 17M phones.

Huawei is #5 shipping nearly 17M phones. In fact some analysts have them ahead of Lenovo since the numbers are so close. And almost exactly the same number is LG (the second Korean entry into the table). Then Coolpad and ZTE.

Bringing up the rear are Sony, Microsoft and Motorola Mobility all with around 9M phones shipped, more or less.

What I think is happening is that at the high end of the market in the US, Samsung and Apple are doing very well. You certainly see a lot of Galaxy and iPhones around, although it is always wise not to assume that what you see in silicon valley generalizes to middle America. In US Samsung has 36% market share and Apple 26%. And as late as this time last year, Apple and Samsung’s profits together were 109% of the entire mobile industry, everyone else in aggregate losing money.

But Samsung used to be #1 in China and now Xiaomi is, at a much lower price point. The iPhone 6 didn’t launch in China until October so it has no impact on the Q3 numbers but Apple is an aspirational brand that everyone wants if they can afford it. Apple is wildly profitable, with Samsung struggling. Some estimates of Apple’s profits are as high as 85% of all the profit for the whole industry, but its challenge is going to be to keep growing as fast as the market so that its share stays relevant to 3rd parties (it is currently 12%). Android has close to 85% market share (across all the manufacturers) so Apple need to keep iOS desirable. Today, people seem to develop first for iOS and then port to Android, and Apple would like to keep it that way.

It doesn’t look as if Samsung’s position is likely to change very fast either. Kim Hyun-joon, senior executive at its mobile division, said:
the outlook for the fourth quarter in smartphones “wasn’t looking good” as competition will get fiercer. “That will probably hurt our profitability.”

Another small story is Microsoft (the old Nokia handset division) which had dropped out of the top 10 to fall behind Motorola but snuck past them again this quarter. But I still find it hard to believe that Microsoft, and thus WindowsPhone operating system, can get out of the basement at around 3%. As well as Microsoft, Samsung and ZTE do ship some phones with the WindowsPhone OS but less than a million units together. Blackberry (what used to be called RIM) is even lower at under 1% and also has to be doomed, although with their strong position in government and some corporations they presumably are an acquisition target at some point.

Oh, and Amazon? They took a $170M writeoff on their smartphone inventory. The Fire just didn’t seem to light. Amazon don’t publish numbers but some analysts reckon they only sold 35,000 in the first 25 days. Not quite up there with Apple selling 10M in a week. I reckon that means Apple sold as much as Amazon in the first 40 minutes.


More articles by Paul McLellan…


Bluetooth Smart Crashes IoT Party

Bluetooth Smart Crashes IoT Party
by Tom Simon on 11-07-2014 at 7:00 pm

When you hear the term Internet of Things the first image that comes to mind is, well, a lot of things talking over TCP/IP, maybe using WiFi or god forbid Ethernet. But upon closer examination it seems that Bluetooth is crashing the IoT party. This was driven home for me when my girlfriend gave me a FitBit Flex. For those unfamiliar, it is a tiny capsule of electronics that goes onto an inconspicuous wristband. It can help you track your activity and your sleep. Its accuracy and efficacy is probably fodder for another discussion. But it provides gratifying feedback.

FitBit has done some very clever things. It is dead simple to use, and it links directly to your phone or PC via a small dongle they provide. The real service goes through their website, where your data is aggregated and viewable. Though your phone can show you this info, the app must be signed into their site to work properly. So the FitBit is clearly a ‘thing’. And the internet is involved, but this device relies heavily on Bluetooth Smart, formerly BLE. Thankfully the Bluetooth SIG decided to get away from 3 letter acronyms for this technology.

Being a bit of a hardware hacker I was immediately curious about what was inside. Fortunately ifixit.com posted a teardown showing the device’s insides. It’s mostly what you’d expect: LiPo battery, ST’s ST32L151C6 ARM cortex M3, Nordic Semiconductor’s nRF8001 Bluetooth chip, an accelerometer, haptic feedback device and LEDs, etc.

Space is clearly at a premium. The whole thing is very compact and it looks like lots of 0402 and smaller SMT devices are crammed in. After seeing this I researched Bluetooth chips a bit. The growing trend is for the Bluetooth radio to be combined with the MCU. This is a very interesting development. Of course you need a software stack to run the radio, and certainly there will be application code for whatever the ‘thing’ is going to be doing. In one fell swoop you can a single device that has most everything you need to build a ‘thing’. You can use I2C to read sensors, you have GPIO’s to operate LEDs or other output devices. And, it can talk to your phone or computer!

Each company has a different name for it: Bluetooth MCU, Bluetooth SOC, etc. But now processor choice is becoming an important part of Bluetooth chip selection. And there are definitely different camps. TI unsurprisingly uses the 8051. Nordic uses ARM – mostly Cortex MO.Broadcom also uses ARM and you can get a Cortex M3. CSR is using something called Xap. And Intel seems to not have one yet. Witness that their Edison board has a separate WiFi/ Bluetooth combo chip. If they do have one it is not easy to find on their website. But when they do have one, I expect it will be Quark or Atom based.

So why did FitBit use a separate radio and MCU? They could have saved a lot of area on their very small board. I can think of a few reasons. Perhaps the application team and the RF team were separate and did not coordinate, as was suggest in an online interview I read recently. Or perhaps they needed the compute power of the Cortex M3 and when they were doing development the Broadcom chip was not available. FitBit is quite loyal to Nordic. Maybe they did not want to switch radios. They certainly have switched processors from product to product. Their initial products used a Freescale ARM core, instead of the ST ARM chip in the newer Flex. Interestingly though they use the TI Bluetooth SOC with an 8051 MCU for their PC dongle.

It will be interesting to see what comes in future products from the combining of microprocessors and radios in one chip. It is already making ripples in the maker community and allowing much easier product development and prototyping in small footprints.


Amorphous Silicon and TFTs

Amorphous Silicon and TFTs
by Daniel Payne on 11-07-2014 at 7:00 am

Most ICs are fabricated with crystalline silicon (c-Si), which is a tetrahedral structure forming a well-ordered crystal lattice. There’s another form of semiconductor material called amorphous silicon (a-Si) which has no long-range periodic order. It turns out that a-Si is a great material for the active layer in thin-film transistors (TFTs), used in most of our liquid-crystal displays (LCD) because it allows the manufacture over a large-area.

You can use either a planar or staggered structure for an a-Si TFT transistor:

The gate of a TFT device can either be structured on top or on the bottom:

Related – Silvaco at the TSMC 2014 Open Innovation Platform

The a-Si TFT device is sensitive to light, so shielding from incident light must be added:

If you’re interested to learn more about a-Si TFT devices and how to use TCAD simulations, then consider attending a webinar on November 18th, set for 10AM-11AM, Korea local time. It’s during the TCAD simulation phase that process engineers can start to predict critical electrical performance like leakage currents. At this webinar you can expect to learn about:

 

  • Basic concepts of a-Si TFT TCAD simulation
    • Basic equations
    • Physical parameters
    • Density of states model
  • TCAD calibration procedure example
    • Process and Device simulations for IV curve generation
    • Understanding and use of density of states models
    • Understanding and use of probability of occupation function
    • Correlation between density of states and current density

Related – SiC and Si Power Devices

Presenter
Silvaco
is producing this webinar live for the Korean market, however they will also be archiving the webinar on their web site for people to view. The presenter is Nam-Kyun Tak, a Senior TCAD Application Engineer from Silvaco. Nam-Kyun has been at Silvaco since 2010, where he worked on TFT technology development. Prior to Silvaco, he worked at Samsung Electronics for 6 years doing DRAM development.

Nam-Kyun Tak received B.S. and M.S. degrees in electrical engineering and computer science from Kyungpook National University, Daegu, Korea.

Related – TCAD to SPICE Simulation of SiC and Si Power Devices