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January 6, 2015

Intel: 2015 and Beyond?

Intel: 2015 and Beyond?
by Daniel Nenni on 01-06-2015 at 7:00 am
Categories: Foundries, Intel Foundry

Russ Fischer of Seeking Alpha fame just posted another article on Intel which, for a change, I agree wholeheartedly with except of course the part where he comments on the fabless semiconductor ecosystem, something he knows nothing about. But other than that it is definitely worth a read because as investments go Intel is certainly in a strong position.

Like me, Russ is a semiconductor professional although he is retired. Unlike me, Russ invests in the stocks he writes about which, in my opinion, is a questionable practice. Yes there is a disclaimer at the end but unfortunately blogs are quoted and cut/pasted all over the internet and the disclaimer does not follow.

According to Russ, we can ignore the non-mobile Intel Custom Foundry business (Altera etc…) as a growth driver which I agree with. Russ does however suggest that Intel could be a player in the mobile foundry business but of course that did not happen at 14nm. Given the problems Intel has had with 14nm yield on internal products it is not surprising the big fabless companies skipped it. You also have to ask yourself: Will one of the big SoC companies hand over designs to one of their fiercest competitors? Intel may not be a competitor for smartphone SoCs but tablets are another story completely (Core M and Cherry Trail). Flooding the SoC channel with 40 million “contra revenue” Bay Trails did not help either (scorched earth).

Russ also states that TSMC 20nm is all Apple with very little or no wafers going to all other customers. This is a complete Fischer Fabrication. CES will be filled with 20nm silicon from both TSMC and Samsung. I also noticed that the 64-bit SoCs being launched at CES this week use ARM Cortex A57/53 cores versus doing their own ARM implementation like Apple. Even the latest QCOM Snapdragon uses ARM versus their in-house Krait core which begs the question: Why?

Here is the funniest part of the article cut and pasted so the humor is not lost:

Intel: 2015 And Beyond:The non-Intel finfet business represented by TSMC and Glo Fo is in a serious state of confusion. The latest news is that Glo Fo will be delayed a couple of quarters on 14nm and that Apple is scurrying to figure out a solution. Glo Fo denies the delay.

Russ is the only one in a serious state of confusion here. This was a “rumor” and not “news” of course and it has since been debunked. Check the comments section of this blog:

GlobalFoundries did NOT Pull the Emergency Brake!

I have exactly zero direct knowledge of whether TSMC or Glo Fo will ever deliver finfet-based products in production volumes. I do know that neither company is delivering finfets today. We are down to the “fish or cut bait” time on non-Intel finfets. If TSMC and Glo Fo really can’t get a finfet process working pretty soon, Apple and others (under the new, “All customers for foundry” policy at Intel) will have no choice but to get involved with Intel.

This could be the ultimate solution to the smartphone problem; Intel gets it through the foundry.

Smartphone problem indeed. The funny thing is that when I read his articles they track with what I hear from the Intel PR machine and even the Intel executive staff. Seriously, Russ should come with an “Intel Inside” label. Here are some other famous quotes for perspective:

“Trigate? We are on our second generation, no one has figured that out, they aren’t going to figure that out.” Paul Otellini, Intel CEO, 12/2012

“TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed to mitigate leakage current.” Mark Bohr, Senior Fellow at Intel Corporation, 4/2012

“We’re going to introduce FinFET after the 20-nanometer planar. We’ve been working on FinFET for more than 10 years. We’re quite confident that we will have a robust FinFET technology.” Dr. Morris Chang, TSMC Chairman, 4/2012

To be clear: TSMC, Samsung, and GF are delivering risk production FinFET wafers today with volume production scheduled to start in Q2 2015. Fabless heavyweights Apple and QCOM are driving this effort at all three foundries so I have no doubt it will happen, absolutely.

January 6, 2015

Apples Versus Zebras

Apples Versus Zebras
by Scotten Jones on 01-06-2015 at 12:00 am
Categories: Foundries, Intel Foundry

I have seen a couple of posts comparing the density of the Apple A8 to the Intel Core M and concluding that the TSMC 20nm process is denser than the Intel 14nm process. In one of the threads one of the posters likened this to comparing apples to oranges, I agree except I think it is even worse than that, I think it is more like comparing apples to zebras and here is why:

Let’s start by talking about the elements one might see in a chip design on these advanced processes. First there are logic elements. Depending on the design goals, density, power, and speed the logic elements will vary in size. They will also vary in size versus SRAM cache and SRAM cache itself will vary in size depending on the goals even on the same process. For example, TSMC’s 45nm process has high density SRAM cache with a 0.202 um2 cell size and other SRAM cache (presumably high performance) with a cell size of 0.324 um2, a 1.6x difference on the same process! Intel’s 22nm SOC process offers HDC cache with a cell size of 0.092 um2, LVC with a 0.108 um2 cell size and HPC with a 0.130 um2 cell size, a 1.4x difference! And these are just a few quick examples from scanning published papers on processes. Analog circuit elements will also have a different density particularly when considering that elements such as resistors and capacitors aren’t even counted towards the circuit density.

I have analyzed seven different Intel MPU designs I have data on, all were produced on the same Intel 32nm process. The designs vary from just over 2 million transistors per mm2 to over 5 million transistors per mm2, a 2.5x difference in density on the same process for different MPU designs executed by the same company! To compare the Apple A8 design that has a completely different set of design goals to an Intel Core M on two different processes and conclude one process is more or less dense than the other is simply not a valid comparison. You would need two identical or close to identical designs on the two different processes to make a valid comparison and in this case that isn’t available. This is why at all the major technical conferences, all of the companies use design independent minimum pitches to compare processes.

Lately I have made several posts using the gate pitch x metal pitch metric to compare relative process density. This is a metric Intel has used in several recent presentations; IBM and the common platform alliance have also used it in their own technical papers. Even TSMC when disputing an Intel density advantage claim didn’t question the metric, they merely said Intel used old numbers for TSMC. The best and indeed only valid design independent comparisons of processes currently available are SRAM cell size and gate pitch x metal pitch which is why process experts use them.

I think it is fair to say that process experts generally agree that Intel has the densest 16nm/14nm logic process currently available, but so what? The more relevant question is whether Intel’s 14nm process is the best process and that depends on your design goals. Intel’s processes are first and foremost designed to produce Intel MPUs, and then the processes are adapted to make SOCs. TSMC processes are developed in close coordination with their customers and are specifically targeted at the SOC needs of those customers. I would bet money that if Apple knocked on Intel’s door and wanted to make the A9 on Intel’s 14nm process, Intel would be interested, in fact I would be surprised if Apple hadn’t at least evaluated that option. Apple makes the A8 on TSMC’s 20nm SOC process because they concluded that at the time they did the design that was their best option from a performance, price and delivery perspective for Apple’s design goals. I have no doubt the A9 sourcing decision will be made based on the same criteria.

Intel’s processes look different from TSMC’s processes because their design goals are different and TSMC’s processes look different than Intel’s process because TSMC’s customers have different design goals. TSMC is far and away the market leader in foundry and their process development is targeted at maintaining that lead. Intel is far and away the market leader in MPUs and their process development is targeted at maintaining that lead. One company makes apples and one company makes zebras, they both do it really well.

January 5, 2015June 14, 2019

Coventor Panel at IEDM Digs into Variation Issues

Coventor Panel at IEDM Digs into Variation Issues
by Tom Simon on 01-05-2015 at 7:00 pm
Categories: Coventor, EDA

Recently I attended a panel discussion on variability in semiconductor fabrication hosted by Coventor in conjunction with the IEEE IEDM conference in San Francisco. The IEEE bills the conference as “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling.” It’s easy to see how this discussion was relevant to the conference focus. SemiWiki’s own Dan Nenni was the panel moderator.

The panelists were John Wise from Lam Research, Jan Hoentschel with GLOBALFOUNDRIES, David Fried of Coventor, Jeff Smith for Tokyo Electronics NA, Tom Dillinger of Oracle Corporation, and Tomasz Brozek representing PDF Solutions. Each made opening comments, but the overriding theme was that variation is becoming a huge bottleneck for IC design and manufacturing. Paul McLellan has already written here about this panel, but I thought certain highlights were worth focusing on.

Tom Dillinger of Oracle spoke from the perspective of the design community, so I found his observations to be particularly interesting. He started out right away by saying that the device models are the most important thing. For FinFET you need to use BSIM-CMG models. BSIM-CMG comes with new parameters to indicate the number of fins. With additional fins comes “lots of parasitics.” Tom’s view is that for SRAM designers statistical models help a great deal with modeling variation. You have many copies of the exact same physical device. But with logic designs you introduce a wide variety of physical parameters that make predicting variation effects extremely difficult. FinFETs have finger counts and fin counts to factor in. With high fin counts it is necessary to reduce the parasitics in the models.

Tom feels that one of the models fall down because the fin is presumed to be rectangular. In reality it is a trapezoid or even a triangle. Also at more advanced nodes without EUV, moving to multiple patterning will introduce new sources of variation in devices. In fact a great deal of the Q&A after the panel discussion centered on whether EUV will become viable. There was no clear consensus on this point. There was agreement with Coventor CTO of Semiconductor David Fried’s statement that without a lightning bolt change from the current, 7 generation old, approach to lithography, that the only way to reduce the effects of variation is to work a ‘chorus’ of smaller improvements.

David Fried sees each discipline in the design and manufacturing process taking a silo based approach and specifying worst case parameters for the design. The result is expensive guard-banding that is probably overkill. It used to be that you could run batches of wafers and have a good idea about the variation problems you might encounter. With an exploding number of sources of variation, Fried asserts, it is impossible to run enough wafers. Jeff Smith of TEL America said that they use Coventor tools to identify the highest risk areas so they know what kinds of test wafers they should run. This makes it possible to find a manageable number of test cases to explore.

Fried also made the point that causes of variation are now masked so that it is harder to connect physical effects to yield results. The underlying physical effects can be misunderstood. This leads to overly conservative design guidelines. Not surprisingly, Fried called for a predictive approach, using simulation tools to better understand the underlying physics.

The panel discussion highlighted that we are at an interesting juncture. There was some talk about SOI versus FinFET, but the consensus was that FinFET on SOI will be the winner. So, going forward there are many questions. Will a cost effective lithography change come in time? How well will existing FinFET models work in production designs? Can excessive guard-banding that reduces cost effectiveness of new nodes be eliminated?

It promises to be an interesting year ahead.

January 5, 2015

QuickLogic betting big on sensor hubs

QuickLogic betting big on sensor hubs
by Majeed Ahmad on 01-05-2015 at 12:00 pm
Categories: FPGA, QuickLogic

QuickLogic Corp.—the former FPGA maker that reinvented itself through configurable design for consumer electronics (CE) products—is taking its sensor hub arsenal to high pitch at the 2015 International Consumer Electronics Show (CES) in Las Vegas. Sensor hub, a companion to application processor, offloads data from sensors and processes it to boost overall performance while saving power for the main processor. Sensor hubs serve always-on, always-aware sensor-based applications for smartphone and wearable products.

S2 Sensor Hub Block Diagram

The Sunnyvale, California–based company is demonstrating its latest sensor hub solution—the ArcticLink 3 S2—along with reference designs and evaluations kits at the MP25452 booth in South Hall 2, Las Vegas Convention Center. QuickLogic is also participating in a MEMS Industry Group panel at the CES.

QuickLogic engineers call their sensor hub chips customer specific standard products (CSSPs) and claim that they have an edge over competing solutions that are either based on MCUs or ASSPs. They point to the fact that the MCU-centric approach is entirely based on software that uses more power than hardware. The company spokesman asserted that QuickLogic’s ArcticLink 3 S2 chip consumes 95 percent less active power than typical MCU-based sensor hub solutions.

On the other hand, alternatives like ASSPs, while they are power savvy, they don’t have the inherent flexibility to adapt sensor hubs to emerging applications like gesture and context awareness. QuickLogic engineers say that their hardware-based solution offers greater power efficiency, and its programmable fabric enables greater flexibility to add upcoming features and adapt to design changes.

Furthermore, QuickLogic engineers maintain that the fact that ArcticLink 3 S2 sensor hub consumes only 150µW, which makes it ideal for the always-on, always-aware smartphone and wearable applications. The company has also joined hands with Bluetooth Smart chipmaker Nordic Semiconductor, and the collaboration of the two semiconductor firms has led to the creation of TAG-N wearable sensor hub evaluation kit.

Nordic nRF51822 Development Kit

“The kit incorporates QuickLogic’s ultra-low power sensor hub, related algorithms, and a direct connection to a Nordic Semiconductor multiprotocol development kit for its nRF51822 SoC,” said Frank Shemansky, Senior Director of Product Management at QuickLogic. “The resulting wearable reference designs are suitable for quick prototyping, demonstration and testing of monitoring, context and gesture algorithms.”

Context and gesture solutions
QuickLogic spokesman said that the TAG-N development kit aided by pedometer, gesture and context algorithms could help OEMs significantly accelerate product development cycles. He added that QuickLogic’s context, gesture, and transport algorithm library includes pedometer accuracy, context awareness, and more.

S2 Sensor Hub Context and Gesture Solution

QuickLogic President and CEO Andy Pease said, “The context and gesture solutions available through sensor hub will enable a wide variety of apps ranging from motion detection to enhanced pedometer.” Take pedometer functions, for instance, which are the foundation of witness and wellness apps. A pedometer helps the application processor determine if a user is walking or running and does the step count for each condition.

Gesture requires no verbal communication while context is the state of being that doesn’t need an immediate response. And both gesture and context need to be accurate. QuickLogic has developed sensor algorithms for activity, gesture, location and transport contexts. These algorithms work as a baseline along with third-party and OEM-developed algorithms in an integrated development environment that provides software engineers with an easy-to-use way for deploying algorithms to hardware.

Image credit: QuickLogic Corp.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

January 4, 2015July 18, 2025

Prototyping Kits to Accelerate IP Development & Integration into SoCs

Prototyping Kits to Accelerate IP Development & Integration into SoCs
by Pawan Fangaria on 01-04-2015 at 10:00 am
Categories: EDA, IP, Synopsys

With growing SoC size, complexity, software and hardware content in it and shrinking time-to-market, the SoC design completion in time has become increasingly dependent on IP which need to be sourced (internally or externally), customized according to the design need and integrated together into the SoC. While IP providers can provide best optimized IP with good configurability and flexibility, its integration into SoC is not a straight forward task; it needs significant amount of work to consider various configurations, negotiate with significant amount of legacy design, adhere to frequent changes in standards and protocols, optimize, prototype and validate it in an SoC context before its integration into the SoC. How to do it when the final SoC is not yet available?

That’s the beauty of EDA vendors getting into the shoes of IP providers to provide complete automation to make an IP ready to be integrated into an SoC as fast as possible. While Synopsys, over a couple of years, has built a strong IP portfolio, it is now marching into accelerating the IP integration into SoC through several of its programs under “IP Accelerated Initiative”. Synopsys is providing DesignWareIP Prototyping Kits for several IP titles to accelerate designers’ IP prototyping, software development, and integration into SoCs. A Kit specific to an IP comes with proven reference design that can be used to explore design trade-offs with specific configurations of the IP, optimize the IP and validate it with fast iterative flow. The same design can be set as a target for early software bring-up, debug and test.

Above is an IP Prototyping Kit for USB 3.0 Device Controller. The Kits, in general, include Synopsys’ HAPS-DX FPGA based prototyping system with proven reference design, pre-configured IP, necessary SoC integration logic, PHY daughter board, simulation testbench, reference drivers and application examples along with either a connection to host PC (running the target OS) or DesignWare ARC processor based 32-bit software development platform running Linux. Assisted with Synopsys’ coreConsultantIP configuration tool, ProtoCompiler DX development and debug tool, and several scripts, designers can instantly modify and optimize the IP configuration, develop drivers and other software and accelerate integration of the IP into the target SoC.

The USB 3.0 Kit has been observed to be working excellently in customer’s design environment. It accelerates driver and software development early for customers to advance their schedule for FPGA validation by several weeks.

There is an example of a DDR IP Subsystem consisting of memory controller, communication ports, PHY block and so on, each of which requires configuration at hardware and software levels to ultimately define permissible functionality, range of registers, and connectivity characteristics and so on. While an FPGA image rebuild or even simulation (that involves OS setup, loading, initialization, accessing proper communication busses and debugging) for any hardware change can take several hours to days, the IP Prototyping Kit can accelerate iteration cycles by providing IP reference designs in a tested environment that allows fast exploration of different configurations through hardware-aware development tools. Look herefor more details on the Kit for “DDR uMCTL2 and Gen2 multiPHY with ARC Software Development Platform”.

Today, Synopsys provides DesignWare IP Prototyping Kits for multiple interface protocols including USB 3.0, SSIC, PCI Express 3.0 and 2.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI 2.0, and JEDEC UFS. Through these Kits, the designers need not spend much time in learning about the internals of IP and other details. A Kit provides ready environment for designers to implement an IP in an SoC context instantly, thus boosting their productivity which helps them in meeting challenging time-to-market.

Secure Microprocessors the Andes Way

Secure Microprocessors the Andes Way
by Paul McLellan on 01-04-2015 at 7:00 am
Categories: Andes Technology, IP

Microprocessor vendors such as Andes have been saying for some time that security requires extensive hardware support. In particular, embedded processors in intelligent sensors inside IoT chips are now popular targets for hackers, who find it easy to change the program code and system parameters to alter the operation of the sensor or to use the system for their own purposes. Every time a major breach occurs, like the recent infiltration of Sony, the message that security cannot be left in software only becomes stronger.

There are different levels of hardware support for security. At the lowest level, the encryption keys need to be kept in hardware and the access carefully controlled. But there are a lot of other more subtle ways to attack a microprocessor-based system.

One point of vulnerability to hackers in an embedded system is the JTAG interface. An attacker able to put the system into debug mode has complete control of the system with complete access to the CPU’s registers, program memory and another memory in the system. To provide protection of embedded software and program data while keeping the debugging capability, Andes secure debugging feature requires pass code validation. Anyone accessing JTAG port must provide a pass code, which can be provided in a static or dynamic form. A static pass code is stored in non-volatile memory in the chip. Anyone attempting to access the JTAG interface must provide the stored code. The other alternative is storing the pass code on a remote server and anyone accessing the JTAG port must acquire the pass code from the server.

Another point of vulnerability in an embedded system is the memory interface brought out to the pins on the packaged part to access external memory. By probing the interface pins with a logic analyzer, attackers can capture all the traffic passing between external memory and the embedded CPU. To secure the memory interface, the Andes secure MPU scrambles the data and/or address thus displaying random information to a logic analyzer probe and making it impossible to copy the memory contents without the encryption key.

A third technique used to hack into embedded designs is differential power analysis. This is a technique developed by Cryptography Research and works by looking at the power consumption of the system cycle-by-cycle and by looking at small differences in repetitive operations (such as DES encryption) to try and deduce, for example, the key. It is especially important to protect against in smart cards, which are used in credit and debit cards in most of the world (and probably coming soon in the US). The Andes solution is to randomize the power profile to eliminate the repetitive patterns, thus making the CPU less vulnerable to this type of hacking. One technique used to achieve this result includes a hardware random-bit generator that randomizes the internal clock signal. Another technique is to use a hardware random-bit generator to schedule per instruction cycle between two or more threads of execution that run on the MPU’s register sets.

Of course security is a sort of war in which the attacks never get weaker. Andes continues to enhance their microprocessor solutions to keep their security strong.

Update: Who will manufacture the Apple A9?

Update: Who will manufacture the Apple A9?
by Daniel Nenni on 01-04-2015 at 12:00 am
Categories: Foundries, GlobalFoundries, TSMC

Last August I presented possible scenarios for the manufacturing of the Apple A9 processor. Quite a bit has changed since then so I think it is worth revisiting. There has also been quite a lot of misinformation in the press which is now pretty much a daily thing. Attending the IEDM conference last month really was a stark difference than what “The Google” has to offer people who are looking for answers in all the wrong places. Seriously, the chasm between the two sides (semiconductor professionals and non-professionals) really is quite large.

Also Read: Who will Manufacture Apple’s Next SoC?

As we all know Apple has disrupted many different industries with innovative technology and aggressive business practices, the semiconductor industry included. Apple is now one of the largest and most innovative fabless semiconductor companies and becoming part of their supply chain is bringing a whole new level of competition amongst the fabless semiconductor ecosystem. Let’s start with last year’s blog Samsung ♥ GLOBALFOUNDRIES.

You have to ask yourself why Samsung REALLY did this deal with GF? One theory, which I firmly believe, is to get the Apple SoC business back from TSMC. Apple amongst many others (myself included) really wants GF to be successful for the greater good of the pure-play foundry business. Take a look at the last paragraph I wrote:

An interesting thing: On one side of the briefing table was Ana Hunter, Vice President of GLOBALFOUNDRIES, formerly Vice President Foundry, Samsung Semiconductors. On the other side was Kelvin Low, Senior Director, Foundry Marketing Samsung, formerly Director Product Marketing, GLOBALFOUNDRIES. It’s a small world after all.

Ana Hunter was instrumental in the foundry relationship between Samsung and Apple so who better to bring Apple to GF? Since the GF 14nm is a copy exact version of the Samsung 14nm, Apple has two manufacturing sources for the A9. And from what I learned at IEDM, both are now yielding in time for the next iPhone launch (September 2015). The Apple A9X (higher performance version) is still slated for TSMC 16FF+. This chip will go into tablets but may also be seen in laptops and possibly a high performance version of the iPhone making it a much higher volume chip than originally expected.

Yes I know Barron’s is still repeating that the foundries have not figured out FinFETs leaving the door wide open for Intel blah blah blah… absolute nonsense:

“Could Intel (INTC) be in a position to be Apple’s (AAPL) savior? That intriguing bit comes from Drexel Hamilton’s chip analyst Rick Whittington, from a note on Micron. In passing, Whittington notes problems had by Taiwan Semiconductor (TSM) and Samsung Electronics (005930KS) trying to produce 3-D transistors. Intel has mastered 3-D transistors, and so, writes Whittington “btw, very good for Intel if neither Samsung or TSM can do FinFET this next year; puts them in line to supply Apple’s internal foundry needs; more likely TSM/Samsung operate FinFET under very low yield output, keeping capacity tight.”

Yet another analyst pretending to be a semiconductor professional…..

Again, Samsung, GlobalFoundries, and TSMC are now yielding FinFETs with high volume production starting in Q2 2015. The next versions of iPhones and iPads will be FinFET based, absolutely.

January 3, 2015

Is the Internet of Things just a toy?

Is the Internet of Things just a toy?
by Bill Boldt on 01-03-2015 at 5:00 pm
Categories: Foundries, IoT

The Internet of Things (IoT) is arguably the most hyped concept since the pre-crash dot-com euphoria. You may recall some of the phrases from back then such as “the new economy,” “new paradigm,” “get large or get lost,” “consumer-driven navigation,” “tailored web experience,” “it’s different now,” among countless other media fabrications.

The IoT is the new media darling. In fact, it has been dubbed everything from the fifth wave of computing, to the third wave of the Internet, to the next big thing, to the next mega-trend, to the largest device market in the world, to the biggest efficiency booster/cost reduction technology. You get the picture.

Now, the question is whether or not the IoT will indeed be more real than just hype, as is the case with any media powered feeding frenzy. Let’s start by looking at the numbers.

Respected market researchers and giant networking companies are predicting gigantic numbers of connected devices to the tune of 20 to 50 billion units of installed base by 2020 or 2025, with some estimates even going higher. With numbers like that coming from the world’s most-followed, reputable sources, it won’t be long before high roller investors start placing enormous bets on who will be the winners of the IoT game; a game that will be make Vegas action look like a game of marbles. The IoT casino is now open.

There is really big money at stake because IoT represents a perfect storm of opportunity for venture capitalists and bold corporate acquirers — that is because many believe that half the successful IoT companies don’t even exist yet. Conditions don’t get much more attractive than that when it comes to risk capital.

Here’s a hot tip: Only bet on the companies offering systems that articulate a clear strategy that put strong security (especially authentication) as a top priority. This tip is derived from the observations of Dr. Vint Cerf (the acknowledged creator of the Internet) who declared that the IoT will require strong authentication. And, he’s right. Note well that the strongest authentication comes from hardware-based cryptographic key storage because hardware key storage beats software-based key storage every time. Inexpensive and easy-to-use integrated circuit devices already exist to do just that. The media should grasp that but don’t seem to get it yet.
The dirty little secret of the constantly-connected era is that without security, the IoT will just be a toy that consumers, governments, and corporations cannot take seriously. What good is a system of billions of interconnected things sensing and sending data (often through the cloud) that can be intercepted, corrupted, and spoofed? Not very much. IoT growth is dependent upon security.

Charting the Growth
The graphs below show estimated unit shipments and the resulting installed base of IoT devices. What has also been called out in each chart are devices with on-board security, mainly hardware-based security, and those that do not have built in hardware security. Most market estimates out there tend to show the growth of the IoT in terms of installed bases, growing to many billions by 2020. Typically speaking, you will see a chart like the one below, but without the divisions between secure and insecure nodes.This is a case of the devil being in the details, because installed base charts can be very misleading. Data jockeys such as market researchers and statisticians know very well that installed base is a tricky way to present data. Fair warning: Beware of drawing conclusions from installed base charts only.

The IoT case is a perfect example of how to hide the important information, because even if you remove the secure nodes, the chart still looks like there will be enormous growth. However, that masks the fact that growth will plateau without the secure nodes being a part of the picture. It is a an illusion caused by the fact that the early days of the IoT will build a base of significant numbers, but the volume shipments will fall off quickly as users reject insecure solutions precisely because they are insecure.

The installed base IoT chart is analogous to chart of automobiles in the time of Henry Ford showing the installed base of black cars (remember Model Ts came in any color as long as it was black). That would show that black cars were the overwhelming color and it would be impossible from that chart to conclude anything other than they always would be. Obviously, such a chart would mask the market changes that in fact happened and the inflection points as to when the changes happened. Masking is exactly what the IoT installed base chart does.

It fails to show that the inflection point towards secure nodes that is starting right now, which is a shift that will happen quickly. Reason being, the need for security is becoming clear (just ask Sony, Target, Home Depot, JP Morgan, and Iranian nuclear scientists about that). As aforementioned, inexpensive hardware-based devices are available now that can provide strong security to IoT nodes.

The unit shipment slide is what tells the real story. And, that is that security is becoming a requirement of IoT if growth is to be sustainable. Simply stated: Without real security, the IoT will falter.

Security Maters
Security matters because users must trust that the nodes are who they say the are (i.e. are authentic). Additionally, confidentiality of the data is important to keep unauthorized third parties from getting the data and misusing it. Also, without data integrity mechanisms there is no way to ensure that the data have not been tampered with or corrupted. All three of these matter. A lot.

However, with all the press that the IoT receives and all the tremendous predictions of giga-volumes, you just don’t hear much other than passing comments about security. Security should, in fact, be the prerequisite of any article, discussion, or plan for IoT-based anything. Talking about the Internet of Things without addressing the security question (with specifics) is like talking about scuba diving without mentioning water.

Security gets short shrift even though it is pivotal to the IoT’s existence (and important to literally everyone in the digital universe, including the readers of this article). One main reason is that the meaning of security is not really well understood. As a result, engineers, executives, investors, and researchers alike have been mainly whistling past the graveyard hoping that their digital interests will not be attacked too badly. However, with the increasing frequency, variety, and creativity of security breaches and especially with the advent of breach-based litigation, the danger is increasing and finally more attention is getting paid. It is not hard to envision ambulance-chaser legal firms moving from class action suits regarding asbestos, medical devices, and pharmaceuticals to seeking data-breach damage rewards. In actuality, this has already started. You can almost hear the cloying ads already.

Security Defined

There are two important and fundamental questions about security and the IoT:

1. What is IoT security?
2. How do you implement it now?

To address the first item, the best way to understand it is to break it down into the three pillars of security, which are confidentiality, data integrity, and authentication (ironically referred to as “CIA”). The second inquiry is related directly to the first because implementing security is a function of how well you address the three pillars.

It is critical to address security right now because because putting insecure systems into the world is just asking for trouble. There is no time to wait. Assembling a network or product dependent on a network that is filled with vulnerabilities is bad practice. The good news is that thanks to cryptographic engine integrated circuits with hardware-based secure key storage powerful solutions are clear and present.

Crypto Engines
Crypto engines refer to a dedicated integrated circuit devices that handle crypto functions such as hashing, sign-verify (e.g. ECDSA), key agreement (e.g. ECDH), authentication (symmetric or asymmetric), encryption/decryption, message authentication coding (MAC), run crypto algorithms (e.g. elliptic curve cryptography, AES, SHA), and perform many other functions. The other critical part of the equation that makes crypto engines so valuable is their ability to store cryptographic keys in ultra-secure hardware. (The CTO of a major home networking company recently described storing cryptographic keys in software being like storing a key in a wet paper bag.)

Providing the exact type of security needed for the IoT to grow is what crypto engines like CryptoAuthentication solutions are all about. They make security both easy and cost effective. The amazing thing is that crypto engine devices were invented before the IoT even existed. Now they are arguably the ideal catalyst to drive IoT growth when they are added to the other fundamental elements of the IoT. So, it should be clear that there are now four elements to a serious IoT node:

1. Intelligence (microprocessors)
2. Communications (Wi-Fi, Bluetooth, etc.)
3. Sensors
4. Security

These four items will be the recurring theme of IoT nodes. The story from here will be which communications standards are supported, the level of integration, how security is handled (standards and methods), performance, speed, power, size, etc., not if security is there or not.

Long story short: While some sort of IoT is possible without security, without security it would really just a toy.

Bill Boldt, Sr. Marketing Manager, Crypto Products Atmel Corporation

January 3, 2015

IEDM: FD-SOI Down to 10nm

IEDM: FD-SOI Down to 10nm
by Paul McLellan on 01-03-2015 at 1:48 pm
Categories: FD-SOI, Foundries, STMicroelectronics

The big picture is that planar semiconductor transistors don’t really work below 20nm. The reason is that the gate does a poor job of controlling the channel since too much channel is too far from the gate and so there is a lot of leakage even when the transistor is nominally off. So the channel needs to be made thinner. One way to do this is to make it into a thin fin and wrap the gate around it. That is what Intel, IBM and TSMC have all done and I reported on their papers at IEDM last month.

See IEDM: TSMC, Intel and IBM 14/16nm Processes

The other alternative is to build the channel as a thin layer on an insulating wafer (SOI). This is the approach that has been pioneered by ST Microelectronics and its partners. They also presented at IEDM in a paper entitled FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10um Node. The paper has a long list of authors from ST, CEA-LETI, IBM, Soitec, and Albany Nano Tech.

Planar fully depleted silicon-on-insulator (FDSOI) technology represents an important device architecture for continued CMOS scaling. Its advantages include excellent short-channel electrostatics, un-doped channels and effective back bias for performance boost and leakage lowering. Moreover, FDSOI is fabricated using a more conventional, lower-cost process than more complex FinFET architectures. Researchers from STMicroelectronics and the IBM Technology Development Alliance discussed the successful implementation of strained FDSOI devices with gate lengths, spacers & buried oxide (BOX) dimensions compatible with design rules of the 10nm technology node.

Two additional enabling elements for scaling FDSOI devices to the 10nm node were reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also will report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 μA/μm for NFET at Ioff=1 nA/um, and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 μA/μm at Ioff=1 nA/um.

Facts Support New Emergence in Semiconductor Landscape

Facts Support New Emergence in Semiconductor Landscape
by Pawan Fangaria on 01-03-2015 at 9:00 am
Categories: EDA, Foundries, General, IoT, IP, Mobile

As we left an exciting year 2014 which is poised to record 7+ % increase in semiconductor revenue (~ $338 B) compared to 2013 (~ $315 B) and entered into another promising year 2015 for semiconductors, I looked back over the year bygone and collected inferences from some of the major important events which clearly convey how 2015 can be pivotal to provide momentum to some of the newer areas ushering semiconductor landscape into newer territories. Although we hear about many hot topics on our way, but few make it to the finishing line; that’s a reason I tried to assimilate things in the complete ecosystem, see how they have performed in the past and how they connect together to ascertain real completion to finish lines for some of the larger goals in the industry.

Before I get into details, to sum up there are a few areas which will see maximum activities and they can provide enough thrust to transform semiconductor industry to newer heights – these are IoT (Internet-of-Things), I would say internet of everything market, smartphone market and system level EDA (we may call it ESL) including IP to support those markets. Well these are not new things I am talking about; we have seen these on our way. What is interesting is that when I looked at how things have progressed so far, they convince me that there is a great momentum, technically as well as businesswise, pushing these three areas to finishing lines. They are going to transform semiconductor industry into newer growth zone for at least next decade. Let’s see how things are folding into these three major dimensions which are interrelated.

On the macroeconomic front, with a few consecutive years of consistent, nominally increasing semiconductor revenue (in 2013 it was 5+ % increase compared to 2012) on top of significant investment in newer technology and process nodes, we can safely assume that we are on the side of growth curve in semiconductors.

The businesses responds according to macroeconomic scenario after taking into account the forward earning cues. Consolidation and expansion are typical of businesses in particular areas based on their life cycle stages. When the semiconductor economy was in decline or trying to come out of recession, we saw mega consolidation in existing EDA and design spaces including foundries (we have seen GLOBALFOUNDRIESacquiring IBM’s foundry business even in 2014) and semiconductor equipment arena. Now we are seeing business leaders expanding in newer areas such as IoT related technologies, IP and system level EDA that includes system prototyping, verification and reliability. Smartphone market remained in the middle with large scale consolidation as well as new entrants eyeing to capture the remaining low-price-point market. Below I will talk about both businesses as well as technical angles for each of these three areas – smartphone, IoT and system level EDA (including IP).

Smartphone – Lenovobought Google’s Motorolaunit, Microsoftbought Nokia; those are towards consolidation. We see a major expansion side too with Xiaomi, OnePlus, Huawei, Gionee, Google Android1 phones and many others. The smartphone market will keep on seeing major revenues. The technical angle to this is that smartphone will play a pivotal role in the expansion of IoT devices in several sectors including personal, home, social, industrial, health, automotive, and so on. Most of the IoT devices will be controlled through smartphones, and therefore the companies who provide best IoT enabled smartphones will be the winners.

IoT – This is a major expansion space at different levels – enterprise, medium and low scales. Google bought Nest Labsthat provides home automation technologies such as thermostat and smoke detection; CEVAacquired RivieraWavesthat specializes in IP for connectivity with smartphones through WiFi and red-hot Bluetooth; MegaChipsacquired SiTimethat has 80% share in MEMS timing solution; NXPis to complement its IoT portfolio with Quintic’sassets and IP related to wearable and Bluetooth Low Energy (BTLE) business; Qualcommis buying CSR(a pioneer in Bluetooth wireless technology to connect devices to smartphones) to expand in technology for connected appliances; earlier Qualcomm bought Wilocity, which makes WiFi products for home internet routers and appliances that connect to the web. Qualcomm also developed an open source platform, AllJoyn for connected devices to work together.

This is not all, there are major activities going on in this space in several companies, either in-house or through acquisitions. We are going to see major technological moves to solve security issues, large data management (storage, filtering, secured transmission, access, privacy, and so on), communication protocols, standardization in software, o/s, devices optimized on several parameters and so on.

System level EDA – Last year has seen EDA leaders getting into ESL related and system level reliability, verification, optimization, and application areas with renewed fervor. Cadencebought Forteto strengthen HLS solution and Jasperto expand complex system verification solution. Mentorwent on to further expand its automotive section, acquired Mecel Picea AUTOSAR Development Suite from Mecel AB; acquired XS Embedded GmbH, a leader in creation of automotive system architectures and hardware reference platforms. Mentor strategically eyed on system reliability space, acquired Nimbic, a leader in 3D full-wave electromagnetic simulation solutions that provides signal integrity, power integrity and EMI analysis for systems on scalable cloud compute platform. To strengthen SoC design and verification flows further, Mentor acquired Certus ASIC Prototyping Debug Solution that addresses challenges in FPGA prototyping. Also Mentor acquired Berkeley Design Automation to advance nanometer AMS verification. Synopsysis not behind in acquisitions, it acquired Target Compiler Technologies that strengthens its ARC Designware family by enabling design and programming of ASIPs (Application Specific Instruction-set Processors).

Synopsys and Cadence have already made strong portfolios in IP. While providing system level automation for SoCs, it’s strategic advantage for them to have IP portfolios. Cadence went ahead buying high speed interface IP assets from TranSwitch. ARM, being an IP leader, went ahead acquiring Duolog to strengthen its IP configuration and integration capabilities addressing increasing SoC complexities and sub-system functional verification.

There are many other activities happening around the world in IP, system level automation, and connectivity between things and internet. It’s clear, EDA and IP providers are vying to fill the gap between chip design and system design by providing robust and reliable IP and seamless automation for prototyping, optimization and integration of SoCs; the design houses are striving towards providing complete and secure systems of connected devices; smartphone makers will be gearing up to catalyze the IoT phenomenon by enabling connections between devices and the web through their smartphones; and foundries are already on their march towards providing light weight, low power, high performance devices suitable for IoT.

Let’s watch for more trends evolving in this direction in this year. Wishing the semiconductor community an exciting 2015!!