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January 2, 2015June 14, 2019

WLAN Design Optimization at Lantiq

WLAN Design Optimization at Lantiq
by Daniel Payne on 01-02-2015 at 7:00 am
Categories: EDA, MunEDA

Right now I’m typing on my MacBook Pro computer connected to the Internet through WiFi, thanks to the electronics in both my laptop and WiFi router. I kind of take WiFi for granted because it is so ubiquitous throughout my daily life, yet there are IC designers at companies like Lantiq Semiconductorthat have to design and optimize for WLAN specifications like 802.11ac by designing RFIC devices. Last month at the MunEDAUser Group meeting in Munich I attended a presentation by Daniel Lopez-Diaz, a senior engineer in the RF design group at Lantiq.

Lantiq was founded over 20 years ago and has grown into a successful fabless company with 800 people, focusing on high-speed broadband, connected home, home automation and voice products. Here’s the big picture showing how everything fits together:

They have a reference board used in WiFi router products with just a handful of highly integrated components:

EASY362 V1.1 Reference Board

The WLAN chip supports the 802.11ac standard, operates on a 5G frequency band, and has RF bandwidths of: 20MHz, 40MHz, 80MHz and 160MHz. These requirements translate into a transmitter with a Power Spectral Density (PSD) that looks like:

Power Spectral Density

Another important spec is the minimum performance as the Error Vector Magnitude (EVM), also called the Relative Constellation Error (RCE) – measured in units of dB:

Error Vector Magnitude (EVM)

The RFIC design team needed to verify the performance over a range of Process, Voltage and Temperature (PVT) conditions to ensure that the WLAN chip would be robust and yield well. Combinations of intra-die and inter-die variation could result in unrealistic process parameters. The approach used by the team was to create an iterative sign-off process using EDA tools from MunEDA called WiCkeD.

Iterative Design Flow

A simplified RF block diagram is shown below with the Transmit Mixer portion highlighted for analysis.

Simplified RF Block Diagram

The Transmit Mixer block has two main specifications:

Conversion Gain (CG) of -3dB, typical
1 db Compression Point (P1dB) of 7 dBm, minimum

At the first design review it was shown that the specifications were not quite met:

[TABLE] style=”width: 500px”
|-
| Case
| Process
| Voltage
| Temperature
| CG
| P1dB
|-
| Initial
| TT
| 1.26V
|
| -2.22 dB
| 10.17 dBm
|-
| Slow
| SS
| 1.2V
| 110 C
| -4.18 dB
| 10.2 dBm
|-
| Fast
| FF
| 1.32V
| 10 C
| -1.62 dB
| 10.77 dBm
|-

Further analysis using Worst Case Distance results instead of corners for Conversion Gain and 1 db Compression Point showed:

[TABLE] style=”width: 500px”
|-
| Case
| Voltage
| Temperature
| CG
| P1dB
|-
| Fast
| 1.32V
| 10 C
| -1.63 dB
| 12.09 dBm
|-
| Slow
| 1.2V
| 10 C
| -4.292 dB
| .5705 dBm
|-

Engineers quickly spotted that with Worst Case Distance analysis the result for P1DB was out of spec, so it meant three possible choices:

[LIST=1]

Re-center the design to meet the spec

Re-size the transistors to meet the spec

Relax the specifications

Conclusions

RF design optimization for a WLAN chip is possible by using a Worst Case Distance approach as found in the WiCkeD tool from MunEDA. Designs can be analyzed for robustness prior to tape-out.

January 1, 2015

IEDM Advanced CMOS Technology Platform Session

IEDM Advanced CMOS Technology Platform Session
by Scotten Jones on 01-01-2015 at 7:00 am
Categories: Foundries, Intel Foundry, TSMC

First I want recognize that IEDM once again provided all of the attendees with the proceedings as soon as we arrived at the conference, in fact the proceeding included every year of IEDM back to 1955. This is how a conference should be run! Anyone who read my blog about the SPIE Advanced Lithography Conference will know how frustrating I found SPIE not making the proceeding available until months after the conference. SPIE really needs to fix that! Being able to read the papers before a session and then review them again after the session is really helpful.

There were three papers in the Advanced CMOS Technology Platform session that really caught my attention this year.

TSMC
First up was TSMC presenting their 16FF+ technology. The process presented this year provides a 15% speed improvement at the same power or a 30% power improvement at the same speed versus the 16FF process presented at IEDM last year. All of the critical dimensions disclosed for this process are the same as 2013 (48nm fin, 90nm gate and 64nm M1 pitches). The level of performance improvement TSMC has achieved is more in-line with what you would see for a new node and to achieve this level of improvement while maintaining the same critical dimensions is really an achievement. Unfortunately from my perspective the paper only discussed the results and didn’t provide any details on how they were achieved other than to say they focused on reducing capacitance. Still the results are impressive!

Intel
The next paper that really caught my attention was the Intel paper on their 14nm technology. Intel’s 14nm technology is the densest 16nm/14nm class process currently available with 42nm fin, 70nm gate and 52nm metal pitches. The gate pitch x metal pitch metric is 0.51x the 22nm technology, IDsat is 15% better for NMOS and 41% better for PMOS. Active power is 30% better than 22nm with 10x better tddb and less Vt variation.

Once again there wasn’t a lot of detail presented about the process but there were a few interesting disclosures:
[LIST=1]

The process uses solid source doping to dope under the fins. My belief is that the STI trenches between the fins are filled with doped glass that is then etched back to the bottom of the fin and then annealed to out-diffuse the dopants. I would expect both p and n doped glasses would be required. I have come up with one integration scheme that does this without additional masks but it would result in topography at the bottom of the wells. I think it is more likely one additional mask would be needed.

Air gaps are used on two of the interconnect layers. Data was presented for delay improvements for metal 4 – 17% and metal 6 – 14%. Interestingly my understanding is that analysis of actual Intel products in the field has found the air gaps on layers 5 and 7. During the presentation it was also disclosed that a mask is needed for each air gap. After the paper someone asked how this is done and author declined to comment. Based on cross sections and the one mask per air gap disclosure it seems likely that this is the process Intel described in 2010.

I was surprised when it was first disclosed that this process has 13 metal layers. Intel used 6 metal layers at 180nm (aluminum) and 130nm (copper), 7 layers at 90nm, 8 layers at 65nm and 9 layers at 44nm, 32nm and 22nm. I was expecting 10 metal layers at 14nm. I think what has happened here is that Intel has moved to SADP for critical metals layers and SADP really only produces gridded lines and spaces for a 1D layout. This has likely required additional metal layers versus previous 2D metal layers.

During the presentation Intel briefly displayed the pitches for all the metal layers. Unfortunately it wasn’t up long enough for me to copy down the numbers and unlike many attendees I respect the no photography rule. The pitches are also not in the paper. I have seen measured pitches on products in the field but I can’t share them yet. I will say that I saw a report on EE Times that the process has 8 layers of 52nm minim pitch metal, it actually has 5 layers of minimum pitch metal.

Intel has previously stated that the 14nm process wafer cost is 29% higher than the 22nm wafer cost. I have a really hard time reconciling that number with all the added masks at 14nm. First there are 8 mask layers required for the additional 4 metal layers, then 2 mask layers for the 2 air gap layers and likely 1 mask layer for the under fin doping. Then there are 1 additional cut mask for fins (2 versus 1 for 22nm), 1 cut mask each at contact and M0 and 10 cut masks for metals M1 through M5. In all I see an approximately 50% increase in both masks and process complexity.

IBM
The final paper I wanted to comment on from the session is the IBM paper on their 14nm technology. Where Intel and TSMC produce FinFETs on bulk wafers IBM produces FinFETs on SOI. The use of SOI enables IBM to integrate eDRAM on the same wafer with only 2 masks (my estimate). eDRAM is much more area efficient for cache than SRAM and with the huge cache sizes required for processors and SOCs eDRAM can save a lot of die area. I believe the IBM eDRAM process only requires 1 mask to form the trench DRAM capacitor and 1 additional mask for a thick gate oxide for the access transistors. The IBM process definitely leads in the complexity category with 15 metal layers and the eDRAM. This process is likely targeted at IBMs internal processors used for high end servers where processor cost is really not much of a consideration. The process pitches are 42nm for fin, 80nm for gate and 64nm for metal. IBM gave the most process details of the three papers with a block level process flow, always a favorite of mine. This is a very impressive high performance process.

Comparison and conclusions
The following table compares the density for the three processes.

[TABLE] align=”center” border=”1″
|-
| style=”width: 133px” |
| style=”width: 120px; text-align: center” | IBM
| style=”width: 114px; text-align: center” | Intel
| style=”width: 108px; text-align: center” | TSMC
|-
| style=”width: 133px” | Gate (CPP)
| style=”width: 120px; text-align: center” | 80nm
| style=”width: 114px; text-align: center” | 70nm
| style=”width: 108px; text-align: center” | 90nm
|-
| style=”width: 133px” | Metal
| style=”width: 120px; text-align: center” | 64nm
| style=”width: 114px; text-align: center” | 52nm
| style=”width: 108px; text-align: center” | 64nm
|-
| style=”width: 133px” | Gate x Metal
| style=”width: 120px; text-align: center” | 5,120nm2
| style=”width: 114px; text-align: center” | 3,640nm2
| style=”width: 108px; text-align: center” | 5,760nm2
|-

A few final observations from this session:
[LIST=1]

To my mind Moore’s law is alive and well not only technologically but I also believe these processes deliver cost per transistor reductions as well. For some of the foundry processes cost reduction is modest at 16nm/14nm because they maintained the same BEOL as previous generations but moving forward to 10nm I expect to see significant cost reductions with a return to full scaling.

Intel has the densest process when measured by the gate x metal pitch metric. What isn’t clear is how an Intel die size would compare to an IBM die size for a die with a large cache. Intel’s SRAM is 0.0588um2 whereas IBM’s eDRAM cell is 0.0174um2 providing a significant potential area saving for cache.

December 31, 2014August 22, 2024

GlobalFoundries did NOT Pull the Emergency Brake!

GlobalFoundries did NOT Pull the Emergency Brake!
by Daniel Nenni on 12-31-2014 at 10:00 am
Categories: Foundries, GlobalFoundries

Barron’s again published an unsubstantiated semicondutor rumor that is making the rounds. It all started with a Christmas day blog by Robert Maire who is a long time semiconductor analyst. Please note that he is not a semiconductor professional (someone who actually works in the industry) but he certainly does know people who do. According to LinkedIn Robert and I have quite a few connections in common and those connections are semiconductor professionals.

SoCs should invest in a strong cache position

SoCs should invest in a strong cache position
by Don Dingee on 12-30-2014 at 4:00 pm
Categories: EDA

Like most technology firms, Apple has been home to many successes, and some spectacular defeats. One failure was Project Aquarius. At the dawn of the RISC era, before ARM architecture was “discovered” in Cupertino, engineers were hunkered over a Cray X-MP/48. The objective was to design Apple’s own quad core RISC processor to speed up the Macintosh.

As if designing an instruction set, execution units, and pipeline is not hard enough, getting four cores to work together is more than simply a matter of cloning and connecting. Continue reading “SoCs should invest in a strong cache position”

December 30, 2014August 22, 2024

ANSYS Updates RedHawk for FinFET Nodes

ANSYS Updates RedHawk for FinFET Nodes
by Tom Simon on 12-30-2014 at 7:00 am
Categories: Ansys, Inc., EDA, FinFET, GlobalFoundries

Most designers are not using FinFETs yet, however the increased transistor density and power advantages they offer are compelling. Smaller feature sizes have been a consistent driver in semiconductor technology. Eventually the market will move more and more to FinFET processes, increasingly leaving behind planar transistors. Nevertheless, today FinFETs are used on high end designs, and this means that fabs and designers are working through all the new issues that come with them. There is the need for additional lower level local routing layers. New models, such as BSIM-CMG, are required to get accurate simulation results. Lithography is changing as well. And there are a number of other new issues and challenges.

Sign off for power, noise and reliability are going to change with FinFETs. A recent white paper by ANSYS highlights how each of these areas will need to change. The paper is titled “System-Aware SOC Power, Noise and Reliability Sign-off” and can be found by going to this page. I have always felt that ANSYS (formerly Apache) took hard-to-solve but important problems and built unique solutions for designers. This white paper does a good job of articulating the problems and solutions for advanced node FinFET dynamic voltage drop and the related issues of ESD and electromigration analysis. I used to work for Sequence Design, later acquired by Apache prior to their merger with ANSYS. Back then work started on a comprehensive voltage drop solution. With that early work in combination with Apache technology, ANSYS now has a very impressive solution that has been extended with RedHawk 2014 to address FinFET based designs.

To properly address voltage drop, a full and accurate model of switching activity across the whole chip is needed. Using ANSYS RedHawk this can be done with simulation output from a FSDB file or other sources. Or, this can be accomplished earlier in the design flow before good simulation results are available by using RedHawk’s VectorLess™ dynamic simulation engine. RedHawk supports multiple modes for running VectorLess™; they are PowerTransient™, FrequencyAware™ and VectorLess Scan™. RedHawk can mix gate level simulation data with RTL simulation data to get an accurate view of activity when some blocks have not yet been run at gate level. The white paper stresses that the important elements are to simulate the switching at the full chip level, which should include instance specific block level switching activity, and to include package and even board level power supply models.

To decrease dynamic power these chips use lower voltages. This comes at the expense of a lower noise margin. FinFET devices have higher drive strengths, which translates into more dynamic switching strain on the power supply network accompanied by greater thermal dissipation issues from self heating. Higher current on smaller wires also exacerbates electro-migration (EM). One of RedHawk’s advantages appears to be that it accurately models self heating effects and avoids having to apply worst case self heating data during EM analysis. The following figure illustrates this.

The RedHawk white paper discusses how distributed multi-processing is used to make it feasible to run a full chip analysis, with minimal loss in accuracy. Taking things one step further, the while paper talks about how RedHawk supports stacked die designs and can model TSVs used with interposers. The different dies can even be built with different process nodes. Package structures such as micro bumps and copper pillars are included in the RedHawk analysis.

To meet low power requirements, a high performance SOC might have multiple supply voltages, dozens of power islands, and multiple clock domains. Power gating and clock gating also affect dynamic voltage drop. These design approaches further complicate validation of power grid performance due to dynamic loads and different operational modes of the chip. The white paper discusses how RedHawk deals with these complicating factors in those designs.

Lastly the white paper touches on enhancements to the GUI for RedHawk. There is support for multi-pane views to aid in visualizing and debugging design issues. RedHawk includes the RedHawk Explorer (RHE) that designers can use to locate problems so they can be fixed. It should be useful in locating root causes of power integrity issues.

Based on this white paper it looks like ANSYS is doing an excellent job of keeping up with innovations in the semiconductor design process. At this juncture it is important that they continue to deliver as they bring the Apache tool set under the umbrella of the ANSYS multi physics tools, such as HFSS™, Icepak™ and SIwave™.

December 29, 2014

New Vivado Release. And a Competition!

New Vivado Release. And a Competition!
by Paul McLellan on 12-29-2014 at 5:00 pm
Categories: FPGA, Xilinx

It is not entirely clear what Xilinx is these days. Of course it is an FPGA company. If you hear the word FPGA then I bet Xilinx is the first thing you think of. But what Xilinx ships these days is a far cry from the type of device it created when it was starting, where FPGAs were largely used to vacuum up all the glue logic around the processors and memories on a circuit board. Back in those days a microprocessor was a whole chip and it wasn’t possible to embed one. Now an entire system can be implemented in a Xilinx part. But one key part of the whole system is the Xilinx software toolchain Vivado that is used to program the devices, often starting from Verilog or VHDL but increasingly from C/C++, especially when the person writing the code is actually a software engineer with no (or limited) hardware design experience. As the design of systems moves to the higher level, increasingly the design is being done by engineers who do not know RTL.

Xilinx has just announced a suite of new capabilities in the software with the release of Vivado 2014.4. This release adds support for many of the 28nm and Ultrascale devices in particular the Artix-7 and Zynq-7000 including the recently announced low power/speed grades. The full table of supported devices is above.

More information on Vivado is here.

Another feature is the partial reconfiguration capability. I wrote about this earlier in the context of the SDAccel. Partial reconfiguration allows the array to be partially reprogrammed without requiring the entire bitstream to be reloaded. Indeed, the part of the array not being reprogrammed can continue to operate at the same time, allowing a large array to be dynamically loaded with whatever functionality is required at that time.

Peeling back one more layer of the onion, partial reconfiguration allows for the dynamic change of modules within an active design. This flow requires the implementation of multiple configurations which ultimately results in full bitstreams for each configuration, and partial bitstreams for each Reconfigurable Module. The number of configurations required varies by the number of modules that need to be implemented. However, all configurations use the same top-level, or static, placement and routing results. These static results are exported from the initial configuration, and imported by all subsequent configurations using checkpoints.

More information on partial reconfiguration is here.

It is also time for the Vivado Design Leadership Awards. There are two categories:

All programmable design leadership focusing on designs using Xilinx FPGAs and 3D ICs
Smarter systems design leadership focusing on designs using Xilinx Zynq-7000 all-programmable SoCs, hardware and software programmable devices enabling rapid design and implementation of smarter systems

As Xilinx themselves say:
We are looking for the best of the best. To enter, applicants should submit their design in technical paper format. The winners will be honored with public recognition via a press release, promotion within Xcell Publications, a glass design leadership award for the winners, an award plaque prominently displayed at Xilinx Headquarters in San Jose, California and the opportunity to present the winning technical paper at the Club Vivado Users Group 2015.

To enter go here.

Top Ten Semiconductor CEOs in 2014!

Top Ten Semiconductor CEOs in 2014!
by Daniel Nenni on 12-29-2014 at 7:00 am
Categories: EDA, Foundries

Since my blog about the Intel CEOs went over so well (sarcasm) I thought I should write more about semiconductor chief executive officers. This list comes from David Manners of Electronics Weekly who, unlike me, is a real journalist. Using David’s list as a starting point I will add more candidates at the end and please add yours in the comment section. If you agree or disagree with names on the list feel free to share your opinions, observations, and experiences. Let’s crowd source a top ten list and take a closer look to see what really makes a great semiconductor CEO. One thought I had was to put together a list of questions for the top ten CEOs. If you folks help put together a list I will get the answers, absolutely.

For readability purposes I have provided a link to their full biographies since they are very distinguished men with long lists of accomplishments. I did however include their education since I personally feel it is a qualified data point for a semiconductor CEO.

Syed Ali, President & CEO, Cavium Networks
MSE, University of Michigan

Dr. Jalal Bagherli, Chief Executive Officer, Dialog Semiconductor
Ph.D., Electronics, Kent University, UK

Dr. Oh-Hyun Kwon, Chief Executive Officer of Samsung Electronics Co.
Ph.D., Electrical Engineering, Stanford University

Scott McGregor, President and Chief Executive Officer, Broadcom
MS, Computer Science and Computer Engineering, Stanford University

Ming-Kai Tsai, Chairman & CEO, MediaTek
MSEE, University of Cincinnati

Jen-Hsun Huang, co-founder, president, chief executive officer, NVIDIA
MSEE, Stanford University

Dr. Sehat Sutardja, Chairman and CEO and Co-Founder, Marvell Technology Group
Ph.D., EE and CS, University of California at Berkeley

Behrooz Abdi, President and CEO, InvenSense
MSEE, Georgia Institute of Technology

Dr. Leo Li, Chairman, CEO and President, Spreadtrum Communications
Ph.D., Electrical Engineering, University of Maryland

Steve Mollenkopf,Chief Executive Officer, Qualcomm
MSEE, University of Michigan

To this list I would add:

Moshe Gavrielov, President & Chief Executive Officer, Xilinx
MSCS, Israel Institute of Technology

Fermi Wang, CEO, Ambarella
Ph.D,Electrical Engineering, Columbia University

Dr. Reinhard Ploss, Chief Executive Officer, Infineon Technologies
Ph.D.,Chemical Engineering,Technische Universität München

Sanjay Mehrotra, Co-Founder, President and Chief Executive Officer, Sandisk
MSEE and CS, University of California, Berkeley

Dr. Sanjay K. Jha, CEO of GLOBALFOUNDRIES
Ph.D. in Electronic and Electrical Engineering, Strathclyde University, Scotland

Mark Durcan, Chief Executive Officer, Micron
Master of Chemical Engineering, Rice University

Honorable mention: I did not include Dr. Morris Chang since he is not CEO or Dr. Mark Lui and Dr. C.C. Wei since they are TSMC Co-CEOs. I would have also liked to Include Dr. Aart de Geus and Dr. Walden Rhines but they are EDA CEOs. And Sir Hossein Yassaie CEO of Imagination Technologies but that is semiconductor IP.

December 28, 2014August 22, 2024

Fabless Semiconductor Milestones of 2014!

Fabless Semiconductor Milestones of 2014!
by Daniel Nenni on 12-28-2014 at 9:00 am
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

After working in the semiconductor industry for the past thirty years and writing about it for the past six I would say that 2014 was one of the more interesting years of late. Vindication is the word that pops into my mind now that many “predictions” the fabless detractors have made over the last three years were proven wrong.

As a student of history I think it is important to look at the past to better prepare for the future which is one of the reasons why I blog. Blogging also enabled us to write our book on the history of the fabless semiconductor industry. To take a look back, SemiWiki members can click on the company names or industries (categories) in the header of the blog summaries to see what we have written on that company or market segment. You can also click on the author to see what each of us have written, simple as that.

In 2014 814 blogs were published on SemiWiki bringing the total to 2134 written by 42 different people. According to Google, SemiWiki has recorded 1,245,650 unique viewers since going online in 2011. The big data (analytics) behind all of this activity is truly amazing.

2014 also brought my 30th wedding anniversary which my beautiful wife and I celebrated in Hawaii. She runs the financial side of SemiWiki and edits everything I write. 30 more years is going to be no problem at all.

Some of the top viewed blogs I wrote in 2014 include:

[LIST=1]

GLOBALFOUNDRIES Acquires IBM Semiconductor Unit!

Intel Core M vs Apple A8!

Is Intel the Concorde of Semiconductor Companies?

TSMC Responds to Intel’s 14nm Density Claim!

TSMC vs Intel vs Samsung FinFETs

Who is Using Samsung 14nm?

More Apple A9 Ridiculousness!

Who will Manufacture Apple’s Next SoC?

TSMC Updates: 20nm, 16nm, and 10nm!

Samsung 14nm is the one delayed!

I agree with this ranking 100%. The GF/IBM deal was by far the most exciting thing to happen in 2014. I have written about GF 46 times over the last 5 years and the IBM acquisition blog was viewed 5 times more than the average. It really could be a game changer for the fabless semiconductor industry. The pure-play foundry business model is what delivered supercomputing to our fingertips (literally) so that business model must continue at all costs. Seriously, IDM foundries do not have our collective best interests in mind as history has clearly shown.

The most controversial event was the release of the TSMC 20nm A8 and A8x making Apple one of the leading fabless semiconductor companies. Not only was this Apple’s first pure-play foundry chip it was also the first time Apple designed two SoCs, one for the iPhone and a higher performance version for the iPads. Even though South Korea press said this would be a Samsung chip we all knew it would be TSMC and it would yield in time for the iPhone6 launch in Q3 2014. The other thing the A8 brought was a fresh perspective on the Intel process density superiority claims.

The word vindication also comes to mind since so called industry experts claimed that 20nm would not be in high volume production “until 2015 but mostly 2016”. People also doubted the foundries would produce FinFETs in 2015 and one gentleman predicted that it wouldn’t happen until 2017 and 10nm would also be delayed. Clearly that is not the case so congratulations to the hard working people of the fabless semiconductor ecosystem that proved experts, competitors and the outside media wrong, absolutely.

December 27, 2014

Op-amps moving toward zero-drift, greater voltage range

Op-amps moving toward zero-drift, greater voltage range
by Majeed Ahmad on 12-27-2014 at 7:00 am
Categories: EDA

Operational amplifiers, which are among the most widely used analog components found in nearly all types of electronic systems, are migrating toward zero-drift capability and much-greater range of voltages at the supplies and the inputs. Take Linear Technology Corp.’s LTC2057HV, a zero-drift operational amplifier, which features self-calibrating circuitry that provides high DC precision and stability over changes in temperature, time, input range and supply voltage. The LTC2057HV components claim to offer optimal combination of low voltage noise, low current noise and low input bias current, while the zero-drift architecture cancels 1/f noise.

Operational amplifier – commonly known as op-amp – is one of the basic building blocks of analog electronics for functions such as filters. It’s a linear device that boasts all the properties required for nearly ideal DC amplification and is therefore used extensively in signal conditioning, filtering or to perform mathematical operations such as add, subtract, integration and differentiation. An op-amp is basically a three-terminal device which consists of two high impedance inputs, one called the inverting input, marked with a negative or “minus” sign, ( – ) and the other one called the non-inverting input, marked with a positive or “plus” sign ( + ).

Operational amplifier block diagram

A wider range of supply and input voltages is critical because high supply-voltage amps are powered by systems that connect to power systems, automobiles, or large battery packs. Here, the amplifier’s input may be connected to hundreds of volts, but amplifying signals will still be operating in the microvolt range. On the other hand, high-voltage amplifiers also offer features to improve system performance, cost, and robustness, while easing the complexity of system design. The second key element in the ongoing op-amp evolution is zero-drift – a technique originally developed to address constantly changing temperature as well as drift over time. The zero-drift amplifiers dynamically correct offset voltage as well as reshape noise density.

Linear’s LTC2057HV amplifier offers more than 140dB dynamic range while operating on a 60V (±30V) supply. “This wide dynamic range enables tiny signals to be amplified in the presence of much larger signals without saturating the amplifier or losing precision,” said Brian Black, product marketing manager for signal conditioning products. Here, spurious artifacts normally associated with zero-drift amplifiers are suppressed, further extending the dynamic range, stability and useful signal bandwidth.

For applications requiring supply voltages of up to 36V, a lower supply version of LTC2057 is also available. Both LTC2057 and LTC2057HV components – operating over a -40°C to 125°C temperature range – claim to offer low voltage noise, low current noise and low input bias current, while the zero-drift architecture cancels 1/f noise. The input common-mode range includes the negative rail and the output swings rail-to-rail, which makes the LTC2057 component suitable for single- and dual-supply industrial, instrumentation and automotive applications.

The LTC2057 part is available in 3mm x 3mm DFN, MSOP-8 and SOIC-8 packages, as well as an MSOP-10 package with a pin-out that enables a guard ring to be easily routed around the input to preserve the high precision and low noise performance at high source impedance.

Linear’s 60V zero-drift op-amp

High-speed op-amps

Exar Corp., another supplier of analog and mixed-signal chips, has recently launched the XR805x family of high-speed operational amplifiers for applications such as video distribution and surveillance systems. These operational amplifiers are widely used in a vast array of consumer, industrial, and scientific devices.

Exar claims that its operational amplifiers will lower the overall system power consumption and provide higher precision for improved performance. “The XR805x family offers customers an opportunity to make their designs more power efficient and at the same time, improve performance,” said Dale Wedel, Exar’s vice president of High Performance Analog product line. “These pin-for-pin drop-in replacements allow customers to lower power consumption in existing platforms and offer performance enhancements that enable next generation designs.”

The XR805x family of devices is targeted at applications including professional and IPC cameras, active filter circuits, coaxial cable drivers, and electronic white boards. The amplifiers can drive four video loads and operate from a wide supply voltage range to accommodate general-purpose, high-speed applications where dual supplies of up to +/- 6V or single supplies from +2.7V to +12V are required.

Amplifiers often pick up a small signal in a hostile environment and then ride on top of a larger signal. These highly versatile components are the unsung heroes in most of the electronic systems. Op-amps are an increasingly important part of the amplifier recipe, and they are likely to play a crucial part in the future for their role in a diverse range of applications.

Majeed Ahmad is the author of Smartphone, Nokia’s Smartphone Problem, Mobile Commerce 2.0and Essential 4G Guide.He has been writing for technology and trade media for more than 19 years.

December 26, 2014

Riding the Wave of Silicon Magic in 2015!

Riding the Wave of Silicon Magic in 2015!
by Daniel Nenni on 12-26-2014 at 7:00 am
Categories: ESD Alliance, Events, Semiconductor Services

2014 was a busy year for SemiWiki. We attended dozens of events, met hundreds of people (if not thousands), and published 810 blogs and a book that reached more than half of a million people. We collaborated throughout the fabless semiconductor ecosystem all year long and let me tell you it has been an amazing mind expanding experience, absolutely.

Next year will be even bigger for SemiWiki and the fabless semiconductor ecosystem and it all starts with the first SEMI Industry Strategy Symposium (ISS) at the Ritz Carlton in Half Moon Bay. Here are just a few of the topics that will be covered:

Riding the Wave of Silicon Magic–Broadcom
Internet of Everything (IoE) – Supply Chain Transformation–Cisco Systems
The Future in a World of Digitized Defined Objects–Consumer Electronics Association
Transforming a Business for Success–Honeywell
Imagine How Genomics Will Transform Our Future–Illumina
Technology Innovation in an IoT Era–IMEC
IoT– The Next Technology Revolution–Intel
Enabling Moore’s Law through Materials Innovation–Intel
Top-10 Economic Predictions for 2015–IHS
Industry Dynamics and Growth Trends for Semiconductor Wafer Fab Materials–Linx Consulting
Mapping Innovations to Growth: Assessing the Impact of Emerging Technologies in Autonomous Systems, Internet of Things, Wearables, and 3D Printing–Lux Research
Semiconductors in 2015–Where Are We and Where Are We Going?–McKinsey and Company
A Geopolitical Forecast: Trends Shaping Semiconductor Manufacturing Countries–Stratfor
The Cycle: Is it Different This Time?–VLSI Research

With an incredible lineup of speakers from Altera, Boeing, Broadcom, Cisco, IBM, IMEC, Intel, Micron, Qualcomm, Samsung, and TSMC, here is the premise of the symposium. It is definitely worth a read. Paul McLellan and I will both be there and it would be a pleasure to meet you!

Since the dawn of computing, the semiconductor industry has been the enabler for the major innovations in the electronics industry. Moore’s Law has been the foundation for semiconductor industry economics. It laid the groundwork for the PC revolution, pervasive use of the internet, and the emergence and dominance of mobile devices, and each wave created renewed demand and prosperity in the semiconductor industry. In recent years, demand for semiconductors, and with it growth, has slowed to single digit numbers. Exploding costs for developing and manufacturing these state-of-the-art devices has led to major consolidations, first among device makers and then among the equipment and material suppliers. Although this may be healthy, profitable growth is necessary for the re-investment needed to continue the silicon magic and create the next wave of innovations that will generate demand for more device capability.

While the above natural forces are in play, mobility and availability of tablets and smart phones for the masses, coupled with the exciting possibilities that the Internet of Things can bring, could potentially lead to increased growth in ICs. Further, continued efficiencies and shifts in the value chain caused by deeper collaboration between fabless and foundries on one hand, unique capabilities that IDMs deliver on the other, and the entry of some IDMs to the foundry sector, should generate new dimensions in the supply chain’s quest to create value.

ISS 2015 explores the trends taking place in the industry from economic, market, technology, and manufacturing perspectives. In addition, the conference will look at ways to address the demands for continued development and manufacture of advanced technology. How should the supply chain respond to create increased value for customers, no matter where in the supply chain they reside? And most importantly, what should the industry do to maintain and increase prosperity to meet this demand in order to continue to sustain future growth? As always, the final goal is to help semiconductor industry executives set their strategies to navigate this exciting and rapidly changing environment.

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains. Our 1,900 member companies are the engine of the future, enabling smarter, faster and more economical products that improve our lives. Since 1970, SEMI has been committed to helping members grow more profitably, create new markets and meet common industry challenges. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org.