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Three New Circuit Simulators from Siemens EDA

Three New Circuit Simulators from Siemens EDA
by Daniel Payne on 06-27-2024 at 10:00 am
Categories: EDA, Siemens EDA

solido simulation suite

The week before DAC I had the privilege to take a video call with Pradeep Thiagarajan – Product Manager, Simulation, Custom IC Verification at Siemens EDA to get an update on new simulation products. I’ve been following Solido for years now and knew that they were an early adopter of ML for Monte Carlo simulations with SPICE users. Using generative AI with LLM has become quite popular with vendors like OpenAI, Google and Microsoft all updating their product offerings. This trend is driving semiconductor design starts, increasing system complexity, rising semiconductor costs, all while our universities are not attracting enough students to become engineers. Many of my EDA and semiconductor peers are now in retirement age. So, AI has the promise to help meet these challenges by improving productivity.

Over the years the software tools at Siemens EDA have infused AI technology where it makes sense:

  • Emulation, Prototyping – Veloce
  • Digital verification – Questa
  • Custom IC verification – Solido
  • DFT – Tessent
  • Place & Route Floor planning – Aprisa
  • DRC, LVS, DFM – Calibre
  • PCB design exploration – HyperLynx
  • PCB design – Xpedition

The news is that for Custom IC verification, there are three new product announcements under the name of Solido Simulation Suite. Let me show you where these new simulators fit into the product family.

Solido Simulation Suite has three new technologies with descriptive product names to fit different requirements:

  • Solido SPICE
  • Solido LibSPICE
  • Solido FastSPICE

The motivation for adding three new circuit simulators is to meet the growing need from 7nm and smaller nodes for higher performance and capacity while maintaining accuracy. Yes, the existing SPICE tools AFS and Eldo continue to serve customers and will remain supported and enhanced.

Three New Circuit Simulators

The Solido Design Environment was launched in 2023 at DAC, followed by the Solido Characterization Suite, and then the Solido IP Validation for QA was announced in May, so this news of three new simulators continues the progress at Siemens EDA. The Solido R&D headcount has doubled in just the past 3 years to bring all these advancements to life. Solido Sim AI is a technology inside of each new simulator to further accelerate the many internal computations, like: netlist parsing, model evaluation, partitioning, and matrix solving. The transistor models for 2nm and 3nm nodes are quite complex now, so using acceleration helps reduce run times.

For SPICE accuracy engineers would run Solido SPICE, for smaller designs and library characterization runs it would be Solido LibSPICE, and for the largest designs including memories the Solido FastSPICE tool is the best choice. These simulators also integrate nicely with other Siemens EDA tools, like mPower for EM/IR analysis, ESD analysis with Calibre PERC, 3D IC electro-thermal with Calibre 3DThermal, and analog fault analysis with Tessent Defectsim.

Looking at customer circuits the speed improvements in Solido SPICE showed a 2X – 30X verification speedup at full SPICE accuracy, Solido LibSPICE had 2.3X to 5.5X speedups across a variety of library cell runs, and Solido FastSPICE touted speed improvements ranging from 13.8X up to 68X. Early customer endorsements were noted from tier-one semiconductor companies: Silicon Laboratories, and Samsung Electronics. Foundry endorsement from Intel Foundry too.

Summary

The challenges of designing an SoC or chiplet with nm process nodes continue to grow, demanding higher capacity circuit simulations and even integration with other analysis tools. Siemens EDA has just launched three new circuit simulators that span a spectrum from SPICE accurate to libraries to the largest netlists, and the early customer results show dramatic speed improvements while maintaining accuracy. Integration with tools for EM/IR, ESD and 3D IC make these new simulators more valuable. Many EDA vendors launch a new circuit simulator once every 3-5 years, but having three new circuit simulators all at one time is something that I’ve never seen done before, so kudos to the development teams at Siemens EDA for pulling this feat off.

Related Blogs

 

Podcast EP231: Details of the New Solido Simulation Suite with Sathish Balasubramanian

Podcast EP231: Details of the New Solido Simulation Suite with Sathish Balasubramanian
by Daniel Nenni on 06-27-2024 at 8:00 am

Dan is joined by Sathishkumar Balasubramanian. Sathish currently leads the product management and marketing organization for CustomIC Verification (CICV) division at Siemens. Sathish is an experienced product leader with over 20+ years of experience in the EDA industry.

Sathish’s focus is on bringing value to the semiconductor ecosystem through innovative solutions. Sathish is proficient in scaling product portfolio growth and expansion of market share/revenue through relentless focus on data-based execution and thought leadership. Prior to Siemens, Sathish held various product management, strategic business development and corporate development roles for Cadence Design Systems and Synopsys.

Sathish describes a major announcement being made at DAC for a new Solido Simulation Suite. This represents a new, AI-powered circuit simulation capability to address the special requirements of advanced designs such as those driven by AI technology.

Sathish provides details of three new capabilities that are part of the Solido Simulation Suite. The first is Solido SPICE, a foundry-certified circuit simulator that provides significant speedup compared to other Spice simulators. The second is Solido Fast SPICE that employs AI partitioning and multiresolution technology to deliver orders of magnitude speedup. And the third is a purpose-built simulator focused on the special needs of foundation IP to ensure robust performance for new foundation IP design.

Sathish explains how these new offerings are integrated into the overall design flow to address all the requirements for advanced design verification.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Siemens Provides a Complete 3D IC Solution with Innovator3D IC

Siemens Provides a Complete 3D IC Solution with Innovator3D IC
by Mike Gianfagna on 06-27-2024 at 6:00 am
Categories: 3D IC, AI, EDA, Siemens EDA

Siemens Provides a Complete 3D IC Solution with Innovator3D IC

Heterogeneous multi-die integration is gaining more momentum all the time. The limited roadmap offered by Moore’s Law monolithic, single-die integration has opened the door to a new era of more-than-Moore heterogeneous integration. The prospects offered by this new design paradigm are exciting and the entire ecosystem is jumping in to bring it all closer to reality. Standards to help make chiplets more widely available, new materials to increase density and a host of design technologies to make it all work are underway. While all this promises to deliver an integrated design capability, the elephant in the room is where to start.  High quality and well-integrated up-front planning at the system level is a necessity to ensure success for the next wave of designs. Siemens Digital Industries Software recently announced a comprehensive new approach to 3D IC design. They seem have gotten it right regarding how to scope the problem for success. Let’s examine how Siemens provides a complete 3D IC solution with Innovator3D IC.

What Problem Needs Solving?

Keith Felton

I recently had the opportunity to chat with Keith Felton, product marketing manager at Siemens for High-Density Advanced Packaging (HDAP) solutions. Keith has a long history of solving advanced design and packaging challenges.

Keith explained that there is indeed a lot of work going on to address the challenges of tasks such as place and route for multi-die heterogeneous designs. All of that is quite important, but Keith pointed out that early feasibility planning and analysis of the system, before implementation begins is a critical step that needs to be addressed first. The questions that must be answered before implementation begins include:

  • What are the system thermal considerations?
  • Can I get the right level of power to all parts of the system?
  • How will the substrate and the overall package behave under typical and extreme operation?

This is just a summary of a much longer list of questions that must be addressed early in the design flow and at the system level. This is really the only way to avoid downstream re-work that can have substantial negative impact. Keith explained that part of the innovation here is to build a digital twin model of the system early. Using this model a design cockpit can be created that allows forward visibility to all downstream tools to allow tradeoffs to be assessed and roadblocks avoided before detailed implementation begins.

This made perfect sense to me. Let’s look at some of the details of the announcement.

How Siemens Provides a Complete 3D IC Solution with Innovator3D IC

Innovator3D IC delivers the fastest and most predictable path for planning and heterogeneous integration of ASICs and chiplets using the latest semiconductor packaging 2.5D and 3D technology platforms and substrates. The technology provides a unified cockpit for design planning, prototyping and predictive multi-physics analysis. This cockpit constructs a power, performance, area (PPA) and cost optimized digital twin of the complete semiconductor package assembly that in turn drives implementation, multi-physics analysis, mechanical design, test, signoff, and release to fabrication and manufacturing through a managed and secure design IP digital thread conduit.

Innovator3D IC is architected around the system technology co-optimization (STCO) methodology process developed by IMEC. STCO is utilized throughout prototyping and planning, design, sign-off, and manufacturing hand-off, concluding with comprehensive verification and reliability assessment.

The figure below summarizes the broad set of capabilities delivered by Innovator3D IC.

Innovator3D IC Heterogeneuous Integration Cockpit

Although the cockpit is directly integrated with the extensive Siemens Xcelerator technology portfolio, it supports the integration of third-party point solutions, recognizing that customers may have third party tools in their current design flows that they wish to continue using. The co-optimization employed by Innovator3D IC also makes extensive use of AI technology for co-optimization as shown in the figure below.

Innovator3D IC AI Infused Co Optimization

Industry standards support is also an important part of the overall solution. A key area is the commitment and support for the growing 3Dblox™ standard that enables EDA tool interoperability, bringing the benefits of improved productivity and efficiency to end users and customers in 3D IC system level designs.

It is also important to ensure frictionless adoption and consumption of existing and new die-to-die interface IP, such as UCIe and BoW. The Open Compute Project Chiplet Design Exchange Working Group (OCP CDX) has enabled direct consumption of standardized chiplet models that will be provided by the emerging commercial chiplet ecosystem.

Predictive multiphysics analysis is also an important part of the solution. During prototyping and planning it is critical to evaluate the performance of all design scenarios before committing to implementation. Innovator3D IC integrates directly with power, signal, thermal, and mechanical stress analyses so that a design scenario can be evaluated quickly, and any issues explored and resolved prior to detailed design implementation. This shift-left approach prevents costly and time-consuming downstream rework and sub-optimal results.

To Learn More

According to the announcement, Innovator3D IC is expected to be available later in 2024. You can learn more about Siemens’ Innovator3D IC software here.  You’ll find a lot of useful information there, including a very informative brochure. You can read the complete press release here.  And that’s how Siemens provides a complete 3D IC solution with Innovator3D IC.

 

 

 

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New EDA Tool for 3D Thermal Analysis

New EDA Tool for 3D Thermal Analysis
by Daniel Payne on 06-26-2024 at 10:00 am
Categories: EDA, Siemens EDA

3D IC cross section min

An emerging trend with IC design is the growing use of chiplets and even 3D IC designs, as the disaggregated approach has some economic and performance benefits over a single SoC. There are thermal challenges with using chiplets and 3D IC designs, so that means that thermal analysis has become more important. I just spoke with Michael White, Sr. Director in the Calibre group at Siemens EDA to get an update on their newest product, and it’s called Calibre 3DThermal.

3D IC cross-section

The emphasis with Calibre 3DThermal is to enable shift-left, helping IC designers get through analysis and verification more efficiently by doing early feasibility analysis of their IP, chiplet, SoC and package, eliminating surprises at the end of a project. This approach allows a team to start thermal analysis quite early, even in the concept phase with very few details, just to get the analysis process started. Siemens EDA has an array of tools from IC to package to systems, and now these tools can communicate through thermal analysis.

Siemens EDA thermal flows

This is another example of EDA enabling multi-physics analysis, as thermal issues also impact power, stress, timing and variation. Calibre 3DThermal has been designed to be easy to learn and use. The Simcenter Flotherm tool has been in use for years now in package and system thermal analysis, and with 3DThermal design teams can pass info back and forth from inside the package then outwards to the system. As a design progresses and more details are available, then annotated SPICE netlists are sent to Solido and other circuit simulators.

Early feasibility analysis helps design teams make decisions about floor planning, gauging the impact of using heatsinks, adding thermal TSVs, and seeing how close they are at meeting power, thermal and timing goals. Data used in Flotherm can use an embedded, abstracted model of the package, even encrypting it to hide any sensitive details or trade secrets.

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Calibre 3DThermal to Flotherm

Inside the 3DThermal tool is an optimized version of the Flotherm solver for even better capacity during analysis of large IC designs. The 3DThermal tool could be used by a package engineer, systems designer or an IC designer to perform analysis. Engineers add details like LEF/DEF and GDS/OASIS files. Fast and accurate results are made easier through automatic gridding, automatic time step generation and automatic chip thermal model creation.  The 3Dblox language started by TSMC is also supported.

3DThermal Screenshots

UMC and their customers collaborated with Siemens EDA  during the development of Calibre 3DThermal

Summary

 It’s a busy week at DAC, and Siemens EDA has just announced another addition to the growing Calibre family of tools with their new 3DThermal product, enabling chiplet and 3D IC designers to start early thermal analysis, then proceed throughout the design process to work with package and systems engineers to meet thermal, power and timing goals. Multi-physics analysis is enabled with this approach, allowing teams to shift-left on tough problems. Expect to see announcements from the major foundries on their support of Calibre 3DThermal.

Read the press release from Siemens EDA online.

Related Blogs

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Novelty-Based Methods for Random Test Selection. Innovation in Verification

Novelty-Based Methods for Random Test Selection. Innovation in Verification
by Bernard Murphy on 06-26-2024 at 6:00 am
Categories: AI, Automotive, Cadence, EDA

Innovation New

Coverage improvement effectiveness through randomized testing declines as total coverage improves. Attacking stubborn holes in coverage could be augmented through learned novel test guidance to random test selection. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick Using Neural Networks for Novelty-based Test Selection to Accelerate Functional Coverage Closure. This article was published in 2023 IEEE AITest. The authors are from Bristol University (UK) and SiFive.

Randomized tests already benefit from ML methods to increase coverage in lightly covered regions of state space. However they struggle to handle coverage holes where there are no or few representative tests from which learning can be derived. This paper suggests learned methods to generate novel tests from input tests based on dissimilarity in each case from the input test

Paul’s view

AI again this month, this time AI to guide randomized simulation vs. to root cause bugs. In commercial EDA, AI-driven random simulation is hot and beginning to deploy at scale.

This paper focuses on an automotive RADAR signal processing unit (SPU) from Infineon. The SPU has 265 config registers and an 8,400-event test plan. Infineon tried 2 million random assignments of values to the config registers to cover their test plan.

The authors propose using a NN to guide config register values to close coverage faster. Simulations are run in batches of 1000. After each batch the NN is re-trained and used to select the next batch of 1000 configs that the NN scores highest from a test pool of 85k configs. Configs that are more different (“novel”) from previously simulated configs score higher. The authors try 3 NN scoring methods:

  • Autoencoder: NN determines only novelty of the config. The NN is a lossy compressor/decompressor for config register values. The 265 values for a config are compressed down to 64 (as trained by configs simulated so far) then expanded back to 265 (as trained same way). The bigger the error in decompression the more “novel” that config is.
  • Density: NN predicts coverage from config register values. The novelty of a new config is determined by inspecting hidden nodes in the NN and comparing to the values of these nodes for previously simulated configs. The bigger the differences the more novel that config is.
  • Coverage: NN predicts coverage from config register values. A final layer is added to the NN with only one neuron, trained to compute a novelty score as a weighted sum of predicted coverage over 82,000 cover events. The weight of each event is based on its rarity – events rarely hit by configs simulated so far are weighted higher.

Results are intriguing: the coverage-NN achieves the biggest improvement at around a 2.13x reduction in simulations needed to hit 99% and 99.5% coverage. However, it’s quite noisy and repeating the experiment 10 times reduces the gain to 1.75x. The autoencoder-NN is much more stable, achieving 1.87x best case and a matching 1.75x on average – even though it doesn’t consider coverage at all! The density-NN is just bad all over.

Great paper, well written, would welcome follow-on research.

Raúl’s view

This is about Neural networks to increase functional coverage, to find “coverage holes”. In previous blogs we reviewed the use of ML for fault localization (May 2024), to simulate transient faults (March 2024), verifying SW for Cyber-Physical systems (November 2023), generating Verilog assertions (September 2023), code review (July 2023), detecting and fixing bugs in Java (May 2023), improving random instruction generators (February 2023) – a wide range of functional verification topics tackled by ML!

The goal is to choose tests generated from a Constrained Random Test Generator to favor “novel” tests based on the assumption that novel tests are more likely to hit different functional coverage events. This has been done before with good results as explained in section II. The authors build a platform called Neural Network based Novel Test Selector (NNNTS). NNNTS picks tests in a loop, retraining three different NN for three different similarity criteria. These NNs have 5 layers with 1-512 neurons in each layer. The three criteria are:

  • Calculates the probability of a coverage event being hit by the input test
  • Reduces an input test into lower dimensions and then rebuilds the test from the compressed dimensions. The mean squared difference that expresses the reconstruction error is considered as Novelty Score.
  • Assumes that for a simulated test, if a coverage event hit by the test is also often hit by other simulated tests, then the test is very similar to the other tests in that coverage-event dimension. The overall difference of a simulated test in the coverage space is the sum of the difference in each coverage-event dimension.

They test against a Signal Processing Unit of the ADAS system. The production project consumes 6-month simulation of ~2 million constrained random tests with almost 1,000 machines and EDA licenses. The simulation expense of each test is 2 hours on average, there is some manual intervention and in the end 85,411 tests are generated.

In the experiment 100 tests from all generated tests are randomly picked to train NNNTS and then 1000 tests are picked at a time before retraining until reaching a coverage of 99% and 99.5%. This is repeated many times to get statistics. Density does the worst, saving on average 22% over random selection of tests to achieve 99% coverage and 14% to achieve 99.5%. Autoencoder and Density perform similarly, saving on average about 45% to reach 99% and 40% to reach 99.5% coverage.

This work is impressive as it can reduce the time and cost for functional verification by 40%, in the example of 6 months,1000 machines and EDA licenses and people – though the paper does not specify the cost of running NNNTS. The paper reviewed in February 2023 achieved 50% improvement on a simpler test case and a different method (DNNs were used to approximate the output of the simulator). I think enhancing/speeding up coverage in functional verification is one of the more promising areas for the application of ML, as shown in this paper.

Also Read:

Using LLMs for Fault Localization. Innovation in Verification

A Recipe for Performance Optimization in Arm-Based Systems

Anirudh Fireside Chats with Jensen and Cristiano

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Lab on Cloud Demonstration

Lab on Cloud Demonstration
by Daniel Payne on 06-25-2024 at 10:00 am
Categories: Semiconductor Services, TenXerLabs

TenXer lab setup min

Systems engineers often want to select the best IC for their projects, yet the time required to search online, buy an Evaluation Kit, waiting to receive it in the mail, then getting it installed and setup for testing can be a barrier and lengthen the project timeline. This is where TenXer Labs comes in, as they have cleverly developed a Lab-on-Cloud offering, with over 80 Evaluation Kits setup in their labs and controlled through a web interface virtually. I had a video call to see this concept demonstrated in real time recently, and I asked lots of questions to learn more about their service.

Anand Subramanian, Director of Engineering at TenXer Labs, provided the demonstration and he has 23 years of experience in multiple areas: software engineering, security domain, AWS infrastructure, cloud security, automation. The first demonstration had a Renesas board for a single-burner induction cooktop, complete with a power board, HMI board, oscilloscope, controls and video.

Demonstration Setup

The web browser used to view and control the evaluation board started with a simple plugin.

Starting LiveBench

Each step performed in LiveBench had an intuitive prompt, and we could view the progress in a log window.

Log Window

Critical measurements like the coil current are measured in real time, then displayed in LiveBench.

Coil Current Measurements

Water is already in the pans, and the coils can heat the pans to a desired temperature. There were even three different pan sizes that could be heated. Parameters like voltage, current and power were being measured and reported.

Parameters Measured and Reported

This demonstration included a video feed, so that you could see the evaluation setup while it was operating.

Video Feed of Setup

Questions about the board setup were typed into a chatbot window called the Knowledge Assistant, and then a reply was auto-generated, saving time from having to lookup details in the documentation.

Chatbot

Only one user at a time is allowed for this specific evaluation board, and there’s a reservation system to request a time slot. For safety purposes, each evaluation board has features built-in so that no fires can be started, and the electronics cannot be over-stressed beyond normal operating regions. There’s a rigorous quality plan for each evaluation board. TenXer provides the necessary maintenance for each of their LiveBench setups, like refilling with water, making sure that batteries are charged, etc.

The second live demo was for a 3D gesture control board with multiple capacitive proximity sensors to detect hand gestures by moving a robotic arm.

Renesas setup – 3D gestures

A vision detection system using the Sitara processor from TI was also demonstrated. Users can choose different object detection algorithms, choose tasks, select test images, then run their tests in real time to measure the effectiveness and efficiency. You can plot the model statistics, verify if your algorithm is working well, and measure the detection rates.

TI setup using the AM62A Sitara processor

TenXer has evaluation boards all setup from several vendors so far:

  • Analog Devices
  • Infineon
  • Micro Chip
  • Monolithic Power Systems
  • Murata Electronics
  • Renesas
  • SiTime
  • Texas Instruments

These labs that are accessible via LiveBench choices span several end-markets:

  • Power Management
  • Industrial Automation
  • IOT, Connectivity
  • Microprocessors & Microcontrollers
  • Edge AI
  • Clock and Timing

LiveBench has language support for English, Chinese, German and Japanese. All of the user manuals are included online for easy reference. Systems engineers can use LiveBench for free, while AEs that want to demonstrate the capabilities of their company devices do pay a fee to use TenXer.

New LiveBench systems are continuously being added as IC vendor demand drives adoption of this Lab on Cloud concept.

Summary

Systems engineers have always been challenged in how to best choose and evaluate kits from IC vendors. It takes engineering time and effort to evaluate new ICs. TenXer has built up an impressive number of LiveBench offerings in the cloud made available for free to systems engineers that have a web browser and Internet access. With this Lab On Cloud approach you can now remotely evaluate a wide range of ICs and sensors, saving time, money and effort.

Visit TenXer online and start trying out their LiveBench setups.

Related Blogs

Podcast EP230: An Overview of the Siemens EDA Calibre 3D Thermal Announcement at DAC with Dr. John Ferguson

Podcast EP230: An Overview of the Siemens EDA Calibre 3D Thermal Announcement at DAC with Dr. John Ferguson
by Daniel Nenni on 06-25-2024 at 8:00 am

Dan is joined by Dr. John Ferguson, senior director of marketing for the Calibre product line at Siemens EDA. John has worked extensively in physical design verification. Current activities include efforts to extend physical verification and PDK enablement for 3DIC design and silicon photonics.

Dan explores the Siemens EDA Calibre 3D Thermal announcement with John that was made during the conference.

John describes the significant new challenges that 3DIC design presents with regard to thermal analysis and modeling. He explains the unique approach that the new Calibre 3D Thermal takes and how it can be used to optimize many different types of designs.

He explores how to use the tool in a Siemens EDA design flow and how to interface the tool to other design flows as well.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Synopsys’ Strategic Advancement with PCIe 7.0: Early Access and Complete Solution for AI and Data Center Infrastructure

Synopsys’ Strategic Advancement with PCIe 7.0: Early Access and Complete Solution for AI and Data Center Infrastructure
by Kalar Rajendiran on 06-25-2024 at 6:00 am
Categories: AI, EDA, IP, Synopsys

(From NewsRelease)Synopsys PCIe 7.0 IP Solution Infographic

In the rapidly evolving world of high-performance computing (HPC) and artificial intelligence (AI), technological advancements must keep pace with increasing demands for speed, efficiency, and security. Synopsys recently announced the industry’s first complete PCIe 7.0 IP solution. This groundbreaking initiative addresses current demands and anticipates future needs, highlighting the importance of early access to advanced technology, the benefits of providing a complete solution, and Synopsys’ pivotal role in the industry. I had an opportunity to gain further insights around this announcement, from Manmeet Walia, Executive Director, Mixed-Signal PHY IP at Synopsys.

Meeting the Demands of Modern Data Centers

The demand for computational power in AI and HPC applications is growing at an unprecedented rate. Large language models require the processing of trillions of parameters in real-time. Synopsys’ PCIe 7.0 solution, with its doubled bandwidth of up to 512 GB/s bidirectional in a x16 configuration, is designed to meet these exacting requirements. Early access to this technology is crucial for hyperscalers and AI data centers to stay ahead of the curve, enabling them to handle larger datasets, faster processing, and more complex algorithms efficiently.

One of the standout features of Synopsys’ PCIe 7.0 solution is its support for linear direct drive optics. This technology eliminates the need for additional digital signal processing (DSP) chips within the optical modules, reducing power consumption and latency. By directly interfacing with optical components, Synopsys’ solution enhances signal integrity and performance, making it ideal for high-speed data transfer over longer distances.

PCIe 7.0 Over Cable and Optics

The ability to extend PCIe 7.0 connectivity beyond traditional confines is a significant advancement. Synopsys’ demonstrations of PCIe 7.0 over both cable and optics address different facets of data center interconnectivity. Here is a short video clip of a PCIe 7.x, PCIe 6.x and 224G Over Optics Synopsys Demo from OFC 2024 Conference. PCIe over cable enables efficient communication within a rack, traditionally dominated by Ethernet. On the other hand, PCIe over optics facilitates high-speed, low-latency connections between racks and across data centers, supporting distances of up to 2 kilometers. This versatility is crucial for hyperscalers and AI data centers that need to manage vast amounts of data across distributed systems efficiently.

The Imperative of Early Access and Complete Solutions

The pace of innovation in data centers and AI applications necessitates early access to cutting-edge technology. Synopsys is offering an early access program for its PCIe 7.0 IP solution, set to be available in early 2025. By engaging with early adopters, Synopsys enables leading companies to integrate the latest advancements into their designs ahead of the formal standard ratification, expected by the end of 2025. This early access allows for thorough testing, optimization, and customization, ensuring that when the technology becomes mainstream, it is robust, reliable, and ready for mass deployment.

Synopsys’ complete PCIe 7.0 IP solution integrates a controller, PHY, IDE security module, and verification IP, offering a turnkey solution that addresses every aspect of data transfer needs. This complete package simplifies the integration process for customers, ensuring seamless compatibility and optimal performance. By providing a fully integrated solution, Synopsys reduces risks associated with piecemeal implementations, such as compatibility issues and suboptimal performance.

Synopsys’ Leadership and Industry Influence

With over 20 years of experience in PCIe technology, Synopsys holds a strategic vantage position in the industry. The company has a seat on the PCI-SIG board, giving it a deep understanding of upcoming standards and allowing it to influence the direction of PCIe technology. This insight enables Synopsys to align its IP product development closely with industry needs and standards. Synopsys’ extensive track record, with over 500 wins in PCIe Gen 4 IP solution and nearly as many in PCIe Gen 5 IP solution, underscores the company’s expertise and leadership in the field.

The Significance of Synopsys’ Partner Ecosystem

Synopsys’ PCIe 7.0 solution is further strengthened by robust industry support. Leading companies such as Intel, Astera Labs, Enfabrica, Kandou, XConn, Rivos, Microchip and Samtec have endorsed Synopsys’ technology, recognizing its critical role in advancing AI and data center infrastructure. This highlights the broad industry support for PCIe 7.0 and underscores the collaborative effort required to meet the complex demands of modern computing environments.

Demonstrations at PCI-SIG Developers Conference

Synopsys showcased two significant demonstrations at the PCI-SIG Developers Conference on June 12 and June 13, 2024. The first demo featured Synopsys PCIe 7.0 PHY IP running at 128 Gb/s with OpenLight’s Photonic IC, illustrating the electrical-optical-electrical (E-O-E) TX to RX connection. The second demo demonstrated the PCIe 7.0 Controller IP successfully establishing a root complex to endpoint connection with FLIT transfer. These demonstrations highlight the technology’s capabilities and readiness for deployment, reinforcing Synopsys’ leadership position in the PCIe ecosystem.

Below is a photo of the Demo setup in June 2024, at the PCI-SIG Developers Conference

 

Below is the eye diagram capture from Synopsys PCIe 7.0 PHY IP supporting 128 GT/s with PAM-4 signaling; the IP enables 512 GB/s bidirectional data transfers with 16 lanes

Summary

Synopsys’ introduction of the industry’s first complete PCIe 7.0 IP solution marks a significant milestone in the evolution of data center technology. By offering early access to this advanced technology, providing a complete and integrated solution, and leveraging its extensive experience and industry position, Synopsys is setting a new standard for high-performance, low-latency, and secure data transfer. The inclusion of linear direct drive optics and support for both cable and optical interconnects further enhances the solution’s applicability, ensuring it meets the diverse needs of modern data centers and AI infrastructures. As the demand for computational capabilities continues to grow, Synopsys’ PCIe 7.0 solution is poised to play a pivotal role in shaping the future of data center technology, backed by strong ecosystem support.

To learn more, visit the Synopsys PCIe 7.0 solutions page.

Also Read:

Synopsys-AMD Webinar: Advancing 3DIC Design Through Next-Generation Solutions

Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification

What to Do with All that Data – AI-driven Analysis Can Help

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Automotive Semiconductor Market Slowing

Automotive Semiconductor Market Slowing
by Bill Jewell on 06-24-2024 at 6:00 pm
Categories: Automotive, Semiconductor Intelligence, Semiconductor Services

Semiconductor Market Growth 2024

We at Semiconductor Intelligence estimate the automotive semiconductor market was $67 billion in 2023, up 12% from 2022. The top twelve suppliers accounted for over three-quarters of the market. Infineon Technologies was the largest automotive semiconductor supplier, at $9.2 billion or 13.7% of the market. NXP Semiconductors was second at 11.2% and STMicroelectronics was third at 10.6%. These top three companies accounted for over one-third of the market. For most of these companies, automotive is a significant part of their total revenues. Of the top six companies, the percentage of revenues from automotive ranged from 34% to 56%.

The automotive semiconductor industry has shown strong growth since 2021 as the industry bounced back from pandemic-related shortages. However, there are signs of a slowdown in the market. The quarterly automotive semiconductor revenue of the top three suppliers reflects this trend. Infineon reported strong growth through 2022 and early 2023 but peaked in 2Q 2023 and has been declining since. Though Infineon’s automotive revenue guidance for 2Q 2024 is for 5% quarter-to-quarter growth. NXP saw quarter-to-quarter revenue growth through 4Q 2023 but reported a 5% decline in 1Q 2024. NXP’s 1Q 2024 report cited continued inventory reductions and a soft overall automotive market in the first half of 2024. ST’s quarter-to-quarter revenue growth was strong in 2022 and 2023, averaging 7%. That growth ended in 1Q 2024 when ST reported a 23% decline in automotive revenue, citing a “deceleration phase”.

Motor vehicle production in 2023 was 93.5 million units, according to the International Organization of Motor Vehicle Manufacturers (OICA), up 10% from 2022. This was the strongest production growth since 26% in 2010 during the recovery from the great recession of 2008-2009. The 93.5 million vehicles in 2023 were still below the all-time high of 97.3 million vehicles in 2017. The industry experienced moderate declines in 2018 and 2019 before dropping 15.4% in 2020 due to pandemic related shutdowns. Yet it appears much of the pent-up demand for automobiles has been satisfied. S&P Global Mobility’s April 2024 forecast is for light vehicle production growth in the 0% to 2% range over the next three years. The mid-points of S&P’s forecast range are shown in the table below.

Despite the slowdown in vehicle production growth, the automotive semiconductor market growth is driven by increasing semiconductor content per vehicle. Two key drivers of the increases are electric vehicles (EVs) and driver-assist systems. EVs, which include battery-electric vehicles (BEVs) and plug-in hybrids (PHEVs), have a higher semiconductor content than other vehicles and thus drive automotive semiconductor market growth. EVs have been growing rapidly in the last few years. Autovista24 estimates EV sales grew 54% in 2022 and 35% in 2023. However, growth is expected to moderate to the 17% to 22% range over the next six years.

Driver-assist systems have also been a key driver of semiconductor content. The ultimate goal of driver-assist systems is self-driving cars, or fully autonomous driving. However self-driving cars are several years away from being commonplace. McKinsey & company has estimated by 2030, 12% of passenger vehicles sold will have fully autonomous driving technology installed (level 4 technology). By 2035, it could be 37%. S&P Global Mobility is more pessimistic, predicting only 6% of light vehicles sold in 2035 will have level 4 autonomous driving installed. Thus, the impact of self-driving cars on the semiconductor market will not likely be of major significance in the next few years.

The overall semiconductor market has been weak the last two years after strong pandemic recovery growth of 26% in 2021. According to WSTS, the semiconductor market only grew 3.3% in 2022 and declined 8.2% in 2023. WSTS’ May 2024 forecast was for strong growth of 16.0% in 2024 and 12.5% in 2025. As we stated in our March 2023 newsletter, automotive has been the lone bright spot in the semiconductor market in the last two years. IDC estimated the automotive semiconductor grew 17% in 2022 and 10% in 2023. IDC’s May 2004 forecast called for the growth of the automotive semiconductor market slow to the 5% to 7% range over the next three years.

The combination of slowing production of light vehicles, slower growth of EVs, and delayed deployment of autonomous-driving vehicles will reduce the growth rate of the automotive semiconductor market. The semiconductor industry can no longer count on automotive as a major driver in the next couple of years. However, other sectors are expected to drive growth. Artificial intelligence (AI) is growing rapidly, spurring growth in the computer sector. The memory market has recovered from weak demand and overcapacity. The smartphone market has turned positive in 2024 after declines in 2022 and 2023. Yet the major automotive semiconductor companies are heavily dependent on automotive for the majority or a major portion of their revenues. Thus, they are likely to lag semiconductor industry growth in the next few years.

Also Read:

2024 Starts Slow, But Primed for Growth

Electronics Turns Positive

Semiconductor CapEx Down in 2024

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System VIPs are to PSS as Apps are to Formal

System VIPs are to PSS as Apps are to Formal
by Bernard Murphy on 06-24-2024 at 10:00 am
Categories: Breker Verification Systems, EDA

System VIP Libraries and Solutions

In the formal world the core technology is extremely powerful, and specialist users need full access to tackle difficult problems. But for many applications, teams prefer canned solutions built on the core technology yet scalable to non-experts. A similar dynamic appears to be playing out between System VIPs and PSS. PSS, the system level simulation standard, is an extremely powerful approach to define portable system level tests. Powerful but different from the more familiar UVM standard for lower-level testing, which can be a speed bump for adoption. Dave Kelf (CEO of Breker Systems) told me that his customers have been telling him that while they like Breker’s PSS tests, they are looking for more canned system VIP solutions, for example around coherency testing. Hence my observation in the title. PSS technologies are still essential as the core, but teams now want more scalability through complete out-of-the-box system VIP solutions for standard system verification needs. While still being able to develop their own specialized tests as needed.

What is a System VIP?

The intent is the same as for an interface IP (USB, etc) – a method to generate traffic to drive design testing, along with checkers and scoreboards to check and monitor interaction between the VIP and the design. However rather than checking protocol compliance, System VIP checks system level behaviors such as cache coherence and interoperability between cores/clusters and the rest of the system.

There are some other important differences. An interface IP acts as a proxy for a design block or an external source. System VIPs by their nature don’t have a design equivalent. They act instead as test overseers for their area of interest. A coherency system VIP is a good example. This will at minimum generate traffic for end-point memory requests on a coherent network, checking and monitoring some level of cache controller and directory behavior, and compliance with the coherence protocol (e.g. MOESI). They probably also should provide some kind of scoreboard to accumulate coverage stats against target objectives.

The basic minimum for System VIP

As a relatively new field, an obvious question is “what should such VIPs provide at minimum?” Breker has developed a top-10 list of requirements over and above the basic VIP expectations, which I find quite useful. I’ll start with a zeroth requirement, implied for their list yet fundamental in PSS implementations.

System level tests scale up very fast. Unit tests (for a mesh network say) may run on a simulator but larger tests demand emulation or prototyping together with a virtual interface for the testbench, then virtual models to run software loads and interfaces to interact with other simulation platforms such as a network traffic simulator. The bigger the design gets (e.g. multi-die) the more varied and distributed the simulation platform becomes, each aspect bringing its own constraints to the test flow. PSS is designed to scale across these diverse modeling systems which is one of the reasons System VIPs are built on PSS.

The first 5 must-have’s start with a no-brainer: targeting system level operational scenarios rather than functional components. Of course, you need a configurable model for the VIP, scalable between different system designs and allowing for reuse. The VIP should be built on a detailed understanding of the domain, in the coherence case all the possible options and protocols, abstracting away detailed implementation choices. It should be scalable from unit (system) tests up to multi-die systems and it should support portability between simulation platforms so if I can abstract some part of the DUT in a virtual model if I want, or use a more accurate RTL model running on an emulator. All still under control of the same System VIP.

Dave and Adnan Hamid (Executive President and CTO) see the next 5 must-haves as areas where Breker offers differentiation. One is the ability to intermix verification objectives, so you can combine coherency checking with power management variations for example. A second is the ability to run multiple scenarios concurrently for stress testing. A System VIP should have self-checking tests and a scoreboard because that’s the kind of complexity hiding users want to see in System VIP. Breker also argue that System VIPs should be user extensible. And they say that these tests should support firmware and UVM code components.

Possibly some more must-haves could be added, but this list looks like a good starting point.

The Breker System VIP portfolio

Cache System Coherency is an obvious VIP since Breker have been working in this domain for a long time. Arm SoCReady provides testing against the hardware sections of Arm’s SystemReady certification, verifying compliance against the system-level hardware requirements. RISC-V SoC Ready provides a similar service design based on RISC-V cores. RISC-V CoreAssurance is an interesting complement for teams building RISC-V cores, who want to get a general assurance that the core will be compliant with a RISC-V ready checkout without having to build a surrounding SoC – or rather many such SoCs to get better coverage.

Breker also provides System VIP class solutions in a number of other domains, listed in the graphic above. I didn’t talk about these with Dave and Adnan but I’m sure they would be happy to share more details. You can learn more HERE.

Also Read:

Qualitative Shift in RISC-V Targets Raises Verification Bar

Breker’s Maheen Hamid Believes Shared Vision Unifying Factor for Business Success

Scaling the RISC-V Verification Stack