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Alphacore at the 2024 Design Automation Conference

Alphacore at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 10:00 am
Categories: Alphacore, Events, IP

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Alphacore Inc., an industry leader in proven high-performance analog and radio-frequency (RF) design building blocks, end products, and intellectual property (IP) licensing and non-recurring engineering (NRE) design services. Our customers include multi-national corporations to ground-breaking startups. We were founded in 2012 with headquarters in Arizona’s center of technological innovation, the Silicon Desert. Our engineering and leadership team combines long histories of delivering innovative data converter, RF, analog and mixed signal products, and complete imaging solutions for critical systems, through their business success at both startups and multinational companies.

We drive next-generation ultra-high speed, ultra-low power, radiation tolerant validated data conversion technology with IP designs enabling applications such as 5G/6G Communications, Beam Forming, Automotive sensing, Aerospace and Defense.

At Alphacore, our customers appreciate the specialized Design Services we offer for high performance/low power integrated circuit intellectual property (IP), Analog/Mixed Signal, harsh environments/robustness where our knowledgeable designers create novel analog building blocks and complete circuits using established and leading-edge process technology nodes for demanding conventional and harsh-environment applications.

Our designs utilize advanced technologies from broad-based suppliers such as TSMC and GlobalFoundries, as well as multiple specialty foundries, based on customer requirements and best fit for the application. Alphacore is a proud member of the GlobalFoundries® (GF®) FDXTM Network.

Visit our website (www.AlphacoreInc.com) to view our ever-growing  portfolio of IP solutions, including a wide range of megasample and gigasample per second (MS/s and GS/s) ADC and DAC IP products (e.g., 11-bit, 5 GS/s ADC A11B5G;  6-bit, 5 GS/s DAC D6B6G).

We specialize in designing high performance solutions for the niche needs of demanding market segments that address harsh environments, including scientific research, aerospace, defense, medical imaging, and homeland security. Accordingly, our engineering team includes seasoned device physics and “Radiation-Hardened-By-Design” (RHBD) experts.

At Alphacore, we offer products that focus on delivering uncompromised world-class performance while also meeting strict size, weight, power, cost (SWaP-C), and environmental constraints. Our customers get the best of both worlds.

Strategic core business areas include:
  • High performance and low power analog, mixed signal, and RF electronics
  • High-speed visible light and infrared Readout ICs (ROICs) and full camera systems
  • Robust Power Management ICs (PMICs) for space and high-energy physics experiments
  • Innovative devices ensuring supply chain and IoT cybersecurity

Our customers benefit from prioritized focus on their projects, keen attention to detail, and a higher level of care and responsiveness that we deliver. It is crucial for us to ensure the complete satisfaction of our customers, both in our products and in the way we do business. That is why we work with companies to create adaptable plans of action, and provide flexibility in our commercial contracts and agreements. We adhere to International Traffic in Arms Regulations (ITAR) and maintain Cybersecurity Maturity Model Certification (CMMC) compliance.

Alphacore is a regular participant supporting this industry-leading event, and we invite you to meet with our Alphacore experts on the exhibit floor. You can contact Alphacore here to schedule a meeting at booth #2332. We hope to see you there!

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Pragmatic at the 2024 Design Automation Conference

Pragmatic at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 8:00 am
Categories: EDA, Foundries, Pragmatic Semiconductor

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Pragmatic is pioneering a fundamental shift in semiconductor technology, delivering lower-cost, lower-carbon intelligence to power the Internet of Everything. Its FlexIC – flexible integrated circuit – technology delivers connect, sense and compute capabilities at a fraction of the cost and carbon footprint of silicon chips.

The FlexIC Foundry® enables rapid, high-volume fabrication with a high level of customisation, taking designs from tape-out to delivery in just weeks. The unique, low-temperature processes consume less energy and water, with fewer harmful chemicals, making Pragmatic one of the most sustainable semiconductor manufacturers in the world.

This year, Pragmatic Semiconductor will be setting up stall at the Design Automation Conference (DAC) for the first time.

Visit stand 1534 to discover their new, industry-standard 300mm wafers, as well as demos including:

  • PlasticARM
    The groundbreaking ultra-minimalist Cortex-M0-based SoC boasting 128 bytes of RAM and 456 bytes of ROM – 12x more complex than previous state-of-the-art flexible electronics
  • Electronic nose
    The world’s first machine-learning-based flexible mixed-signal chip, integrated with a flexible electronic nose sensor array.
  • Temperature sensors
    A selection of Flex-IC based sensors in a thin, flexible form factor:

    • Standalone temperature sensor
      A discrete linear PTC temperature sensor, supporting a wide operating window
    • I2C temperature sensor
      Integrated analogue front-end and digital I2C temperature readout, enabling wide-array sense capability
    • Temperature sensor with heating element and control logic
      Fully integrated heater FlexIC with on-chip sensor, control logic and heating elements
  • NFC products
    For applications including consumer engagement, authentication and tamper detection
About Pragmatic

Pragmatic has developed an integrated circuit (electronic ‘chip’) platform that doesn’t rely on silicon. Our revolutionary technology uses thin-film semiconductors to create flexible integrated circuits that are thinner than a human hair and are significantly cheaper and faster to produce than silicon chips. This provides a compelling alternative for many mainstream electronics applications, as well as enabling new applications not possible with silicon.

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Empyrean at the 2024 Design Automation Conference

Empyrean at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 8:00 pm
Categories: EDA, Empyrean, Events

DAC 2024 Banner
Empyrean Technologies is excited to introduce our comprehensive and highly productive Custom IC design solutions at DAC 2024. Our suite of tools is fully integrated within a design environment tailored for AMS (Analog/Mixed-Signal) designs, covering every step from initial design specification to tape-out. These tools support advanced nodes like 5nm and 3nm and are widely adopted by major semiconductor companies.
Comprehensive Custom IC and PMIC Design Solutions
Key Features:
Seamless Integration: Integrates smoothly with the SPICE simulator ALPS suite, physical verification tool Argus, transistor-level dynamic Electromigration and IR drop (EMIR) analysis tool Patron™, and parasitic extraction tool RCExplorer. This ensures a highly efficient workflow that mitigates risk and boosts productivity.
Comprehensive Reliability Analysis: Our specialized tools provide extensive solutions for EMIR with thermal awareness analysis, ESD/ERC, Monte Carlo, Failure in Time (FIT) calculation, and DSPF-based RC Analysis, enabling early detection of potential design issues.
Fast GPU-Accelerated SPICE Simulator
Empyrean ALPS-GT is a heterogeneous simulation system based on the CPU-GPU platform architecture. Compared to traditional CPU architecture, ALPS-GT offers accelerated processing power and significantly improves performance with GPU Turbo Smart Matrix Solving (SMS-GT) technology. Utilizing the ALPS engine, it provides SPICE accuracy and breaks the bottleneck in large-scale analog and mixed-signal circuit simulation performance, achieving a 10x performance improvement over current CPU-based parallel SPICE for post-layout simulation.
Extraction and Verification Tools
  • Empyrean RCExplorer: Supports transistor-level and standard cell-level post-layout extraction for analog designs. It also supports point-to-point RC analysis and timing delay analysis.
  • Empyrean Argus: A physical verification tool that includes DRC and LVS, helping improve verification quality and efficiency.
PMIC Design Solutions
Empyrean Technologies offers a comprehensive design flow specifically tailored for PMIC (Power Management IC) designs. This suite of tools is fully integrated within a design environment covering every step from initial design specification to tape-out, delivering performance, accuracy, and user-friendliness.
Key Features:
  • Comprehensive Power Device Analysis: Specialized tools for analyzing power devices, including accurate Rds(on) value calculations, ensuring PMIC efficiency and avoiding costly re-spins.
  • Efficient EMIR Analysis: Advanced Electromigration and IR Drop (EMIR) analysis tools provide deep insights into power integrity and noise, optimizing designs for robust performance.
  • Key Network RC Analysis: A fast DSPF-based RC Analysis tool evaluates critical RC effects in large power networks, detecting potential issues early in the design process.
Highlighted Products:
  • Empyrean Patron™: A state-of-the-art power integrity tool designed to ensure the performance and reliability of analog and mixed-signal designs. It specializes in transistor-level power and signal net electromigration (EM) analysis and power net IR-drop analysis.
  • Empyrean Polas™: Offers a powerful solution for analyzing and optimizing power devices. It is designed to handle the complexities of PMIC designs, providing a highly integrated system that includes extraction, simulation, results viewing, and analysis.
Digital SoC Design Solution
Empyrean Technology also provides a comprehensive SoC (System on Chip) solution, including:
  • Standard cell library characterization
  • Memory characterization
  • Mixed-signal IP characterization
  • Standard cell library and IP validation
  • Clock diagnosis and analysis
  • Accurate timing simulation and analysis
  • Timing and power optimization
  • Layout integration and analysis
  • Digital physical verification
  • Parasitic RC extraction

These solutions ensure that designers can meet the stringent demands of modern electronic designs with confidence and efficiency. Empyrean’s participation at DAC 2024 will showcase its commitment to pushing the boundaries of electronic design automation and providing cutting-edge solutions to the semiconductor industry.

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AMIQ EDA at the 2024 Design Automation Conference

AMIQ EDA at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 6:00 pm
Categories: AMIQ EDA, EDA, Events

DAC 2024 Banner

AMIQ EDA is a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis. We’ve been attending DAC for many years and are pleased to do so again in 2024. We exhibit at this show for several reasons. We’re always looking for new users and our booth is a great place for them to check us out. We also meet with many current users, providing updates on what we’re doing and sometimes just saying hello.

As veterans in the EDA industry we know many people from other vendors and organizations, so DAC is a great opportunity to catch up. Finally, the location in San Francisco is just an hour from the heart of Silicon Valley, so we always stay a few extra days to visit users at their facilities. Quite often we will offer a short training course for new users or a presentation on the latest features for those who already know us. Everyone is interested in what’s new and what we’re working on for the future.

So what is new this year? For a start, we have added some cool features for SystemVerilog users to our Design and Verification Tools (DVT) Eclipse IDE and DVT IDE for Visual Studio (VS) Code. We now offer runtime elaboration of Universal Verification Methodology (UVM) code, making it easier to find and fix coding errors within the IDE editor. UVM is a complex verification library with lots of SystemVerilog macros, so the ability to elaborate and check code on the fly is valuable.

We’ve added the ability to precompile or “shallow compile” portions of code to speed up the full build process. This is helpful because verification environments for huge chips are also huge. Not having to compile the full code set all at once saves time and shortens the find-fix-verify loop for coding errors. We’ve also added support for SystemVerilog AMS, reflecting the fact that many of our users are designing mixed-signal chips.

We’ve also significantly improved our ability to handle SystemVerilog files that contain “preprocessor” statements in other languages such as Perl or Python’s Jinja2 library, or even in proprietary languages. Users can edit such files just as if they were pure SystemVerilog. They can take advantage of all their favorite IDE capabilities: navigational hyperlinks, autocomplete, on-the-fly incremental compilation and error detection, quick fixes, refactoring, and more.

We’ve not forgotten our other products. Our Verissimo SystemVerilog Linter now checks around 900 rules, more than 100 of which were added in the past year. Our Specador documentation tool now has a new HTML interface plus support for the PDF and Markdown formats. So, yeah, there’s a lot new to see at DAC. We’re happy to show demos of any features in our booth or to arrange a virtual or physical visit with design and verification teams who may not be at the show.

As we did last year, we’re sponsoring the City Bytes & Beverages Hospitality Zone, where attendees can buy a quick lunch that’s a lot more interesting than the usual convention center hot dogs and frozen pizza. There will be AMIQ EDA signs around to remind everyone that we are long-time supporters of DAC. We invite everyone to stop by our booth!

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proteanTecs at the 2024 Design Automation Conference

proteanTecs at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 4:00 pm
Categories: Analytics, Events, proteanTecs

DAC 2024 Banner

Meet with proteanTecs at DAC. Explore our full set of health and performance monitoring solutions. We’ll be showcasing our latest products and solutions, and we’d love to connect while you’re there. Visit booth #2417 to explore our health and performance monitoring solutions.

Also – Don’t miss out on our daily sessions in our in-booth theater, featuring guest speakers from top companies in ASIC, design, IP, services, cloud, and proteanTecs.

We are also accepting booking for a private session in our meeting room, presenting new solutions and features tailored to your needs

proteanTecs offers a first-of-its-kind, in-system self-monitoring solution. With machine learning, we unlock deep insights increasing reliability, optimizing power, and enhancing quality.

During the show, we will be presenting multiple solutions, including:

  1. Power and Performance
  2. Reliability, Availability, Serviceability
  3. Functional Safety & Diagnostics
  4. Product Bring-Up
  5. Operations & Quality
  6. Die-to-Die Interconnect
Meet us at Booth 2417, 2nd floor

See the full booth agenda, and book a meeting at –

Meet proteanTecs at DAC 2024

About proteanTecs

proteanTecs is the leading provider of deep data analytics for advanced electronics monitoring. Trusted by global leaders in the datacenter, automotive, communications and mobile markets, the company provides system health and performance monitoring, from production to the field.  By applying machine learning to novel data created by on-chip monitors, the company’s deep data analytics solutions deliver unparalleled visibility and actionable insights—leading to new levels of quality and reliability. The company is headquartered in Israel and has offices in the United States, India, South Korea and Taiwan. For more information, visit www.proteanTecs.com.

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Sigasi at the 2024 Design Automation Conference

Sigasi at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 2:00 pm
Categories: EDA, Events

DAC 2024 Banner

Sigasi® will demonstrate its Sigasi Visual HDL™ (SVH™) portfolio during DAC, showing how it supports the shift-left methodology for chip design, catching specification errors early in the design cycle and fixing the inefficient HDL-based design flow.

The traditional HDL workflow cannot accommodate the massive amounts of design specifications from GenAI creations, high-level synthesis results, and other complex SoC IP. These new levels of abstraction need to plug and play alongside large HDL files—that contain functionality created with domain-specific knowledge—to integrate hundreds of billions of transistors on a chip.

The comprehensive Sigasi Visual HDL portfolio is an HDL platform able to take advantage of the shift-left methodology and give hardware designers and verification engineers better insight during the design progress. They can easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. SVH does so by standardizing the concept of an HDL design project, bringing simulation and synthesis projects into a world of integrated development, synchronous visualization, and shift-left validation.

Integrated Development: SVH is fully integrated with Microsoft’s Visual Studio Code (VS Code), the most popular IDE, according to Stack Overflow’s 2019 survey, with a rich marketplace of productivity tools. It includes sophisticated applications to easily use git and GitHub Source Control Management, as well as a selection of utilities to facilitate mundane tasks like extracting TODO comments or bookmarking important sections in HDL code.

Synchronous Visualization: SVH lets users move seamlessly through hierarchy views and graphics that update instantaneously as they make changes in their code.

Shift-Left Validation: SVH flags problems while users enter HDL code. Starting with syntax and semantics, it enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches UVM abuses.

SVH comprises a tiered portfolio, offering three commercial editions meant to meet specific SoC design and verification challenges. The new offering also unveils Sigasi’s new AI chatbot, SAL, a chatbot that works with a local model or a remote OpenAI API and can generate, check, and explain HDL code. Each tier of SVH offers a comprehensive package of features, including type-time syntax and semantic checks and guardrails that enforce coding styles, policies, and standards. Regardless of which tier they use, engineers receive instant feedback and warnings for all files associated with a project.

Additionally, Sigasi offers a fully functional Community Edition that lets users explore its features for non-commercial uses, especially students and teachers learning and teaching the fundamentals of HDL design.

Sigasi will fly its new logo and tagline “Put Your Semicolons to Work” while exhibiting and demonstrating Sigasi Visual HDL at DAC Booth #2416 (second floor). DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

More details can be found on the Sigasi website or by emailing sales@sigasi.com.

To arrange a demo or private meeting to talk about Sigasi Visual HDL, send an e-mail to: dacmeeting@sigasi.com.

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Innova at the 2024 Design Automation Conference

Innova at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 12:00 pm
Categories: Defacto Technologies, EDA, Innova

DAC 2024 Banner

Design projects are becoming more and more complex. The success of a design project is tightly linked to the best preparation. Having an accurate and precise prediction of either project design resources or design parameters, with a plan to react in an appropriate way is crucial and cost saving.

A typical example is the availability of licenses for all designers during experimentation and production. Either pre-synthesis which may require running parallel flows, each flow with needed licenses for restructuring a design, run several synthesis runs, etc. And also, post-synthesis when running tools with significant runtime such as simulation and placement and routing.

Having the possibility to define precisely the number of licenses, knowing peak usage and threshold, and predict the related period this will happen is key to negotiate contract with Vendors (we all know how much a license increment can cost). Same for the hardware resources, anticipate the period we will need additional resources, on cloud for example can lead to a different resource allocation strategy.

Innova leverage advanced artificial intelligence algorithms to provide a design environment and infrastructure to collect data, predict the expected resources, and predict also how design parameters may evolve given data from previous design projects.

For a particular SoC design flow, Innova’s prediction capabilities can even be applied as a “correlation dashboard” between design steps. This means that Innova PDM software can easily answer the question of how much the execution of a given design step would impact the result of a subsequent other design step.  In summary, Innova PDM’s advanced algorithms analyze historical project data to provide accurate predictions, enabling design teams to make informed decisions at each stage. This reduces the risk of unforeseen complications and ensures a smoother progression from one design step to another.

Innova brings also another dimension to the SoC design process and project, which is the eco-compliance of the entire design environment. Innova PDM gives to the user, the ability to start a new design project with a limited impact on ecology and better control on power consumption. Thanks to its qualification metrics of designs flows, design data and related compute resource configurations, Innova PDM helps filtering between different design flow options and possibilities through a unique eco-friendly score.

If you are a designer or a CAD manager, involved directly or indirectly in success decisions of complex design projects, visit the Innova booth (#1528, first floor) and hear about this new and unique automation solution whose customization capabilities will help anticipate needed resources for future projects.

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Defacto at the 2024 Design Automation Conference

Defacto at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 10:00 am
Categories: Defacto Technologies, EDA, Events

DAC 2024 Banner

Defacto continues to confirm its SoC Compiler as becoming the “de facto” SoC integration solution for large SoC designs. This year they are coming to DAC to share customer success stories of building the largest SoCs in the market from specification to RTL + collaterals such as UPF by including thousands of IP cores! All done within in less than an hour! It’s quite impressive to see this kind of results because with such short runtime, designers can afford to rerun several configurations in a single day!

Beyond RTL, SoC Compiler is now fully supporting all IP-XACT versions. In particular, even though their specialty remains RTL, they now offer full support for the IP-XACT format with joint management between the two formats. This joint management has enabled several major semiconductor companies to increase their use of the tool and test it on very complex designs.

This year, Defacto also closely collaborated with Arm to offer a joint and fully automated SoC generation solution. Indeed, if you have seen Arm’s latest announcements on their new IP configuration and SoC architecture description tool called IP Explorer, Defacto’s SoC Compiler tool is automatically plugged in order to generate Arm-based SoCs described by the user. In summary, this joint IP Explorer/SoC Compiler solution is the shortest path from defining ARM-based system architecture to implementation and design verification.

This year at DAC, Defacto is also promoting the ease of use of its solution, especially with its Python APIs. It’s true that today the use of Python is increasingly frequent, particularly among young engineers. Python also offers a wide range of advantages, such as: its very active community, ease of debugging, execution speed (compared to Tcl), and the vast number of available open-source libraries. Therefore, it can no longer be ignored in the use of EDA tools, and it is no longer possible to continue making Tcl and Python coexist in design flows knowing the heaviness of the process. Defacto made the choice two decades ago to build its software so that Python would be a built-in API, and today this allows many users to benefit from the power of this language. Defacto estimates that today more than 60% of its users switched to its Python API.

Last and not least, Defacto is revealing at this DAC and for the first time AI prediction capabilities with an opportunity for only few customers to start experimenting in 2024 unique capabilities and adding predictability to complex SoC design projects.

As a conclusion, Defacto’s solution has greatly progressed since last DAC, and this DAC looks promising if we consider these first announcements.

Defacto will be exhibiting at DAC, June 24-26 at first floor (booth #1528), Their technical experts will be present to provide more detailed product update. Make sur to contact them here (https://defactotech.com/contact)  to schedule a meeting at their booth. Hope to see you there!

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Codasip at the 2024 Design Automation Conference

Codasip at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 9:00 am
Categories: Codasip, Events, IP, RISC-V

DAC 2024 Banner

Codasip will be demonstrating its new L110 core alongside Codasip Studio Fusion at #61DAC. Codasip L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market. ​The core offers extensive configurability, allowing different area/performance trade-off levels, and support for standard RISC V code-size extensions. Additionally, the L110 is fully customizable allowing designers to extend the processor to achieve massive PPA improvements to differentiate their products. Designed by the Codasip team using Codasip Studio Fusion, L110 is ideal for small-area, low-power applications, such as state machine replacements, sensor controllers, and IoT edge.

Codasip Studio has been the toolset to generate both the RTL and the software development tools from one processor model for years. The latest version, Codasip Studio Fusion, improves this fundamental capability and adds a layer of segmentation. You can configure the core from set options, create custom instructions within set bounds, or design freely.

Codasip will be showcasing both of these new products at the 2024 DAC show through the, Anomaly Detection in Near-Sensor Embedded Devices Demo. Which enables for AI/DSP on Tiny Processors optimized through Bounded Customization.

Codasip is a processor solutions company which uniquely helps developers to differentiate their products. We are Europe’s leading RISC-V company with a global presence. Billions of chips already use our technology.

In today’s technology market, differentiation is everything. The difference between success and failure. And, in chip design, this difference is quite literally wafer thin. With increasing transistor costs, your developers can no longer rely on semiconductor scaling and legacy processors to achieve your goals. The only way forward is to implement custom compute with designs tailored to your applications.

We deliver custom compute through the combination of the open RISC-V ISA, RISC-V ISA processor design automation and high-quality processor IP. Our innovative approach lets you easily customize and differentiate your designs. You can develop high-performing, and game-changing products that are truly transformational.

Unlike traditional design approaches, our custom compute enables you to take control of your destiny. We allow you to set free your creativity and to use your ingenuity. We’re at the leading edge of a transformation in processor design, providing our partners, the most innovative companies on the planet, with a proven alternative to the norm.

At Codasip, we enable you to design different.

It’s time to take the leap.

Architect your ambition.

See you at DAC!

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Siemens Hardware-Assisted Verification at the 2024 Design Automation Conference

Siemens Hardware-Assisted Verification at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 8:00 am
Categories: EDA, Events, Siemens EDA

DAC 2024 Banner

Visitors to Siemens’ booth (#2521) at the 61st Design Automation Conference (DAC) will see on display the Veloce™ CS system that unifies hardware emulation, enterprise prototyping and software prototyping into one hardware-assisted verification and validation platform.

The display will feature the three single-blade system designed for engineering teams to add scalability and capacity as needed: Veloce Strato CS for emulation, Veloce Primo CS for enterprise prototyping, and Veloce proFPGA CS for software prototyping.

The evolution of SoC and system level design made the use of hardware-assisted verification a necessity, an opportunity Siemens embraced. It worked with key customers and partners to develop Veloce CS’ new, fully unified software architecture and innovative hardware built on two highly advanced ICs –– Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC for enterprise and software prototyping.

Architected for congruency, speed, and modularity across all three platforms, the Veloce CS system supports design sizes from 40 million gates up to designs integrating more than 40+ billion gates. Veloce CS executes full system workloads with superior visibility and congruency by selecting the right tool for the task, as each task has unique requirements. The result is faster time to project completion and assists in decreasing cost per verification cycle.

Veloce CS system addresses the specific needs of hardware, software and system engineers who play an essential part in delivering the world’s most advanced electronic products by providing the right tool for the task:

  • Veloce Strato CS delivers significant emulation performance improvement over Veloce Strato, up to 5x maintaining full visibility and it scales from 40 million gates (MG) to 40+ billion gates (BG).
  • Veloce Primo CS, based on AMD’s latest Versal Premium VP1902 FPGA, a congruent enterprise prototyping system that scales from 40MG to 40+BG.

Both the Veloce Strato CS and Veloce Primo CS solutions run on the same operating system for congruency while providing the freedom to seamlessly move between platforms. This can dramatically accelerate ramp up, setup time, debug, and workload execution.

  • Veloce proFPGA CS also leverages the AMD Versal Premium VP1902 FPGA-based adaptive SoC, which delivers a fast and comprehensive software prototyping solution, scaling from one FPGA to hundreds. This performance, together with its flexible and modular design, can help engineers accelerate firmware, operating system, application development and system integration tasks.

The entire Veloce CS system is available in a modular blade configuration fully compliant with modern datacenter requirements for easy installation, low power, superior cooling, and compact footprints. Further, the Veloce proFPGA CS solution provides a desktop lab version for additional user flexibility.

General availability of the three hardware platforms is planned for < >2024. Pricing is available upon request. For more information, visit the Siemens website. To arrange a demonstration or private meeting at DAC, send email to

DAC registration is open.

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