DVCon turns 30 this year which is a very big deal. My oldest child also turns 30 this year which really puts things in perspective looking back at what we have all accomplished during that time. DVCon originally started as a user’s group at the 1988 Design Automation Conference in Anaheim California and the rest as they say is history.
Continue reading “DVCon 2018 Mentor Graphics and SemiWiki”
Jalopnik’s report that car maker Fiat Chrysler Automobiles (FCA) had experienced a failed software update that had thrown the infotainment systems in some MY 2017-18 vehicles into a never-ending cycle of rebooting was a reminder that cars are indeed becoming smartphones on wheels. Blackberry CEO John Chen has no doubts on this subject. Chen expects Blackberry’s QNX to be the operating system of choice for this new paradigm.
With the onset of vehicle connectivity, car owners are confronting issues that were previously confined to phones, televisions or desktop computers. Is this device secure? Should I accept this software update? How do I get help? How do I reboot?
Blackberry was there at the creation, providing its QNX operating system underlying General Motors’ OnStar telematics system. (Blackberry acquired QNX from Harman International in 2010.) Software updates are nothing new for QNX or Blackberry.
When John Chen took the reins as interim CEO of Blackberry in 2013 the company was well into its downward spiral in the handset business, mirroring the experience of Nokia in the face of an industry-wide UI and OS shift driven by Alphabet, with the help of Samsung, and Apple. Both Blackberry and Nokia sought to reverse their fortunes by shifting their focus from one operating system to another.
Nokia’s switch from Symbian to Windows failed miserably. Blackberry’s leap from its proprietary operating system to QNX also failed, but, unlike Nokia, Blackberry was able to shift its focus to leveraging its IP portfolio and security credentials while endeavoring to make cars more like smartphones – a process that is unfolding slowly but steadily while the rest of Blackberry’s business continues to turn around. (Q3 2018 earnings beat estimates – though the automotive portion of Blackberry’s business was relatively flat.)
What has emerged from this effort, first hinted at last year, is an expansion of Blackberry’s QNX real-time operating system beyond in-dash infotainment systems, where the company dominates, to vehicle gateways and safety systems while bringing cybersecurity and over-the-air software update technology along for the ride. (Important to note QNX’s use in other embedded environments including aerospace, industrial automation and numerous other industries and applications.)
The shift in strategy points toward an increase in Blackberry software content per car and a more central role for the company in defining future vehicle architectures. Signing on for this new adventure are strategic partners including Denso, Intel, Nvidia, Delphi, Renesas, Baidu, Bosch, Magna, Qualcomm, Ford and Volkswagen among others.
The transformation of Blackberry has not arrived without considerable pain and substantial staff reductions. Like Nokia’s, Blackberry’s handset decline was precipitous allowing little margin for error for the company’s shift away from the smartphone business.
Even more dicey has been attempting to leverage the generally slow growth, low margin and long product life-cycle automotive business as a fulcrum. Chen’s efforts have so-far proven successful in spite of the challenges.
The bottom line is that the car has indeed become or is becoming a smartphone on wheels. What company is better positioned to bring about this transformation than a company, Blackberry, with unmatched security credentials and an already dominant position in the dashboard?
In fact, the onset of the Android OS in vehicle dashboards at Honda, Cadillac and across Asia, will be facilitated at some carmakers by Blackberry’s QNX operating system and its hypervisor technology. Unlike a smartphone, a car is a multiple network, multiple OS environment where competing systems can co-exist.
Blackberry’s work with Nvidia, Qualcomm, Renesas and Intel sets the stage for an expansion of its hypervisor technology enabling re-use of powerful embedded processing resources. Blackberry is not alone in this regard, but it is a leader.
At the core of Blackberry’s updated automotive strategy is the rapid industry-wide adoption of advanced safety systems and autonomous driving development and the growing requirement for an OS like QNX with its ISO 26262 ASIL D safety certification. The demand is paving the way to a broader role for Blackberry in cars. So, yeah, cars are becoming more like smartphones. Which is very good news for Blackberry.
For more information:
The Internet of things (IoT) is growing rapidly and 2018 will be a fascinating year for the IoT industry. IoT technology continues to evolve at an incredibly rapid pace. Consumers and businesses alike are anticipating the next big innovation. They are all set to embrace the ground-breaking impact of the Internet of Things on our lives like ATMs that report crimes around them, forks that tell you if you are eating fast, or IP address for each organ of your body for doctors to connect and check.
In 2018, IoT will see tremendous growth in all directions; the following 8 trends are the main developments we predict for next year:
Trend 1 —Lack of standardization will continue
Digitally connected devices are fast becoming an essential part of our everyday lives. Although the adoption of IoT will be large, it will most likely be slow. The primary reason for this is lack of standardization.
Though industry leaders are trying to develop specified standards and get rid of fragmentation, it will still exist. There will be no clear standards in the near future of IoT. Unless a well-respected organization like IEEE stepped-in and leads the way or the government imposes restrictions on doing business with companies if they are not using unified standards [6].
The hurdles facing IoT standardization can be divided into 3 categories; Platform, Connectivity, and Applications:
All three categories are inter-related, you need all them to make all them work. Missing one will break that model and stall the standardization process. A lot of work needed in this process, and many companies are involved in each of one of the categories, bringing them to the table to agree on a unifying standards will be a daunting task [12].
Trend 2 — More connectivity and more devices
The speedy proliferation of IoT in past 3 years has resulted in billions of interconnected devices. As the consumer continues to stay hooked to more gadgets. The number of connected devices grew exponentially every year. By 2018 it will at least double and touch a whopping the mark of 46 Billion by 2021. More IoT devices will enter the channels, more than ever before. A clear indication of our direct dependency over the gadgets and that’s how our future is shaped.[6]
As IoT continues to expand we will certainly see an increase in devices connected to the network in different areas in business and consumer markets. Smart devices will become the de-facto for people to manage IoT devices. The benefits of using smart devices in that capacity include boosting customer engagement, increasing visibility, and streamlining communication that will include new human-machine interfaces such as voice user interface (VUI) or Chatbot.[4][2]
Trend 3 — “New Hope” for security: IoT & Blockchain Convergence
As with most technology, security will be the major challenge that needs to be addressed. As the world becomes increasingly high-tech, devices are easily targeted by cyber-criminals. Evans Data states that 92% of IoT developers say that security will continue to be an issue in the future. Consumers not only have to worry about smartphones, other devices such as baby monitors, cars with Wi-Fi, wearables and medical devices can be breached. Security undoubtedly is a major concern, and vulnerabilities need to be addressed.
Blockchain is a “new hope” for IoT Security. The astounding conquest of Cryptocurrency, which is built on Blockchain technology, has put the technology as the flag bearer of seamless transactions, thereby reducing costs and doing away with the need to trust a centered data source.
Blockchain works by enhancing trustful engagements in a secured, accelerated and transparent pattern of transactions. The real time data from an IoT channel can be utilized in such transactions while preserving the privacy of all parties involved.[4][2]
The big advantage of blockchain is that it’s public. Everyone participating can see the blocks and the transactions stored in them. This doesn’t mean everyone can see the actual contents of your transaction, however; that’s protected by your private key.
A blockchain is decentralized, so there is no single authority that can approve the transactions or set specific rules to have transactions accepted. That means there’s a huge amount of trust involved since all the participants in the network have to reach a consensus to accept transactions.
Most importantly, it’s secure. The database can only be extended and previous records cannot be changed (at least, there’s a very high cost if someone wants to alter previous records). [10][3][4] [7]
In 2018 increased interest in Blockchain technology will make the convergence of Blockchain and IoT devices and services the next logical step for manufacturers and vendors, and many will compete for labels like “Blockchain Certified”.
Trend 4 — IoT investments will continue
IDC predict that spending on IoT will reach nearly $1.4 trillion in 2021. This coincides with companies continuing to invest in IoT hardware, software, services, and connectivity. Almost every industry will be affected by IoT, which means many companies will benefit from its rapid growth. The largest spending category until 2021 will be hardware especially modules and sensors, but is expected to be overtaken by the faster growing services category. Software spending will be similarly dominated by applications software including mobile apps.
IoT’s undeniable impact has and will continue to lure more startup venture capitalists towards highly innovative projects. It is one of those few markets that have the interest of the emerging as well as traditional venture capital. While the growth next year is firmly attested and the true potential is yet to be unearthed, IoT ventures will be preferred over everybody else. Many businesses have assured adding IoT to their services model from the Transportation, Retail, Insurance and Mining industries [4][6].
Trend 5 — Fog Computing will be more visible
Fog computing allows computing, decision-making and action-taking to happen via IoT devices and only pushes relevant data to the cloud, Cisco coined the term “Fog computing “and gave a brilliant definition for Fog Computing: “The fog extends the cloud to be closer to the things that produce and act on IoT data. These devices, called fog nodes, can be deployed anywhere with a network connection: on a factory floor, on top of a power pole, alongside a railway track, in a vehicle, or on an oil rig. Any device with computing, storage,andnetwork connectivity can be a fog node. Examples include industrial controllers, switches, routers, embedded servers, and video surveillance cameras.”
The benefits of using Fog Computing are very attractive to IoT solution providers, some of these benefits: minimize latency, conserve network bandwidth and operate reliably with quick decisions. Collect and secure wide range of data, move data to the best place for processing with better analysis and insights of local data. Blockchain can be implemented at the level of fog nodes too. [11]
Trend 6 — AI & IoT will work closely
Amalgamation of IoT data analytics with AI for applications ranging from elevator maintenance to smart homes, will progress rapidly over the coming two years. Platform and service providers are increasingly delivering solutions with integrated analytics designed to feed data directly into AI algorithms. Another important advantage of using AI is supporting the optimization and adaptation of both IoT devices and related processes and infrastructure.
AI can help IoT Data Analysis in the following areas: data preparation, data discovery, visualization of streaming data, time series accuracy of data, predictive and advanced analytics, and real-time geospatial and location (logistical data). [10]
Trend 7 — New IoT-as-a-Service (IoT-a-a-S) business models
Transformational business models will develop in many IoT verticals over 2018-2019, supported by Big Data and AI tools. In these models, the value is in the convenience of the service for end customers (on-demand and not requiring heavy upfront expenditure), and the usage data that is collected, analyzed, and fed back into suppliers’ businesses and processes.
But the potential for IoT business model transformation extends beyond this, to encompass an increasing variety of more complex, as-a-service business models that disrupt existing industries, particularly for areas such as heavy industry, transport and logistics, and smart cities.
For these industries, IoT solutions can enable more of an ongoing, managed service relationship with both technology providers and end customers. One selling point is that costs can be more directly linked to ongoing measured usage or to specific trigger events captured by IoT sensors (e.g., “break-the-glass” solutions in which sensors pick up when a building or car is broken into). Another is that costs may be spread over time, shifting from upfront Capex to a more regular Opex outflow. Examples of such models include lighting-as-a-service (L-a-a-S), rail-as-a-service (R-a-a-S), and even elevators-as-a-service (E-a-a-S).[1]
Trend 8— The need for skills in IoT’s Big Data Analytics and AI will increase
Dynamic data sharing is at heart of IoT and Big Data Analytics will be instrumental in building responsive applications. Integrating IoT data channels with AI to retrieve on demand analytical insights has already gained momentum this year and will definitely grow exponentially in 2018. Subsequently, the need for Big Data and AI skills will rise, while most IoT service providers have highlighted the shortage for such extensively skilled candidates, internal learning programs in close proximity with R&D has set to be launched in many companies.[1][10][8]
This article was published on IEEE-IoT
Ahmed Banafa Named No. 1 Top VoiceTo Follow in Tech by LinkedIn in 2016
Read more articles at IoT Trends by Ahmed Banafa
References:
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All figures: Ahmed Banafa
Also read:CEVA Ups the Ante for Edge-Based AI
There’s been a lot of discussion of late about deep learning technology and its impact on many markets and products. A lot of the technology under discussion is basically hardware implementations of neural networks, a concept that’s been around for a while.
What’s new is the compute power that advanced semiconductor technology brings to the problem. Applications that function in real time, on real products are now possible. But what exactly does a deep learning chip look like? What technology drives these designs?
I caught up with Mike Gianfagna recently to discuss deep learning and pose some of these questions. Besides buying lunch, Mike told me some interesting things about deep learning chips based on what’s happening at eSilicon.
First of all, chips targeted at deep learning applications are often not “chips” at all using the traditional definition of a monolithic piece of silicon in a package. Rather, they are combinations of monolithic chips and massive external memories all integrated in a sophisticated 2.5D package. The use of 2.5D makes the whole process a good bit more complex but allows the delivery of significant new capabilities.
If you poke around inside one of these 2.5D deep learning packages, you typically find HBM2 memory stacks, along with the associated HBM PHY and controller. High-speed SerDes is also typically needed for off-chip communication. The actual deep learning chip itself typically has optimized multiply-accumulate functions – many of them. These designs have a need for specialized on-chip memories for efficiency and power reasons. So, a deep learning chip looks something like this:
To really take advantage of advanced silicon technology, customization to optimize deep learning algorithms is a very good strategy. That means building ASICs, and that’s where eSilicon comes in. There aren’t many places you can go to implement a deep learning ASIC. There are lots of technical challenges involved.
Performance demands use of FinFET technology, and that raises the stakes quite a bit. FinFET-class ASICs are substantially more challenging to design than older planar technology chips. Customizing memory for the multiply-accumulate design is tricky to get correct. Interfacing HBM memory stacks to the ASIC also requires very high-performance circuits – something not everyone is good at. And then there’s the 2.5D package. Integrating multiple components on a silicon interposer requires a lot of skill as well. Assembly yield is impacted by thermal and mechanical stress. Testing these devices also requires some new approaches, as does the actual design of the interposer itself.
And on top of all this, Mike explained that it takes a team of ecosystem partners to get the job done. Critical IP is typically sourced from more than one vendor. Fabrication of the chip is done by the foundry, but HBM memory stacks, interposers and 2.5D packages all come from other vendors. It takes a well-coordinated team to get all this done reliably.
As the lattes were being served at the end of our lunch, Mike told me about an event at the Computer History Museum in Mountain View on March 14. eSilicon is teaming up with Samsung Memory, Amkor and Northwest Logic to explain how that group of ecosystem partners works together to build deep learning ASICs. They also have a keynote address from Ty Garibay, the CTO of Arteris IP. I’ve been to eSilicon events in the past and they are typically very informative. The wine and food are pretty good, too. If you want to dig into deep learning I would attend this event, absolutely. Check out more about the seminar, or register to attend. SemiWiki will be there.
Also read: High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory
At Intel back in the late 1970’s we wanted to know what process corner each DRAM chip and wafer was trending at so we included a handful of test transistors in the scribe lines between the active die. Having test transistors meant that we could do a quick electrical test at wafer probe time to measure the P and N channel transistor characteristics, providing valuable insight for the specific processing corner. We would’ve loved to have this kind of test transistor data for processing embedded into each die as well. The increase in transistor complexity for DRAM chips has been quite dramatic over the years, so in 1978 we had 16Kb DRAM capacity while today the technology has reached 16Gb, an increase of 1,000,000X. On the SoC side we see an equally impressive increase such that a GPU from NVIDIA now contains 21 billion transistors and 5,120 cores using a 12nm process from TSMC. So whether you are designing a CPU, GPU, SoC or a chip for IoT applications requires that IC designers understand how process variability impacts each die and packaged part during operation. Other design concerns include:
Moore’s Law has held up pretty well until the 28nm node, and below that node the price learning curve hasn’t been as rewarding. Even clock speeds have stalled in the GHz range. Short-channel effects started to hurt current leakage values, limiting battery life and performance, so new transistor approaches emerged like FinFET and SOI. Device variability is a dominant design issue today, meaning that even adjacent transistors on the same die can have different Vt (Voltage Threshold) values caused by different dopant values or silicon stress caused by proximity to isolation wells – layout dependent effects. Just take a look at how variations have increased with each smaller geometry node from 90nm down to 22nm:
Switching speed delay variations against supply voltage across process nodes (Source: Moortec)
For a 22nm process node with a 475mV supply level you can expect switching speed delay variations of 25%, while at the more mature process node of 90nm the delay variations are only 9%.
With FinFET technology in use since 22nm there are some new concerns caused by higher current densities like localized heating effects, so designers using 14nm, 10nm, 7nm and 5nm need to be aware of self-heating because it impacts the aging of transistors and the Vt actually begins to shift over time as shown below:
Vth degradation from NBTI and HCI effects (Source: Moortec)
The dark curve above shows a Vdd value of 1.3V being used for transistors, and over a 10 year operating period the nominal Vt value of 0.2V can be changed by over 4% due to negative bias temperature instability (NBTI) and hot carrier injection (HCI) effects. That Vt shift can simply slow down your IC or cause it to fail meeting your clock speed specification.
With lower Vdd values being used coupled with higher current levels and higher interconnect resistivity you can expect to see internal supply levels of a chip drooping from the values supplied at the pins. Knowing the actual internal Vdd levels can be quite critical.
To meet stringent power consumption requirements many approaches have been taken, a popular technique is called Dynamic Voltage and Frequency Scaling (DVFS) where the chip has the ability to change local Vdd values in order to throttle or speed up the frequency of operation. Reducing the Vdd value quickly reduces power consumption because power is related the square of the Vdd value. So lowering the Vdd value locally allows you to tune for power consumption. Adding DVFS does increase the logic overhead and requires even more simulation during the design phase. Turning local Vdd lines on causes a rush of current, triggering an IR drop issue which can cause transient errors in the silicon logic behavior.
IC designers can deal with all of these effects by a couple of approaches, the earliest approach was to design for worst-case conditions although at the expense of leaving margin on the table. A newer approach is to actually embed in each chip some specialized IP for three tasks:
Knowing your actual PVT (Process, Voltage, Temperature) corner in silicon is incredibly useful to controlling your chip for maximum performance. With an embedded PVT monitor you can quickly perform speed binning without having to run extensive functional, full-chip testing. Aging effects on Vt can be measured with an embedded PVT methodology.
Using a temperature sensor at strategic locations on an SoC can then be used to dynamically measure how hot each region is, then decide to alter the Vdd values to keep the chip operating reliably while still meeting timing, even as the chip ages over time. A multi-core SoC with temperature sensors can dynamically assign new instructions to the core with the lowest temperature value, balancing the work load so as to not over-heat any one core with too many sustained operations. The mean time to failure for ICs is directly related to operating temperature levels, so with embedded PVT you can control the aging effects.
Moortec is the IP vendor that designed PVT monitoring for popular process nodes and they have internally created the sensors and controllers to interpret the data on-chip. Yes, you have to use a tiny amount of silicon area to implement the PVT monitoring, however the benefits far outweigh the die size impact. The process monitor can tell you the exact speed of your transistors to let you know how close they are to nominal values. Benefits of using these monitors include:
You can use PVT monitors to measure if your specific silicon will meet timing goals, or program local Vdd levels to achieve a certain clock speed. It also can make sense to have multiple PVT monitors spread out across a single die in order to collect regional data. For example you could place a PVT monitor in each corner of a die, then one in the center in order to measure process variability. For multi-core SoCs you would place PVT monitors in each core, next to critical blocks.
Engineers at Moortec have designed PVT monitors across a wide range of process nodes starting at 40nm and extending through 7nm, so you don’t need to be a PVT expert to use their IP. You get to consult with their experts about which PVT monitors to use and where to place them on your specific chip design. To really get the most performance out of advanced FinFET nodes you should consider adding PVT monitors into your next design, even the battery-powered IoT designs benefit from the data gathered by PVT monitors in saving power consumption.
There’s an 11 page white paper available at Moortec for download after a brief sign-up process.
When I started dabbling in hardware again for fun using Arduinos about five years ago, it had been a long time since I had played with microprocessor chips. The epiphany for me was seeing how easy it was to load programs onto the onboard flash on something like an Atmel AVR using the SPI interface. My previous experience decades early brought up visions of bulky parallel interfaces with complicated programming units. The USB to SPI interface was essentially one chip and a few discretes. I also played with the SPI, in its most basic form, to drive programmable LED strips. Of course, SPI has mushroomed into a popular and essential interface for many embedded and SOC based systems. I was therefore pleased to see a webinar by Silvaco that delved into SPI and its many applications today.
The webinar, cleverly named SPI vs SPI, aired recently, but is now available for viewing on the Silvaco website. For those who are missing the SPI vs SPI reference, look up Mad Magazine, another one of my childhood favorites. With Silvaco’s acquisition of IP Extreme, they have become a significant player in the IP market. The webinar was hosted by Jim Bruister, Director of Digital Systems at Silvaco. MCU programming aside, the main application for SPI is the broader field of flash memory enabled devices. These cover a large range of consumer, IoT and networked products.
External flash memory for these products is enabled by SPI and helps solve many system and SOC level problems. Nonvolatile memory is needed for storing boot images and startup. However, onboard flash can be a problem due to cost or process compatibility. Rather than have embedded flash availability dictate SOC process selection, off-chip flash decouples the choices.
Even though SPI started out as a single data line serial interface, it has increased in speed and added bus width to boost performance. It has evolved from 1 bit at 1MHz to up to 8 bits running at 200MHz. At the same time is has preserved its simple and effective clocking and bus arbitration scheme. Jim pointed out during the presentation that with the newer SPI IP, a serial SPI bus running at 80MHz can exceed the throughput of a 32 bit parallel bus with a 90ns access time. At the same time SPI requires one 8 PDFN part, and the parallel interface would need 2 of the 64 BGA parts and the 64 traces that go with them.
Silvaco has IP for Quad and Octal SPI controllers. These interface with a large number of commercial flash memories and integrate inside SOC’s with ARM’s AMBA AHB and AXI interfaces. The story really gets interesting when Execute in Place (XIP) comes into the picture. XIP allows for external flash to be used as if it were system memory. This vastly expands system architecture choices. With XIP there is DMA support, which can be used to load encrypted images from external flash devices for increased security.
Jim’s talk articulates several scenarios where XIP, DMA and other advanced features of their high-performance SPI IP are used. Jim also discusses the software support available for system operation and debug. Silvaco offers a QSPI Boot Loader that copies external boot code stored on flash memory into internal SRAM and then re-boots. They also have a QSPI flash loader that is useful copying data to flash memory chips.
SPI is one of those long running success stories, from its origins in the 1990’s it has evolved and become newly important to an entire class of SOC based designs. With quad and octal designs running at high speeds, it has kept pace with data and throughput requirements. SPI enables data transfers with vastly fewer traces and with smaller and less expensive packages. SPI IP is an ideal example of how system level IP can help improve customers’ time to market, lower expenses and increase predictability. The webinar which is online now describes in more detail how a variety of solutions can be designed to incorporate flash memory by using Silvaco SPI IP.
Performance verification is among the most challenging of objectives in any SoC verification plan. It’s difficult to start effectively until quite late in the development cycle, at which point you don’t have a lot of time left to develop extensive performance-oriented testbenches. So many teams adapt functional tests to this purpose, typically a less than ideal way to truly stress performance. Even then they must comb through log and other files to extract latencies, bandwidths and other performance-related metrics, then compare these with targets.
Vaishnav Gorur, product marketing manager in the verification group at Synopsys, told me this has been a common concern he has heard from multiple verification teams and architects. This encouraged Synopsys to develop more automation around performance testing in their just-released VC VIP AutoPerformance and Verdi Performance Analyzer products. This tool automates the construction of traffic stimulus, orchestrating runtime traffic, visualizing and analyzing metrics, automating checking (did I meet targets) and diagnostic traceback (show me the packets that led to this problem).
From what I can see, there are four main components to a performance verification solution in this flow solution:
• VC AutoTestbench for building the testbench
• VIP for Arm® AMBA® protocol
• VC VIP AutoPerformance automates building the performance test from a test
• Extensive support within Verdi for performance-related metrics: latencies, bandwidths, counts, user metrics, all with user-definable thresholds, protocol-aware transaction tracking, linkages between violations and transactions, linkages to signals, memory activity/value tracking, cache operation/history tracking, you get the idea.
Synopsys has been making a big push to simplify and accelerate SoC verification. I recently introduced their webinar on automating building the SoC testbench, reducing time from a standing start to “lights-on” from days/weeks to hours. This webinar provides and overview on the solutions they are releasing targeting this objective.
You can register HERE for this webinar on February 21st at 10am PST
Abstract
Performance is a critical source of competitive advantage for modern SoCs, and performance targets need to be verified on top of functionality. SoCs can be configured in a multitude of ways with different IP and interconnect topologies, number of masters and slaves, bus widths, packet sizes, clock speeds, etc., and performance verification can quickly get overwhelming. Further, given SoC performance verification is often done towards the end of the project cycle, there is a pressing need for push-button performance verification, analysis and debug.
In this Synopsys webinar, we will outline an automated flow to perform end-to-end performance verification using Synopsys VC VIP AutoPerformance, Verdi Performance Analyzer and Verdi Protocol Analyzer. We will also include a demo of this flow using a real-world design and Synopsys VIP for Arm® AMBA® protocol.
Specifically, you will learn:
• How to quickly create a test profile for VC VIP AutoPerformance to auto-generate stimulus for performance testing
• How to easily preset thresholds for key metrics such as latency, bandwidth etc. to auto-detect performance bottlenecks
• How to analyze and seamlessly debug performance issues right down to the violating transaction
Vaishnav Gorur
Product Marketing Manager
Verification Group, Synopsys
Vaishnav Gorur is currently Staff Product Marketing Manager for Debug & SoC Verification Automation products in the Verification Group at Synopsys. He has over 12 years of experience in the semiconductor and EDA industry, with roles spanning IC Design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and an M.B.A. from University of California, Berkeley.
Satyapriya Acharya
Senior Manager – Applications Engineering
Verification Group, Synopsys
Satyapriya Acharya is a Senior AE Manager at Synopsys, where he manages the use of Synopsys Verification IP for ARM AMBA protocols with several key customers. He has been involved in the development, verification, and deployment of Synopsys Verification IP for the AMBA 3, AMBA 4 and AMBA 5 specifications. He has over 15 years of experience in design and verification.
According to the Economist, “The world’s most valuable resource is no longer oil, but data”. Is this the case?Data is the by-product ofmany aspects of recent technology dynamics and is becoming the currency of today’s digital economy. All categories in Gartner’s Top10 Strategic Technology Trends for 2018 (Figure 1) imply the generation, handling and processing of massive amount of data.
On May 25, 2018, the European Union (EU) plans to enact GDPR (General Data Protection Rules) aiming to streamline data privacy laws across Europe and to reshape the way organizations across the region approach data privacy/protection. The regulation biggest change is related to extending the jurisdiction of the GDPR (territorial scope applicability), as it will apply to all companies processing the personal data of data subjects residing in the EU, regardless of the company’s location.
Should we care about data security and protection? Does it have anything todo with design or EDA communities? There are several major reasons we should. Let’s take a look on three aspects:
First, the financial consequence to the business operation for failing to protect or properly handling sensitive data could be detrimental.Breaching GDPR can result in fines ranging from 2% for minor violations (e.g.disorderly recordkeeping) and up to4% of company worldwide revenue or €20 Million (whichever is greater). Such a hefty fine can be imposed for the most serious infringement, e.g. for not having sufficient customer consent to process data or violating the core of Privacy by Design concepts. Hence, many cloud providers such as Amazon (AWS) and Microsoft (Azure) were the first group to embrace steps to prepare for this rule enforcement and have established guidelines to tackle customer data and complying with GDPR. Similar data privacy enforcement is also done in the US by the Federal Trade Commission (FTC), although by means of varying list of imposed rules such as The 1974 Privacy Act, the Fair Credit Reporting Act (for financial domain), the Electronic Communications Privacy Act (consumer proprietary network info).
Second,data has gained increased importance due to the advent of Artificial Intelligence. Machine learning has facilitated more efficient engineering optimization and enhanced business analytics of traditional big data. Today’s cloud computing, network and machine learning have enabled the use of real time data, to augment historical data during active learning to produce optimal results. The entire solution supply-chain will take part in handling the data and share the burden of its safeguarding during and after each access. Within the context of the cloud providers, hardware companies will work with both upstream and downstream vendors to deliver a safe and complete solution. Table-1 highlights approaches used by key hardware companies to protect data.
What about the EDA world? Currently only a few EDA vendors have fully addressed ML implementation.ANSYS integrated ML, cloud access, data mapping and visualization facilities for its array of analysis products such that users could plug-in any further customization on topof its SeaScape stack platform (Figure 2). Solido (now part of Siemen) embedded ML into its characterization product but designated Solido Lab as facility to further collaborate with users. Both examples show approaches that accommodate users data proprietary nature. On the other hand, Cadence and Synopsys designplatforms have many underlying point tools such as synthesis,placement, routing, timing. Some of them had been augmented with ML flavors. However, boundaries introduced by these tools prompt unnecessary needs of frequent correlations, design margining and at times view-format transformations. While both vendors have made headways in aligning the delay computation engines (Cadence Gigaplace engine, Synopsys In-Design approach) non-unified database formats still limit data-flow and hence, optimal optimization with ML. It also has not addressed how to collaborate with users when badly needed data are also proprietary.
Third, sprouting digital ecosystems has blurred the boundary of private,corporate versus public domain data. For example, therapeutic medicine involves the potential use of private data (patient, doctor), public domain (Central Disease Control, county health) or corporate (hospital, insurance).Personal data gathered over time carry enormous value. EU estimates the value of European citizens’ personal data could grow to nearly €1 trillion annually by 2020. Some IT security techniques can be applied to protect the privacy of the data itself (i.e., anonymization– to remove personally identifiable infowhere it is not needed; pseudonymization– to replace personally identifiable material with artificial id; encryption– to encode messages so only those authorized can read it), but may not be sufficient.
In summary, the current digital revolution has produced massive data, crossing many evolving digital ecosystems and requiring all data shareholders to take a role in properly and safely handling them. This vary from revamping a more unified, seamless database platform to the need of collaborations in establishing a more solid data segregation (such as data IP) or standard access protocols.
In case you missed it, the FPGA Prototyping for SoCs webinar happened last week. I did the opening ceremonies which I will run through briefly here or you can go straight to the replay HERE.
FPGA prototyping is one of the fastest growing market segments we track on SemiWiki which brings us to the topic at hand: FPGA Prototyping for SoCs presented by S2C. Founded in San Jose, California, S2C has been successfully delivering rapid prototyping solutions since 2003.
Joining me today is Richard Chang, Vice President of Engineering at S2C. Richard has a Masters degree in Electrical engineering from the University at Buffalo and more than 20 years experience designing chips, including two US patents.
FPGA prototyping is a method to create a prototype of an SoC, ASIC, or System for the purpose of logic verification as well as early software development. FPGA prototyping today is used in all different types of applications such as consumer electronics, communications, networking, IOT, data center, autonomous driving, and artificial intelligence. FPGA prototyping can run at or close to real system speed in the ranges of tens of MHz and thus able to boot OS, run applications, and find deeply embedded bugs – significantly shortening the design validation time. FPGA prototypes are also affordable and therefore a large number of systems can be deployed to increase test coverage, shorten design validation time, and reduce the project risk.
With the advancement of software tools available around FPGA prototyping, FPGA prototypes today can be used throughout most design stages. Many commercial FPGA prototypes can link with the simulation environment through a transaction link such as AXI bus. This allows designers to start prototyping their idea on FPGAs early in the design cycle with part of their designs and test benches still in C/C++. FPGA prototypes are also ideal for block level and IP level verification.
It’s always a good practice to make sure each of your design blocks work before you put them together. In addition, many IP blocks today come from 3[SUP]rd[/SUP] party vendors or different design groups in your company. Prototyping with FPGAs first allows you to understand the behavior of these IP blocks at the system-level, easing system integration.
The next step is naturally integrating the entire system on FPGA prototypes. It will usually involve 2 things: multiple FPGAs and daughter cards. Most SoC designs will easily require 2, 4 or an even larger number of FPGAs to fit, and thus requires partitioning the designs as well as doing pin-multiplexing between the FPGAs as usually the interconnects between FPGAs after partitions are much larger than the available physical pins. This process can now be easily managed by partition tools such as Player Pro from S2C. You would also need daughter cards to hook up to real systems such as cameras, displays, memories or network connections. So, the ideal FPGA prototyping system needs to have good I/O expansion capability and a large library of daughter cards.
Finally, FPGA prototypes are used for early software development before the real silicon is available. Again, this is possible because FPGA prototypes run at or close to the real system speed and they are cost-efficient. Here’s a quick summary of FPGA prototyping benefits:
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I attend a lot of events on machine learning and write about it regularly. However, I learned some exciting new information about machine learning in a very surprising place recently. Every year for the last few years I have attended the HSPICE SIG dinner hosted by Synopsys in Santa Clara. This event starts with a vendor fair featuring companies that have useful interfaces and integrations with HSPICE. After a mixer in the vendor fair area, there is a dinner and several talks pertinent to the HSPICE user community.
Usually there are interesting talks by Synopsys customers on how they used the features of HSPICE in their flow to solve a vexing design problem. However, this time Synopsys threw us a curve ball. The main thrust of the talks this year focused on applications for machine learning in EDA, and specifically around HSPICE related issues. Naturally, EDA is not the first thing one thinks of when machine learning is mentioned. Yet, more and more, machine learning is being applied to difficult problems in electronics design.
It’s important to point out that machine learning is as good at numerical problems as it is at visual problems. During a panel portion of the dinner event, Synopsys Scientist Dr. Mayukh Bhattacharya clearly laid out the ideal scenario for using machine learning for a numerical problem. He cited the very broad definition of machine learning as “using a set of observations to uncover an underlying process”. There are three must haves: a pattern exists, we cannot pin it down mathematically, and we have data. It should be evident that these three conditions are met in a lot of SPICE related design problems.
As a good example was the talk that evening by Chintan Shah, VLSI Engineer of from Nvidia, where he has been working on clock methodology and timing. It’s interesting to think that Nvidia, a leader in machine learning technology, is applying machine learning to their own design methodology. In particular Chintan use machine learning to predict clock cell joule self-heating in their designs. Self-heating has become a much bigger issue with the advent of FinFET devices. FinFET self-heating can lead to device failure and it can also contribute to electro-migration issues.
Chintan’s problem is that there are huge numbers of clock cells that need to be simulated based on their parameters and their specific instantiation the design. For small numbers of such cells direct simulation is an adequate solution. Chintan reasoned that machine learning might help determine which cells are at risk and need detailed simulation. Nvidia has lots of historic data that can be used for training and validation of their deep learning model. They chose deep learning because single layer neural networks are not good at systems with nonlinearities.
Their conclusion was that the machine learning model had an average error of around 6.5%, with a mean square error of 0.05. This enabled them to filter out 99% of the cells with no simulation necessary. The remaining 1% represented a tractable simulation problem. This represents a 100X runtime improvement.
Of course, as is traditionally the case, there was a talk at the beginning by Synopsys’ Dr. Scott Wedge on HSPICE. He highlighted their latest developments and talked about their relentless progress on HSPICE performance. He aptly pointed out that if designs are growing at the rate predicted by Moore’s law, the tools used for design need to improve at a similar or better rate – something that Synopsys has been able to do with HSPICE, while reducing the memory footprint. One of the most interesting features Scott mentioned is their Python API. This opens the door for customers to conceive and implement advanced applications that utilize HSPICE as a core engine. As part of this there is support for a distributed computing environment.
Additionally, there was a talk by AMD on their use of HSPICE and MATLAB for global clock tree closure by Jason Ferrell. By the end of the evening it was clear that EDA will be increasingly affected by the growth of machine learning. And, it will happen in what will initially seem to be unexpected places. Machine learning is something that that everyone involved in EDA needs to pay attention to. Synopsys is providing a video of the entire dinner session available online. I’d suggest viewing the video to glean much more specific information on all the topics covered.
