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Open Silicon Delivers Silicon-Verified HBM2 IP-Subsystem on TSMC 16nm FF+

Open Silicon Delivers Silicon-Verified HBM2 IP-Subsystem on TSMC 16nm FF+
by Mitch Heins on 09-20-2017 at 12:00 pm
Categories: EDA, FinFET, Open-Silicon

Open Silicon hosted a webinar today focusing on their High Bandwidth Memory (HBM) IP-subsystem product offering. Their IP-subsystem is based on the HBM2 standard and includes blocks for the memory controller, PHY and high-speed I/Os, all targeted to TSMC 16nm FF+ process. The IP-subsystem supports the full HBM2 standard with two 128-bit wide channels that can deliver up to a 256 GBps bandwidth memory access.

Open Silicon’s IP-subsystem has been verified with TSMC silicon, including the use of TSMC’s 65nm-based CoWoS (chip-on-wafer-on-substrate) interposer and silicon-measured results correlated well with predicted simulations before manufacturing. This bodes well for designers that plan to use the IP as it means that Open Silicon’s simulation and modeling strategy is working well. Open Silicon also characterized their IP over the commercial range with different supply voltages and showed results at the webinar with the IP-subsystem successfully delivering data rates of 1.6Gbps/pin from -10[SUP]0[/SUP]C to +85[SUP]0[/SUP]C over a supply voltage range of 1.14V to 1.26V and 2.0Gbps/pin over the same temperature range with supply voltages between 1.28V and 1.42V.

The HBM2 IP-subsystem is currently offered in two options. The first option is to license the IP-subsystem from Open Silicon, in which case the licensee gets RTL for the memory controller, hard IP for the PHY and high-speed I/Os in the form of GDS, Verilog models for the main subsystem blocks and subsystem documentation.

The second option is to use Open Silicon’s 2.5D HBM2 ASIC SiP (system-in-package) IP, that includes Open Silicon’s help to integrate the IP-subsystem into their customer’s ASIC, and to design and integrate the customer’s ASIC and chosen HBM2 memory into a SiP using the TSMC CoWoS interposer.

Customers also have access to Open Silicon’s validation/evaluation platform to perform early testing of the memory interface against expected system-level memory access patterns. The validation platform uses a FPGA-based reference board with a prefabricated version of the HBM2 IP-subsystem combined with HBM2 memory. The rest of the customer’s ASIC system is synthesized into the on-board FPGA where the logic can be used in conjunction with HBM2 IP-subsystem and HBM memory.

A USB connection is available to connect the evaluation board to a workstation where Open Silicon runs a software suite known as “HEAT”. HEAT stands for Hardware Enabled Algorithm Testing and combines the hardware portions of the evaluation board with design-for-test (DFT) JTAG and BIST logic that can be used to access, control and monitor CSR registers in the HBM controller IP and Test Chip registers. The HEAT software GUI allows designers to build customized generators to drive data traffic to mimic real system usage and to then monitor system bandwidth, latency, and data mismatch results. The software is capable of using fixed, or variable patterns using pseudo random binary sequences (PRBS) as well as standard increment, decrement, walking zero, and walking one addressing patterns.

The current HBM2 IP sub-system supports up to 2Gbps/pin data rates with up to 8 channels (or 16 pseudo channels) delivering up to a total of 256 GBps total bandwidth. It’s compliant to the JEDEC HBM 2.2 specification and supports up to 5mm interposer trace lengths with the above stated performance. It also supports AXI and a native host interface.

Open Silicon also showed a road map of their next development including a port of their HBM2 IP-subsystem to TSMC’s 7nm CMOS process with the intent to have it silicon validated by the middle of 2018. This version will support a multi-port version of the AXI interface with different schemes for arbitration and quality of service (QoS) levels and programmability of different address mapping modes. The 7nm technology will enable greater than 300 GBps of total bandwidth while running data rates of up to 2.4Gbps/pin. This time line matches up with when major HBM memory providers will be delivering products capable of supporting the 2.4Gbps data rates. Additionally, Open Silicon already has eyes on the evolving HBM3 standard and is targeting development of an IP-subsystem to support that with a 7nm TSMC process. They are expecting HBM3 work to begin sometime in 2019.

So, to summarize, Open Silicon presented on their silicon proven HBM2 IP-subsystem based on TSMC 16nm FF+ and showed good modeling and simulation predictability. They also showed some interesting details of their design along with their FPGA-based evaluation and validation board and test methodology. And, they followed up with some real characterization data from their runs with TSMC showing impressive data rates of 1.6Gbps/pin to 2Gbps/pin using 5mm interposer trace length.

All in all, a very impressive set of IP that can be used in a wide variety of markets where high bandwidth memories are key to success. System designers building high-performance computing and networking solutions for data centers, networking, augmented and virtual reality, neural networks, artificial intelligence and cloud computing can all benefit from Open Silicon’s HBM2 IP-subsystem that not only completes their solutions but lowers their risk and shortens their time to market.

Nice job Open Silicon! You can see the replay HERE.

See also: Open Silicon Solutions

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Yield Analysis is a Critical Driver for Profitability

Yield Analysis is a Critical Driver for Profitability
by Daniel Nenni on 09-20-2017 at 7:00 am
Categories: Semiconductor Services, Semitracks

One of the most important aspects of any manufacturing effort is the yield of the process. Today, the investment in facilities, equipment and materials is so high that consistently high yields are vital to the profitability of the semiconductor manufacturer. Furthermore, the engineers must get to that consistent high yield as quickly as possible to avoid product delays, A yield ramp delay of 3-6 months is extremely costly, and a 6+ month delay could be catastrophic (bad press, lost business, etc.). An example of this (although not necessarily a chip problem) is the delay that Apple is experiencing with the iPhone X. The later than expected introduction will impact holiday sales for them, resulting in a significant revenue hit. In fact, the stock price fluctuated significantly when the ship date was announced earlier this month.

Identifying and eliminating the source of yield loss is one of the most challenging activities a product or fab engineer will face in his/her job. Yield analysis is quite often high-pressure work, requiring long days and quick decisions based on an incomplete understanding of the situation. Solving a yield issue requires complex pattern recognition skills using limited amounts of data. While fab tools and test equipment generate terabytes of data, knowing what to look for in that mountain of data is a difficult task. Typically, one needs to start with a big picture understanding, by identifying what is failing (failure mode of the IC), and how the failure manifests itself in the process (spatial dependencies, lot dependencies, equipment dependencies, etc.).

The engineer must then formulate hypotheses that fit the “what” and “how”. He or she would then look through the data at hand to try and confirm or deny each hypothesis. If there is insufficient data to do this, one may have to gather additional data. Finally, if there is no data on hand that can conclusively prove an hypotheses, then the engineer would typically submit a sample of ICs for failure analysis to help provide greater understanding of the problem. Once the engineering team identifies the source of the problem, they will develop a fix and implement the fix on a set of control material. If the fix is successful, they can roll it out to the entire production line. Yield analysis is sort of like learning to ride a bike – you get better at yield analysis the more you do it. However, there are some important concepts relating to data visualization, data analysis, techniques, and the overall process for yield analysis. Semitracks has an online course that covers these concepts in more detail (they provide the course as an in-house training course as well).

If you are a product engineer that has the responsibility for maintaining the yield of an IC, if you are a fab engineer who must gather the data for yield work and fix fab-related problems, or if you are a foundry interface engineer who needs to understand yield analysis work in order to make an informed decision about what to do with your products, then going through this type of training is a must. Successful yield analysis work can save your organization millions of dollars. The stakes are simply too high to ignore this.

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Improved Memory Design, Characterization and Verification

Improved Memory Design, Characterization and Verification
by Daniel Payne on 09-19-2017 at 12:00 pm
Categories: Cadence, EDA, FinFET

My IC design career started out with DRAM design, characterization and verification back in the 1970’s, so I vividly recall how much SPICE circuit simulation was involved, and how little automation we had back in the day, so we tended to cobble together our own scripts to help automate the process a bit. With each new process node offered the amount of SPICE circuit simulation for design and characterization has just increased caused by the number of PVT corners required, especially for IC designers doing memory IP. According to the SIA/ITRS many modern SoC designs can use up to 69% of their die area on memory IP blocks. At the 16nm process node we can expect to see some 196 PVT corners.

So today you still have a couple of choices for automating memory design tasks, either write your own automation scripts, or try something more integrated from an EDA vendor that knows the industry. The folks at Cadence scheduled a phone discussion with me earlier in September to provide an update on something new they had just finished working on that addresses this automation challenge. Cadence is calling this new tool flow Legato, and it’s focused on helping memory designers with three areas: Cell Design, Array and Compiler Verification, and Memory Characterization.

During the bit cell design phase circuit designers can perform variation analysis using Monte Carlo runs inside of the familiar Virtuoso environment, and the Spectre APSsimulator produces fast results using a parallel approach. Verifying instances of memory from an array compiler are best simulated with Spectre XPSbecause it’s a FastSPICE simulator with partitioning. Finally, to create all of the memory models (timing, power, signal integrity, current source) the Liberate tool is invoked and it simulates with Spectre XPS.

With Legato they’ve been able to speed up run times by 2X by using a variety of new techniques like RC reduction of parasitics on inactive bit and word lines:


The process for simulating multiple PVT corners has been optimized by minimizing the partitioning steps and number of tables used by the FastSPICE circuit simulator, along with fewer DC operating points:

So Cadence has taken multiple point tools then re-engineered how they work in conjunction to optimize the overall run-time required during Memory design. The real proof is in what actual customers are doing with Legato, so from Yoshifurmi Okamoto at Socionext I learned:“Through our use of the Cadence Legato Memory Solution, we have experienced a 2X productivity gain when compared with our point solution and successfully taped out 12nm memory macro designs for our System-on-Chip solutions, and we can confirm good correlation between simulation result and silicon measurement.”


At Socionext they did a comparison of SRAM characterization for a 512×32 array on an 10LPE process node using point tools, then using Legato:

  • 720,988 seconds, point tool
  • 262,923 seconds, Legato
  • 2.6X speedup with Legato

Summary
For memory IP designers using Cadence tools like Virtuoso, Spectre and Liberate, you now have something new in the EDA toolbox with Legato that will provide a 2X speed improvement at the same accuracy as before. This new, optimized flow is ready to go, so why not give it a try on your next project. Cadence acquired Altos Design Automation back in 2011 and over the past six years have continued to invest in this characterization tool, so they certainly understand the needs of this market.

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Partitioning for Prototypes

Partitioning for Prototypes
by Bernard Murphy on 09-19-2017 at 7:00 am
Categories: Aldec, EDA, FPGA, Prototyping

I earlier wrote a piece to make you aware of a webinar to be hosted by Aldec on some of their capabilities for partitioning large designs for prototyping. That webinar has now been broadcast and I have provided a link to the recorded version at the end of this piece. The webinar gets into the details of how exactly you would use the software to optimally partition; here I’ll revisit why this is important, adding a realization for me on the pros and cons of automatic versus guided partitioning.


Prototyping a hardware design on a FPGA platform is especially important for software development, debug and regression while the ultimate ASIC hardware is still in development or even in the early stage when your bidding on an RFP or hoping to persuade VCs/angels that you have an investment-worthy idea. They’re also the best way to test in-system behavior with external interfaces like video streams, storage interfaces and a wealth of communications options.

But you can’t typically fit an SoC into even the largest FPGA; Aldec cited as an example a multi-core graphics processor requiring 15 Xilinx UltraScale devices to fully map the design. This means you need to figure out how to split your design across those devices. The temptation may to build your own board or set of boards, which may initially seem simpler but you’ll quickly find that splitting the design effectively and balancing delays at those splits can be very non-trivial.

Wherever you spilt, signals have to cross through board traces and sometimes even between boards. Those signals have to travel through device pins, the board traces and possibly backplane connections so they’re going to switch more slowly than signals within a device. What appeared to be reasonably matched delays in your RTL design can quickly become very unmatched. And in ways that can change wildly with your split strategy; on this experiment, you have certain critical paths you need to manage, on the next experiment, those paths need no special help but a new set of paths are suddenly a big problem.

Clocks can be even more challenging; clock signals crossing between devices may introduce significant clock skew you didn’t anticipate. For both signal and clock timing problems, within a single FPGA device, vendor design tools will help you close timing but closing timing across the whole design is going to be your problem.

You also have to deal with IO resource limits on FPGAs. Aside from timing, you can’t arbitrarily divide up your design because in most cases that will require you support more IO signals on a device than there are signal pins. Handling this requires some clever logic to bundle/unbundle signals to meet pin limitations; a lot more work if you’re trying to hand-craft your own mapping.

Making all of this work on your own custom-crafted FPGA boards is not for the faint of heart. A much simpler solution is to use the Aldec HES prototyping systems (supporting up to 630M gates split across 4 boards, each with 6 FPGAs), together with HES-DVM PROTO to simplify partitioning and setup. They illustrate this through a NoC-based design hosting a CPU, RAM and GPIO and UART interfaces, mapping onto one of their HES7XV12000BP boards.

In the demo they highlight some of HES-DVM Proto capabilities: clock conversion, interconnect analysis, “Try Move” options, experimenting with different inter-chip connectors and others. This is an interactive process so you might wonder why you can’t just push a “Go” button, sit back and wait for it all to be done automatically. That is supported in some tools but even there, if you want to get to decent performance levels (>5MHz), you have to get involved. I guess Aldec just skipped the easy but slow option and went right for hands-on and fast.

You can watch the Webinar HERE.

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What does the Lattice rejection mean for chip M&A?

What does the Lattice rejection mean for chip M&A?
by Robert Maire on 09-18-2017 at 12:00 pm
Categories: Semiconductor Advisors, Semiconductor Services

Although the rejection of the Lattice deal was expected, it none the less has an impact on a number of dynamics in the chip industry and further M&A and consolidation. Freezing out China removes a “catalyst” in the market which help bid up values and add fear to both potential targets or those left out. Cross border deals are obviously more difficult to get done and even small deals with China will likely be put under a microscope now.

The Xcerra deal is likely very safe given the size and lack of critical technology. Much like the Mattson deal before it, China will only be allowed to acquire second or third tier small chip companies with no unique technology or critical market position.

Does this slow down China’s chip ambitions?
Does this slow down M&A and consolidation further?
Does this negatively impact future sales of equipment to China?

Building a Wall…
With the final rejection of Lattice which was well anticipated the US has successfully built a virtual wall specifically aimed at keeping China out of US high tech. Using CFIUS as the building blocks it would appear that China will likely be shut out of further significant deals. Aixtron was a pre cursor and certainly signaled the US resolve as CFIUS blocked a Chinese acquisition of a German company (albeit one with US technology assets).

We did not see similar behavior when Japan, Taiwan and Korea got into the chip business as they were obviously viewed as friendly competitors.

Small deals will get through the ‘Lattice” wall…
Much as small fish can get through the “lattice” structure of a net designed to catch bigger fish, so too will small buys get through the CFIUS review. Mattson got through as it was a small third tier company with no unique technology. We think Xcerra is a safe bet as it is dwarfed by Teradyne and Advantest and remains a distant third in a segment of the market not viewed as a driver of Moore’s law.

The problem here is that small fish don’t get China to where it wants to be very quickly. These size and types of acquisition don’t get China either technology or market share. China will never catch up by buying second and third tier companies….but obviously thats the whole point….let China buy the leftovers that no respectable US company would ever buy.

Roadblocks and detours for China’s grand semiconductor plan…
The industry is obviously concerned about China’s ambitions and $100B checkbook to turn them into reality. The number of fab projects in China sounds like it almost exceeds the rest of the world put together. We have obviously been very dubious as to how many are real and how many are wishful hyperbole.
We have thought that you could easily halve the number of Chinese projects that are announced but will never get built. Of those that get built, how many will be impactful?

The lesson of SMIC…
SMIC had sky high aspirations of being a TSMC beater based in China. Many Taiwanese engineers left the island to go work for SMIC, bringing much talent with them. However, it turned out that SMIC never got very far. The US government clamped down on tools that could be shipped to China and the talent never fully coalesced into a viable team that could keep up. Today SMIC is a respectable foundry but not the world beater it wanted to be. Not having both the technology assets as well as the human assets kept it from joining the country club of Intel, Samsung, TSMC and Toshiba as chip leaders in their respective countries. Having a big checkbook isn’t the only thing that gets you membership in that exclusive club…..

Could this dampen China’s spending on US tools and technology…
We don’t think that any US based tool company had factored all that much China spend into their future plans so its unlikely this will cause any significant disappointments. We could see some spending shift to local suppliers like AMEC in China or SEMES in Korea or maybe even Tel & Hitachi in Japan , but just using those companies exclusively will never get you to the bleeding edge. China will still be stuck buying from US tool companies just as SMIC is

Not likely to be a repeat of China’s smothering of Solar & LEDs…
In a recent conversation with an industry executive, they noted that on a technology scale, building solar panels was likely a “one” and building 10NM chips was a “ten”, with LEDs a “two” and OLED probably about an “eight”. We agree. The economics reflect this as you can start making solar panels or LEDs with a $25M to $50M factory but we all know the astronomical cost of a chip factory. OLEDs aren’t that easy either as Samsung has “cracked the code” but LGs OLEDs are far behind as Apple found out as it was forced to cough up beaucoup dollars for single source supply on high quality OLEDs for the Iphone X coming from arch enemy Samsung.

In short, although rightly concerned we aren’t scared about China’s entry into the Semi market or even the OLED market as a repeat of the solar/LED movie. While the US was forced out of Solar and companies like Veeco were crippled in LED we don’t see the same threat in Chips. AMEC in China has made great strides in MOCVD against Veeco but has nothing close to Lam’s high aspect ratio etch tool for 3D NAND (not yet anyway…)

No China =Less pressure = lower prices = no rush…
If China can no longer reasonably expect to bid on US Chip assets then the ability of this irrational buyer to overpay and drive up valuations has been removed. Lattice is a clear example as China was going to buy it for almost double of its market value rather than a more normal typical M&A premium. It also removes the fear factor and pressure of US companies to merge or run into the arms of a white knight to escape the clutches of China. It also obviously means there is less rush and imperative to get deals done as this overhanging threat is gone.

The Toshiba Soap Opera…
The plot thickens as Apple and Dell are two new characters added to a multifaceted love triangle Italian opera. I have long ago lost track of who is on who’s side and who loves whom, who is suing who etc;. All I pay attention to is that the bid continues to go up to the current $19B and counting. Its likely far from over and is just starting to get interesting.

We wonder what premium is being paid for Toshiba’s chip business above the depreciated value of the fabs and equipment in them. Our math says its a very high premium. You could probably build three large state of the art NAND fabs for the $19B being offered and at last count, Toshiba does not have three bleeding edge big NAND fabs.

This goes back to the point of the value of the technology/IP/know how that China wants and will have a hard time getting.

We also finding it amazing that a few short years ago you probably couldn’t give away assets in the memory space. Does anyone remember Inotera or Elpedia? Micron has obviously done a good job of picking up assets on the cheap at the bottom of a cycle while the current Toshiba auction appears to be going on at the top of the cycle (are these buyers really as smart as they think they are???).

Investors in Abu Dhabi must be cheering from the sidelines as their stock in Global Foundries is obviously worth a whole lot more.

We do think Toshiba is more of an aberration rather than an example of current M&A demand. First off, its a shotgun sale as Toshiba is being forced to liquidate and second the memory market is obviously in a frenzy.

M&A getting smaller…
Its clear that in the chip equipment space, smaller is better. After AMAT/TEL and KLAM both getting shot down everyone has been gun shy. We sense that more companies are now talking about M&A in the space but the pickings are very slim. You can’t do a large deal without the blessings of the customers (think Intel) and small deals don’t move the needle enough. The industry unfortunately is like a barbell with a bunch of very big companies and a bunch of very small companies and not a lot of potential targets of the right size. Varian was one of the last good deals on the equipment side and MKS acquiring Newport was one of the last good deals on the supplier side.

The industry may be stuck doing a lot of smaller deals based on strategic technology rather than financials. An example of this would be the recent purchase of Coventor by Lam which got $25M of revenues which isn’t even a rounding error to Lam but did get some very key technology that will likely generate many times that revenue in helping its core etch and dep businesses sell more product and improve process. ASML clearly overpaid to get Hermes , but Hermes is clearly very strategically important to the larger EUV story of ASML.

The stocks…
Given slowing M&A and China being barred from the market we think there is little reason to pay an M&A premium for a potential target company. Valuations are already strong and we likely won’t see huge premiums in M&A. Veeco buying UTEK was an example of this phenomenon as the premium was low because UTEK was already fully valued given its weak performance.

Most all the low hanging fruit is gone and good deals will be harder to get past government and customer scrutiny. Record stock prices are further deterrents. While we do expect M&A to continue, we think the pace will remain low along with premiums and would not place stock bets based on expectations of activity.

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ATopTech is Back!

ATopTech is Back!
by Daniel Nenni on 09-18-2017 at 7:00 am
Categories: EDA

One of the biggest surprises at the TSMC OIP Forum last week was the reappearance of bankrupt EDA vendor ATopTech. I spoke with former ATopTech CEO and now Avatar IS President Jue-Hsien Chern at OIP. As a survivor of several EDA legal battles myself, I understand what ATopTech went through and I am thoroughly impressed that they had the courage and fortitude to weather a four year legal assault and reemerge under a different name with new technology. What doesn’t kill you makes you stronger, right?

About Avatar Integrated Systems
Avatar Integrated Systems is a leading software company in the Electronic Design Automation (EDA) industry focused on Physical Design Implementation. The company’s products enable integrated circuit (IC) designers to create semiconductor chips which enable today’s electronic devices, such as smartphones, computers, internet equipment, IoT wearables, etc.

Avatar’s product line includes Aprisa, a netlist-to-GDS full-function block-level physical implementation tool, and Apogee, a complete top-level proto-typing, floor-planning and chip assembly tool. The patented technologies were developed specifically to deal with the design challenges at 28nm and below. Avatar’s products have been certified by the industry’s top semiconductor foundries for designs at advanced process nodes, such as 28nm, 20nm, 16nm, 14nm, 10nm and 7nm. As a result, our patented technology has been adopted by world leading IC design companies with numerous successful tape-outs.

It really is an interesting story that plays out on the Law360 website. A Hong Kong billionaire businessman (Jingyuan Han) is behind the $35M funding which adds a bit of intrigue. Synopsys, who won a $30M patent infringement case against AtopTech, went through this bankruptcy sale kicking and screaming but in the end accepted the terms. Synopsys offered $2M for assets only, Silicon Valley VC firm Draper offered $8M with ridiculous terms, so the winner is Avatar and ultimately ATopTech employees and customers.

In addition to funding and fortitude, two other things made this transformation possible:

Leading edge products
The Avatar Aprisa and Apogee products are certified by foundries (TSMC, Samsung, GLOBALFOUNDRIES and UMC) down to 7nm.

Strong leadership
Jue-Hsien Chern, Ph.D President
Jue-Hsien Chern brings over twenty years of experience in high technology companies to Avatar. Prior to joining, he was vice president and general manager of the DSM division at Mentor Graphics for nine years. He was at Texas Instruments for 10 years, holding positions as SMTS and branch manager within the Semiconductor Process and Design Center. Jue-Hsien has also served as head of the DSM business unit at Avant! and vice president, engineering, and CTO at Technology Marketing Associates.

Zongchang Yu, Ph.D. Chief Executive Officer
Zongchang brings 20 years of experience in computational software development and organization management to Avatar in 2017. Prior to Avatar, He co-founded XTAL in January 2014. Zongchang was also the Manager of Applications Engineering at D2S, Inc. Previous to that, Zongchang was the Manager of Product Engineering at Brion (acquired by ASML in 2007). Zongchang was also Senior Product Research Engineer and Senior Development Engineer at KLA-Tencor. Zongchang started his career as Design Engineer at ULVAC in Japan after attaining his PhD from Harbin Institute of Technology.

Ping San Tzeng, Ph.D Chief Technical Officer
Dr. Tzeng brings over 18 years of EDA experience with him to Avatar. Dr. Tzeng was one of the original developers of ArcCellXO, developed at ArcSys in 1992. He was the key architect in the evolution of ArcCell to the industry known place and route systems Aquarius, Apollo and Astro. Dr. Tzeng continued to work and enhance his routing technology at ArcSys, Avant! and Synopsys (ArcSys formed Avant!, Avant! was aquired by Synsopsy in 2002). He holds the prestigious honor of Avant! Fellow and Synopsys Fellow. Prior to ArcSys, he held positions at Cadence Design and Quickturn Design Systems. He holds a B.S. in Electrical Engineering from National Taiwan University and a Ph.D. computer science from U.C., Berkeley.

I would also not discount the Chinese connection and the reported 1,300 fabless companies in China, absolutely.

There is a lot more to this story of course. If you have questions hit me up in the comments section.

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Burning Man 2017 – My vacation is your worst nightmare

Burning Man 2017 – My vacation is your worst nightmare
by Tom Simon on 09-17-2017 at 5:00 pm
Categories: General

I often use this space to report on industry events I have attended and what I have learned at them. So, this article will be a slight, but not complete, departure from this. I am reporting on my experiences at Burning Man this year. For the unacquainted, Burning Man is a temporary city of around 70,000 people in a remote desert-like dry lake bed in Northern Nevada. The Black Rock Desert is a harsh environment with an arid climate where temperatures range from 32 to 104 during the event, and sometimes there are heavy winds and ubiquitous alkaline dust (not sand). The event is a week long and attendees need to pack in and pack out everything they need to survive, and hopefully luxuriate, in this environment. There are no shops, vendors, food stands, trash cans, nor water provided there.

Why, you might ask, do people come here? Back in my first years, starting in 2004, it was a place to get away from your routine, unplug and learn how people can create community and build participatory art. The event is filled with art and expression. There are large projects that are funded through grants, and small creations and activities undertaken by the participants. Yes, there are large parties, naked people and tons of noise. There is also a camp of sober AA members, sunrise yoga, a marathon run, and massive gifting of food, drink and whatever else people feel like contributing. I am sure you also have heard that many high tech luminaries attend, as well as the likes of Paris Hilton.

There are ten principles that attendees should follow to maintain the integrity of the event. More on the ten principles can be found on the Burning Man web site. Back in 2004 most people camped in tents, along with some in RV’s. The harshness kept out ‘weekenders’ and the music festival crowd. There is no “main stage”. The event is created by the attendees, not the organizers – who for their part primarily provide porta-potties and overall event organization.

However, these days there are many RV’s and so called “plug and play” camps, where people look to pay others to prepare things for their experience and often do not contribute to the event itself as was traditionally done. Despite the growth of these kinds of attendees, the event still carries with it a unique culture of openness and interaction.

Most interesting is how technology has become a larger part of the event. In the large open areas of the desert site there are big art projects. To help people cover the thousands of feet of flat desert, many people build and bring art cars which they then use to carry anyone who wants a ride. These art cars look nothing like cars. There have been dragons, sailing ships, yachts, flaming ducks, submarines, desert islands, an octopus made from scrap metal that shoots flame from its tentacles, a giant angler fish called Disco Fish, and so on.

Let’s talk about Disco Fish. It is built on a Chevy van and a trailer that are festooned with translucent ‘scales’ with thousands of addressable LED’s. It has a propane jet torch on top and a huge disco ball where a real angler fish would have its luminescent lure. The dorsal and tail fins are outlined with LED’s as well. The on-board computerized light controllers can make the LED’s shimmer and flash in a wide range of coordinated patterns and textures.

From a distance, it is easy to spot because of the amazing lighting. Inside it has Lidar and GPS to help it navigate. In fact, it can operate as an autonomous vehicle and is safe to operate even in this difficult environment. If it comes across a pedestrian or someone sitting on the ground enjoying the vivid surroundings, it will come to a complete stop – though it never travels more than 5 or 10 MPH. It is even possible to monitor its location using a web service connected to its navigation system. The irony is that the limited cell/internet service in this remote corner of Nevada is swamped and wiped out by the 70,000 people present. So probably only people who are not at Burning Man could have seen exactly where Disco Fish was at any time during the week.

We camped next to a group who brought the Island Art car. They spent days getting their new engine to work. The engine ECU had locked up and the fix required one person from this camp to make a 10 hour round trip drive to Reno get a replacement. However, they had it up and running mid-week. So in the evenings we enjoyed riding a desert island with multi colored LED palm trees across an arid desert in Nevada.

In my own set up, I have gone from buying ice (that and coffee are the only things for sale there) to keep my food cold, to building a 400 watt solar system to power a mini-fridge and lighting for our camp. Also, I built a number of uProcessor based circuits to add LED lighting accents to our bikes, camp and even back packs, which you always need to have with water for hydration and goggles and a dust mask for the frequent dust storms.

This year there was an impressive art project that looked almost exactly like a large oak tree, where every leaf contained 8 or so addressable LED’s. The effect of light patterns moving across this full size tree at night was mesmerizing. There was usually a crowd of hundreds quietly standing and sitting around it through the warms nights we had this year.

There was also an old favorite zoetrope created by Peter Hudson that features a full size skeleton ‘rowing across the river Styx’. This piece is titled Charon, after the mythological being that carried the dead to afterlife. At night, the vertical ring of individual skeletons would synchronize with a strobe light to create the eerie effect of a living moving skeleton. Of course, the electronics are computer controlled. To make the strobe sync with the rotating wheel, viewers have to interact with the art by pulling huge ropes to make the 25 foot wheel of wood move rapidly enough.

While technology is blunting the difficulty of attending Burning Man, making it easier for ‘spectators’ who are not participants to attend, it is also enhancing the sophistication of the art and structures that are built for the week.

At the end of the event all 70,000 people and their temporary homes are packed up and taken home. There is a leave no trace ethic that requires the desert be left pristine at the end of the week. While, not perfect, the people who go do an amazing job of removing debris as small as a nut shell, cigarette butt, dropped zip tie, food, carpet scraps, etc. There are no trash cans, so everyone is aware of their responsibility to pick up and carry away. In fact, returning to the Bay Area was difficult in part because you see how much trash there is along the freeway once you get back to the Bay Area.

It seriously takes a week or more to recover from the experience, and I often do not have the energy to even contemplate returning until sometime months later. But Burning Man has always affirmed my faith in the creativity and potential of people to come together to build something bigger and better than they can individually. It is also a somber reminder that all things are ephemeral. The city is built and disassembled each year. For now I’m cleaning and packing away my very dusty and well used gear and clothes. We’ll wait to talk about going next year until around April or March. Until then, I’ll enjoy reflecting on what has been an amazing and challenging adventure.

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Webinar: Signoff for Thermal, Reliability and More in Advanced FinFET designs

Webinar: Signoff for Thermal, Reliability and More in Advanced FinFET designs
by Bernard Murphy on 09-17-2017 at 7:00 am
Categories: Ansys, Inc., Automotive, EDA, FinFET, Mobile

In automotive applications, advanced FinFET processes are great for high levels of integration and low power. But they also present some new challenges in reliability signoff. Ansys will be hosting a webinar to highlight the challenges faced by engineers trying to ensure thermal, electromigration (EM) and electrostatic discharge (ESD) robustness in advanced SoCs and to show how ANSYS tools and flows can help meet these goals.


REGISTER HERE for the Webinar September 27[SUP]th[/SUP] at 8am PDT

This is of more than passing importance in automotive applications. Cars and other vehicles are expected to have 15+ year lifetimes, far longer than the consumer electronics we normally think of as benchmarks. These systems are also held to much higher expectations, often in much more challenging environments, for thermal problems, electromigration and ESD. And these problems are only going to get worse as autonomy support increases in our cars and safety functions are expected to be 100% dependable through at least the warranty period.

Reliability is also a big concern in mobile and high-performance computing, though in different ways. The average lifetime of mobile devices is likely to grow quite significantly, party because the thrill of constantly updating our phones/pads/watches is wearing off and partly because there is no such thrill in industrial applications. Businesses will be motivated to look for more reliable alternatives if scanning and other devices start to go bad after 2 years.

In high-performance computing, thermal and reliability are both significant cost concerns, directly affecting to the costs of cooling in data centers and repair/replacement and downtime which can directly affect committed throughput for cloud providers.

Demonstrating the level of importance of this area, TSMC and ANSYS recently announced a new Automotive Reliability Solution Guide. ANSYS and TSMC collaborated on this first-of-its-kind guide, incorporating various reliability capabilities in one place to support customers’ IP, chip and package development for automotive applications in TSMC’s 16-nanometer FinFET Compact Technology (16FFC) process and Automotive Design Enablement Platform (ADEP).

Join ANSYS to learn how ANSYS solutions offer comprehensive chip-package-system thermal analysis, as well as thermal aware EM sign-off, for finFET designs. Discover how ANSYS PathFinder can help ensure ESD integrity from the IO/IP level to the SoC for human body model (HBM) and charged device model (CDM) analysis. This session will also cover best practices for ESD model hand-off from IP to SoC for chip ESD validation, and generating SoC-level ESD models for system-level ESD simulations.

REGISTER HERE

Founded in 1970, ANSYS employs nearly 3,000 professionals, many of whom are expert M.S. and Ph.D.-level engineers in finite element analysis, computational fluid dynamics, electronics, semiconductors, embedded software and design optimization. Our exceptional staff is passionate about pushing the limits of world-class simulation technology so our customers can turn their design concepts into successful, innovative products faster and at lower cost. As a measure of our success in attaining these goals, ANSYS has been recognized as one of the world’s most innovative companies by prestigious publications such as Bloomberg Businessweek and FORTUNE magazines.

For more information, view the ANSYS corporate brochure.

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High-Level Synthesis for Automotive SoCs

High-Level Synthesis for Automotive SoCs
by Mitch Heins on 09-15-2017 at 7:00 am
Categories: Automotive, EDA, Siemens EDA

Some of the world’s most complex Systems-on-Chip (SoCs) are being developed for automotive applications. These SoCs have heterogeneous architectures with a variety of processors and accelerators that do real-time image processing for assisted and autonomous driving applications. The Bosch Visiontec team, in Sophia Antipolis, France develops these state-of-the-art SoCs and they recently co-authored a white paper with Mentor, a Siemens Business, that details how they have leveraged high-level synthesis to design these complex ICs.

Traditional SoC design flows start with designers modeling at the system level in MATLAB or languages like System-C or C++. Once the functional trade-offs have been made, designers implement the design architectures using Register Transfer Language (RTL) code which is used for logic synthesis, placement and routing. In the case of autonomous vehicle applications, the algorithms to do image recognition are mathematically intense and the Bosch team found themselves facing very aggressive design schedules. With autonomous and assisted vehicles being such a new area, Bosch also found that their design specifications were continually changing. With that in mind, the team quickly decided that hand-coding RTL was not going to be a viable option. They needed a way to respond in a nimble fashion to design specification changes while being able to rapidly iterate their RTL design.

Bosh partnered with Mentor to implement a design flow that used Mentor’s Catapult High Level Synthesis (HLS) and PowerPro platforms. The team chose to implement their designs using a synthesis friendly subset of ANSI C++ and to then use the Catapult flow to synthesize and optimize their design blocks. Using C++ allowed the Bosch team to stay at a higher level of abstraction while also using parameterized functions to avoid writing the same functions multiple times for different designs.

Catapult’s ability to rapidly synthesize RTL code greatly reduced the time to iterate design blocks as micro-architecture constraints changed. Instead of re-coding RTL by hand, the design team was able to simply change the synthesis constraints and have Catapult re-synthesize new RTL code. A good example of this was when one spec change caused the throughput requirement to go from 5 to 20 clock cycles. In this case, Catapult took advantage of the relaxed throughput requirement and re-optimized the RTL to make use of more resource sharing, resulting in an overall area reduction for the design.

A slick feature of the Catapult-HLS flow is that Catapult can automatically generate the infrastructure for verifying the functionality of the HLS-generated RTL against the original C++ source code. When doing this, Catapult re-uses the original C++ simulation test benches. Mentor calls this their SCVerify flow. When Catapult compiles the C++ design files, it generates scripts that drive the simulator environment for debugging and verifying the design. This saves the team a considerable amount of work and time as they don’t have to manually write a RTL test bench each time the design specifications change.

Another key advantage to using Catapult came about after Bosch synthesized their generated RTL to gate logic. A design-for-test (DFT) tool was used to analyze the resulting gate logic and it was found that their design had a 95% test coverage score. For safety sensitive automotive applications, this needs to be 99% or higher. Upon seeing their score, the design team went back to the RTL level and made use of Catapult’s LOGIC_OPT directives and found they could further increase the DFT coverage to 97%. Next the design team made use of Catapult’s Optimized Reusable Entities (CCOREs) to increase the clock overhead which allowed them to add more test points, enabling them to meet their 99% goal. These changes were later backed out as there was a specification change that increased the clock overhead but the initial worked enabled them to prove that they could in fact meet the testability requirements as desired.

In addition to HLS, Catapult also gave the Bosch team the ability to do “property checking” on their design. This included checks for uninitialized memory reads (UMRs), divide-by-zero (DBZs), array bound read errors (ABRs) array bound write errors (ABWs), incomplete case statements (CAS) and illegal shift errors (ISEs). Catapult also formally proves designer-provided custom assertions and cover points that are used to complement dynamic simulations and to provide further verification of the C++ models. In Bosch’s case, Captapult’s property checking capabilities enabled them to find and fix hundreds of uninitialized memory read problems that were not possible to detect in their C simulations.

Lastly, the Bosch team also made use of Catapult’s low-power flow that integrates high-level synthesis with Mentor’s PowerPro technology. With this flow, Catapult runs supplementary optimizations to control power consumption by using deep sequential analysis of the RTL for power estimation and optimization. PowerPro uses stability and observability clock gating to generate a power-optimized circuit with minimal user guidance. To do this it uses the same test bench as used in the SCVerify flow to capture switching activities. Additionally, Catapult has built-in formal verification technology that is used to ensure that the power-optimized RTL remains equivalent to the original design intent. By using this flow, Bosch was able to reduce their power consumption by 19% on one chip and 33% on a second chip.

In summary, the Bosch team found that by using the Catapult flow, they were able to complete several complex designs in a very short seven months cycle even though their specifications were evolving over the entire design cycle. They were also able to produce higher quality designs through continuous refinement and as a result they have now fully switched over their design methodology to using the Catapult High-Level Synthesis flow. Kudos to Mentor for taking design synthesis to the next level!

See Also:
Full white paper by Bosch Visiontec and Mentor
Mentor Catapult product page

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Power Integrity from 3DIC to Board

Power Integrity from 3DIC to Board
by Bernard Murphy on 09-14-2017 at 7:00 am
Categories: Ansys, Inc., EDA

The semiconductor industry has built decades of success on hyper-integration to increase functionality and performance while also reducing system cost. But the standard way to do this, to jam more and more functionality onto a single die, breaks down when some of the functions you want to integrate are built in different processes. This is why 3DICs – integration of multiple die in 3D stacks and on interposers – have become popular. One currently popular application combines high bandwidth memory side-by-side with processors, allowing for higher-bandwidth communication through low-impedance / highly-parallel connections directly between DRAM stacks and main memory.

Naturally with each design innovation like this come new design problems. One of these is managing power integrity in these systems all the way out to the package and board level. Normally we think of power integrity analysis and power distribution network (PDN) design as something that can be managed chip by chip, forgetting that this is possible thanks to high impedance between packages, and high chip operating frequencies minimizing inter-chip impact on on-chip power noise. But now we have a range of impedances with low resonant frequencies at the board level (MHz), mid-range at the interposer/TSV level (100s of MHz) and high range (GHz) at the chip level, implying a wide span of potential impact on power integrity. Even where board-level frequencies may still be ignored, those mid-range frequencies cannot.

As a result, it is no longer effective to look at each chip in isolation. Power integrity analysis must look at minimum at the whole 3DIC in package objective. Ansys recently hosted a webinar where they talk in particular about this range of power integrity analysis. There are two major components to this kind of analysis – one is to build an accurate power model for the whole 3DIC device which you can use in detailed transient and AC Spice analysis and the other is to ensure that your models effectively reflect usage across a very wide response range, potentially from board/package level (MHz) up to chip-level (GHz).


Building an accurate power model has several components. Analysis for a chip/die is already well understood and can be implemented through RedHawk or Totem (for analog designs). RedHawk is also recommended for extraction on the interposer; this is really just another semiconductor device supported by foundry tech files, and extraction here is a task well within RedHawk capabilities. Ansys recommends that extraction for TSVs be handled by SIwave / HFSS. Together these can be combined into a system chip power model (CPM) which you can use for detailed transient and AC analysis in the Ansys Chip Model Analyzer (CMA).


In the second stage of this analysis it is important to ensure that the CPM models reflect the wide response range inherent to the total system. Here, in chip level analysis, you may look at tens of nanoseconds of activity (blue sections above). But at more widely-separated intervals, discontinuous events will happen causing potentially larger power transitions, as a result of perhaps transition from functional activity to an idle mode on another chip in the 3DIC package or even on another device on the board (red sections above).


It would be impractical to consider an accurate analysis at the nanosecond level across a microsecond range. Instead CMA provides you with tools to construct a representative power noise frequency spectrum based on a chip-level high-frequency response and lower frequency input which can be generated through a variety of methods to reflect interposer/TSV and package/board response to these discontinuities. These can then be merged to generate a new CPM more accurately mirroring the full range of response.

Methods you can use to model these longer cycle-time events include envelope profiles over long time-frames, for example derived from PowerArtist profiles or through manually-specified profiles (perhaps to reflect on-board sensor switching) or through impedance-aware random noise generation based on the PDN for the 3DIC and perhaps the board.

Fully optimizing the system-level PDN has become even more critical task given these 3DIC devices with their range of resonant frequencies from the chip down to the board level. What is clear is that this now requires a broader analysis. You can request a link to the webinar HERE.