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Improving Library Characterization with Machine Learning!

Improving Library Characterization with Machine Learning!
by Daniel Nenni on 12-04-2018 at 7:00 am
Categories: EDA, Siemens EDA

For SOC designers that are waiting for library models the saying “give me liberty or give me death” is especially apropos. Without libraries to support the timing flow, SOC design progress can grind to a halt. As is often the case, more than just a few PVT corners are needed. Years ago, corners were what the term sounded like – the 4 corners of a square. In today’s designs, they are more like the many corners in a massive Parisian roundabout. Multiplied by the hundreds of cells in a typical library, the size of the library creation task has become an enormous undertaking.

In fact, Wei-Lii Tan, Product Manager in Mentor’s AMS Design and Verification group, estimates that it can take between 10 to 100 million simulation runs to create a usable library. This figure comes from their white paper on improving library characterization by using machine learning. If we have learned anything about machine learning in the last few years, it is its ability to revolutionize the tasks that is it applied to. It turns out that this is indeed the case for semiconductor design too.

Mentor’s MLChar Generator and MLChar Analytics address this problem by applying predictive machine learning to this difficult task. Mentor identifies five challenges that have hindered timely and accurate library development for SOC projects. They are: runtime and throughput, accuracy of results, incremental PVT corner characterization, library validation, and debugging and repairing. Each of these benefits greatly from the application of machine learning.

The value proposition for the acceleration machine learning provides really comes to light when teams are faced with the need for new corners that were not available in the initial library, or when the process for the cell library is relatively new and undergoing revisions. To see how it’s useful to look at the process Mentor’s MLChar uses.

The input to MLChar generator is a subset of the Liberty files for PVT corners, which are called anchor corners. With a properly selected set of anchor corners the number of corners that need to be generated by brute force simulation can be reduced by 30 to 70%. MLChar will even help select the optimal anchor corners. Using MLChar, new PVT corners can be produced in a fraction of the runtime that would be needed for full simulation.

An interesting side benefit is because MLChar does not need device models or simulator runs, new corners can be created easily if the need arises, without having to duplicate the initial library characterization setup.

Machine learning is also very good at finding anomalies in data, making it a great tool for validating libraries. It is useful for detecting outliers and ‘spikes’ that could indicate issues in the library characterization process. It comes with a suite of analytics and visualization tools to make debugging library issues much easier.

The net effect of using machine learning is a dramatic reduction in the time needed for library generation of standard cells or memories, with virtually no loss in accuracy. Additionally, the speed up for library validation not only improves library quality, but shortens the process. There is much more about the technology and how it works in the whitepaper. Mentor is making good use of its acquisitions, this whitepaper shows that they are continuing the technology and initiatives that Solido brought to the table, absolutely!

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Car Vandals Eschew Crowbars

Car Vandals Eschew Crowbars
by Tom Simon on 12-03-2018 at 12:00 pm
Categories: Automotive, IP, Security, Synopsys

It used to be that automotive theft and crime was perpetrated with a crowbar. Now with increased electronics content, car designer and owners need to worry about electronic threats. Anywhere there is a communication link or a processor, there are potential threats to the security of the car. The range of these threats covers everything from privacy, safety, malicious intent, damage or even vehicle theft. Automotive suppliers are taking these threats seriously and designing their products with security in mind up front.

On the privacy front, hackers could listen in as you speak inside your car, or they could track your location. Every automated system could be tampered with from door locks, to safety critical systems such as airbags and crash avoidance. Hacked motor and automotive control systems could be harmed by improper commands.

Cars are coming with more and more data connections to the outside world, ones that could be exploited by hackers or malicious actors. The question is, what can be done to minimize security vulnerabilities in connected cars? Synopsys has a technical bulletin that discusses the fundamental problem and ways to deal with it. The paper written by Mike Borza, Principle IP Security Technologist at Synopsys, is titled “Minimizing Security Vulnerabilities in Connected Cars Starts with Silicon”.

They posit that by 2023 there will be over 70 million connected cars on the road. Each one of them will have multiple connections that could be used to compromise their security. This can range from USB, SD, AUX connections to WiFi, Bluetooth, and embedded modem devices. With new smart car functionality, comes increasing pathways in and out of the vehicle. Prevention of these threats requires a ground up approach starting at the SOC level to ensure security.

Two significant types of breaches are installation of hacked software and intercepted or falsified communications. Synopsys asserts that the best way to protect software integrity is to build security into the silicon that it is running on. Using Hardware Root of Trust can enable the creation of a Trusted Execution Environment (TEE). Synopsys’ approach is to provide SOC developers an IP Hardware Security Module (HSM) that offers an isolated secure processing enclave that serves as the center of chip security.

The HSM contains a set of secure services to enable unique chip identification, encryption and application code validation. At startup, the HSM is the first unit that begins operating, it can then validate its own code and then ensure that any application code run on other processors in the system have not been tampered with. Once the SOC is up and running the HSM can provide encryption API’s that make possible secure and authorized communication within and outside of the vehicle.

Synopsys calls its hardware security module tRoot HSM. It offers complete IP for implementing a TEE and also is supported by software libraries and development tools that enable SOC designers to build a complete hardware/software solution and also perform debug and ensure post production test.

The Synopsys Technical Bulletin delves into the details of how tRoot HSM IP can contribute to making SOCs targeted for automotive use as secure as possible. One key take-away is that it’s important to have a complete system that includes all the components, from hardware IP to software, to ensure robust security.

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9 IoT Predictions for 2019

9 IoT Predictions for 2019
by Ahmed Banafa on 12-03-2018 at 7:00 am
Categories: IoT

By 2020, the Internet of Things (IoT) is predicted to generate an additional $344B in revenues, as well as to drive $177B in cost reductions. IoT and smart devices are already increasing performance metrics of major US-based factories. They are in the hands of employees, covering routine management issues and boosting their productivity by 40-60% [1].

The following list of predictions (Figure 1) explores the state of IoT in 2019 and covering IoT impact on many aspects business and technology including Digital Transformation, Blockchain, AI, and 5G.


Figure 1: IoT Predictions For 2019

IoT Prediction 1: Growth in Data and Devices
By the end of this year there will be are around 3.6 billion devices that are actively connected to the Internet and used for daily tasks according to IT Pro [8]. With the introduction of 5G that will open the door for more devices, and data traffic. You can add to this trend the increase adoption of edge computing which will make it easier for business to process data faster and close to the points of action [5].

IoT Prediction 2: IoT and Digital Transformation
IoT is a key driver of digital transformation in several industries. Sensors, RFID tags, and smart beacons have already started the next industrial revolution. Market analysts predict the number of connected devices in the manufacturing industry will double between 2018 and 2020.

These devices are a total game changer for the many industries, disrupting every part of the production process from development to supply chain management. Manufacturers will be able to prevent delays, improve production performance. Another example; in 2019; 87% of healthcare organizations will have adopted IoT technology. The possibilities are endless for healthcare organizations and the IoT—smart pills, smart home care, personal healthcare management, electronic health records, managing sensitive data, and an overall higher degree of patient care. This type of improvements can be applied to many sectors vertically and horizontally [6][9].

IoT Prediction 3: More Investments in IoT
IoT’s undisputable impact has and will continue to lure more startup venture capitalists towards highly innovative projects in hardware, software and services. Spending on IoT will hit 1.4 trillion dollars by 2021 according to the International Data Corporation (IDC) [7].

IoT is one of the few markets that have the interest of the emerging as well as the traditional venture capitalists. The spread of smart devices and the increase dependency of customers to do many of their daily tasks using them, will add to the excitement of investing in IoT startups. Customers will be waiting for the next big innovation in IoT—such as smart mirrors that will analysis your face and call your doctor if you look sick, smart ATM machine that will incorporate smart security cameras, smart forks that will tell you how to eat and what to eat, and smart beds that will turn off the lights when everyone is sleeping [5][14].

IoT Prediction 4: Expansion of Smart IoT
IoT is all about connectivity and processing, nothing will be a better example than smart cities , but smart cities have been in a bit of a holding pattern recently. Smart sensors around the neighborhood will record everything from walking routes, shared car use, building occupancy, sewage flow, and temperature choice 24/7 with the goal of creating a place that’s comfortable, convenient, safe, and clean for those who live there. Once the model is perfected, it could be the model for other smart neighborhoods and eventually smart cities [2].

Another area of spreading smart IoT is auto industry with self-driving cars become a normal occurrence in the next few years, today tons of vehicles have a connected app that shows up to date diagnostic information about the car. This is done with IoT technology, which is the heart of the connected vehicle. Diagnostic information is not the only IoT advancement that we will see in the next year or so. Connected apps, voice search, and current traffic information are a few other things that will change the way we drive [2].

IoT Prediction 5: Artificial Intelligence and IoT Data
Artificial intelligence is the fundamental ingredient needed to make sense of the vast amount of data collected these days, and increase its value for business. AI will help IoT data analysis in the following areas: data preparation, data discovery, visualization of streaming data, time series accuracy of data, predictive and advance analytics,andreal-time geospatial and location (logistical data). Here are a few examples.

  • Data Preparation: Defining pools of data and cleaning them, which will take us to concepts like Dark Data and Data Lakes.
  • Data Discovery: Finding useful data in defined pools of data.
  • Visualization of Streaming Data: On-the-fly dealing with streaming data by defining, discovering data, and visualizing it in smart ways to make it easy for the decision-making process to take place without delay.
  • Time Series Accuracy of Data: Keeping the level of confidence in data collected high with high accuracy and integrity of data
  • Predictive and Advance Analytics: Making decisions based on data collected, discovered and analyzed.
  • Real-Time Geospatial and Location (Logistical Data): Maintaining the flow of data smoothly and under control [3].

IoT Prediction 6: Fog Computing & IoT
Fog computing is a technology that distributed the load of processing and moved it closer to the edge of the network (sensors in case of IoT). The benefits of using fog computing are very attractive to IoT solution providers. Some of these benefits allow users minimize latency, conserve network bandwidth, operate reliably with quick decisions, collect and secure a wide range of data, and move data to the best place for processing with better analysis and insights of local data. Microsoft just announced a $5 billion investment in IoT, including fog/edge computing [3][4][5].

Hardware manufacturers like Cisco, HPE, Dell and more are building specific infrastructure for the edge deigned to be more physically rugged and secure, and security vendors will start to offer endpoint security solutions to their existing services to prevent data loss, give insights into network health and threat protection, include privileged user control and application whitelisting and control, that will help in the fast adoption and spread of edge/fog computing implementations by businesses [2].

IoT Prediction 7: IoT and Blockchain
The current centralized architecture of IoT is one of the main reasons for the vulnerability of IoT networks. With billions of devices connected and more to be added, IoT is a big target for cyber-attacks, which makes security extremely important.

Blockchain offers new hope for IoT security for several reasons. First, blockchain is public, everyone participating in the network of nodes of the blockchain network can see the blocks and the transactions stored and approves them, although users can still have private keys to control transactions. Second, blockchain is decentralized, so there is no single authority that can approve the transactions eliminating Single Point of Failure (SPOF) weakness. Third and most importantly, it’s secure—the database can only be extended and previous records cannot be changed.

In the coming years manufactures will recognize the benefits of having blockchain technology embedded in all devices and compete for labels like “Blockchain Certified”[3][5].

IoT Prediction 8: IoT and Standardization
Standardization is one of the biggest challenges facing growth of IoT—it’s a battle among industry leaders who would like to dominate the market at an early stage. Digital assistant devices, including HomePod, Alexa, and Google Assistant, are the future hubs for the next phase of smart devices, and companies are trying to establish “their hubs” with consumers, to make it easier for them to keep adding devices with less struggle and no frustrations [3][5].

But what we have now is a case of fragmentation. One possible solution is to have a limited number of vendors dominating the market, allowing customers to select one and stick to it for any additional connected devices, similar to the case of operating systems we have now have with Windows, Mac and Linux for example, where there are no cross-platform standards [3][5].

To understand the difficulty of standardization, we need to deal with all three categories in the standardization process: Platform, Connectivity, and Applications. In the case of platform, we deal with UX/UI and analytic tools, while connectivity deals with customer’s contact points with devices, and last, applications are the home of the applications which control, collect and analyze data. All three categories are inter-related and we need them all, missing one will break that model and stall the standardization process [3][5].

There is no way to solve the problem of fragmentation without a strong push by organizations like IEEE or government regulations to have common standards for IoT devices [3][5].

IoT Prediction 9: IoT Skills Shortage
While investment in the Internet of Things (IoT) is set to reach over $1 trillion by 2020, according to IDC, the need for IoT skills may just hamper this growth. In fact, according to a Canonical report, 68% of businesses still struggle to hire IoT experts [10]. The latest Tech Cities Job Watch report from Experis showed a 35% increase in the demand for technology skills since this time last year, as businesses look to harness the power of IoT [11][13].

The Tech Cities Job Watch report noted that IoT has massively increased the number of connected devices and has exploded the volumes of data businesses have to process and as a result, big data roles are important to delivering success on IoT. The report found that businesses were willing to pay for such skills, with big data professionals commanding by far the highest salaries and day rates of any other technology discipline analyzed [13].

Since connected devices also create many more vulnerabilities to cyber threats for businesses to contend with, security skills are also in demand, the report found. There has been a 24% increase (year-on-year) in the demand for IT Security contractors. Businesses are urgently plugging short term security gaps and using contractors to train up existing employees across the business and are shifting focus to this more flexible contractor model for IT security in response to the demands for IoT [13].

Universities cannot keep up with the demand, so to deal with such shortage, companies have established internal training programs to build their own teams, upgrading the skills of their own engineering teams and training new talents. This trend will continue, representing an opportunity for new engineers and a challenge for companies [3][5].

References

[LIST=1]

  • https://mobidev.biz/blog/iot-trends-for-business-2018-and-beyond
  • https://www.forbes.com/sites/danielnewman/2018/07/31/five-iot-predictions-for-2019/#5a73cf186edd
  • https://www.linkedin.com/pulse/looking-ahead-whats-next-iot-ahmed-banafa/
  • https://blogs.wsj.com/cio/2018/04/05/it-execs-see-promise-in-iot-reinforcing-microsofts-5b-investment/
  • https://www.amazon.com/Secure-Smart-Internet-Things-Iot/dp/8770220301/
  • https://www.i-scoop.eu/internet-of-things-guide/internet-things-healthcare/
  • https://www.roboticsbusinessreview.com/manufacturing/an-introduction-to-the-internet-of-things/
  • https://www.itproportal.com/features/next-big-things-in-iot-predictions-for-2020/
  • https://www.linkedin.com/pulse/iot-ai-blockchain-catalysts-digital-transformation-ahmed-banafa/
  • https://blog.ubuntu.com/2017/08/09/68-of-businesses-are-struggling-to-hire-talent-for-iot?_ga=2.150705918.931132101.1502305379-1356650044.1502305379
  • http://techcities.experis.co.uk/?utm_source=exp_insights&utm_medium=website&utm_term=none&utm_content=q42017&utm_campaign=techcities
  • https://www.forbes.com/sites/forbestechcouncil/2018/08/23/so-you-want-a-job-in-iot-here-are-the-three-skills-every-iot-company-looks-for/#14a1f97c45b7
  • https://www.idgconnect.com/idgconnect/analysis-review/1003535/talent-shortage-hampering-iot-development
  • https://www.linkedin.com/pulse/8-trends-iot-2018-ahmed-banafa/


    This article appeared first on IEEE-IoT : https://iot.ieee.org/newsletter/november-2018/nine-iot-predictions-for-2019

    Ahmed Banafa, Author the Book: Secure and Smart Internet of Things (IoT) Using Blockchain and AI

    Read more articles at IoT Trends by Ahmed Banafa

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    Auto Cyber Security: From Ignorance to Compliance

    Auto Cyber Security: From Ignorance to Compliance
    by Roger C. Lanctot on 12-02-2018 at 7:00 am
    Categories: Automotive, Security

    Auto makers have long relied on security by obscurity to get away with not defining or adhering to proper cyber security hygiene. This rationalization had been embraced in the context of low levels of automotive hacking mainly carried out by enthusiasts or so-called “white hat” or ethical hackers.

    A new report from Strategy Analytics, highlighting the contributions of Argus Cyber Security, identifies the growing array of standards and regulations governing automotive security. The report points out that auto makers must confront and take responsibility for the vulnerability of their vehicles especially in the context of evolving autonomous vehicle tech.

    – Argus Helps Answer the Call for Automotive Cyber security Regulation

    In fact, the recent passage, and signing by President Trump, of the Cybersecurity and Infrastructure Security Agency Act of 2018, has established the Cybersecurity and Infrastructure Security Agency within the Department of Homeland Security. The Act and the Department recognize 16 critical infrastructure sectors, one of which is “Transportation Systems.”

    – Website of new CISA agency

    – Text of Cybersecurity and Infrastructure Security Agency Act of 2018

    While the focus of the Act is infrastructure, it is the belief of cyber security professionals that it is only a matter of time before the onset of autonomous vehicles triggers the identification of connected vehicles as part of this critical infrastructure. This perspective was voiced just this week at the Security Summit held at the L.A. Auto Show. Bryson Bort, CEO and founder of Scythe, in particular, emphasized this point.

    Bort’s concerns were echoed at the Summit by John Gomez, CEO of Sensato, who focused on ransomware as the most immediate automotive cyber security concern. Gomez identified three types of threats including cyber criminals, cyber spies and cyber terrorists with the motivations being profit, intelligence, and ideology, respectively. Other speakers noted ongoing concerns with privacy and data ownership (Lauren Smith, Future of Privacy Forum) and the vulnerability of app-based car-sharing programs (Mikhail Savushkin, Kapsersky Labs).

    Automotive cyber security was long ignored because it had no constituency or business model. Consumers weren’t looking for “secure” cars and car makers weren’t required to make secure cars. That is rapidly changing – especially with the onset of new laws and regulations around the world.

    Before theses new laws and regulations, though, there was the famous “Jeep hack” of 2015. This hack, pulled off by Charlie Miller and Chris Valasek, embodied all of the shortcomings of the prevailing cyber security ignorance in the automotive industry at the time.

    Miller and Valasek identified a vulnerability in certain Jeep models from FCA. Miller and Valasek likely notified FCA of the problem. They were likely disappointed in FCA’s response – so they created a video demonstrating the potentially horrendous implications of the vulnerability: remote control of certain vulnerable Jeeps.

    FCA suffered a massive public relations blow along with absorbing the nine-figure cost of recalling millions of vehicles to correct the security flaw. Finally, the entire industry got the message. (Miller and Valasek now work directly for General Motors after briefly working at Uber.)

    The lessons learned:

    • Hackers can be helpful and must not be ignored
    • Car makers cannot rely on hackers to identify and fix vulnerabilities
    • Fixing vulnerabilities in the field is expensive (and embarrassing)
    • Connectivity is essential to identifying, preventing and correcting cyber security vulnerabilities
    • Cyber security must be addressed throughout vehicle design and system integration

    The automotive industry is not out of the cyber security woods. The good news is that General Motors has seen fit to elevate cyber security to a Board-level responsibility – a model for other car companies to emulate.

    Will there be more automotive hacks? No doubt. Do we have time to prepare for the day when cars are designated critical infrastructure? Yes. Will cars ever be certifiably secure? No

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    Webinar: Turnkey Bluetooth True Wireless Stereo Earbuds and Speakers

    Webinar: Turnkey Bluetooth True Wireless Stereo Earbuds and Speakers
    by Bernard Murphy on 12-01-2018 at 7:00 am
    Categories: Ceva, Events, IP, Mobile

    When we were first introduced to earbuds, in-ear speakers connected through thin wires to your phone (and earlier portable music devices), they seemed pretty convenient for private entertainment at work, while walking, exercising, doing almost anything. Until we started to realize those long dangly wires weren’t ideal. They’d snag easily, and pull out an earbud, they tie themselves into frustrating bundles of knots when stuffed in a pocket and those skinny wires aren’t very robust. When we’re surrounded by wireless technology, why do we still need wires for earbuds? The same point could be made for home speakers. While wireless communication races ahead, why are audio connections stuck in the dark ages?

    Register HERE for the CEVA Webinar at 10 AM CET on December 5[SUP]th[/SUP]. I’m guessing this is primarily for EMEA/Asia audiences. A bit early/late for the US but no matter where you are register anyway and you will get a link to the replay.

    Apple Airpods showed the way with truly wireless earbuds. Others quickly followed with pseudo wireless offerings which didn’t need a wired connection to your phone but did come with a strap between the earbuds, like the granny strap for your glasses. More than a few consumers decided they didn’t need that strap, so they cut it off. Oops. Turns out the strap wasn’t just a fashion statement. One earbud received an audio stream from the phone, played one of the stereo channels and forwarded the other channel to the other earbud through that strap. Truly wireless stereo earbuds are a bit harder, especially if you want them to be usable for several hours (there isn’t a lot of space in those tiny devices for big batteries).

    Similar concerns and more apply to home audio systems. When you want to outfit your man-cave/she-shack with surround-sound, having to run cables from speakers to the amplifier just seems so, well, 20[SUP]th[/SUP]-century. Sure you have to power the speakers, but audio streaming should be wireless. There’s another concern here too – synchronizing channels. In a typical room, there’s enough distance between speakers and the source for channel synchronization to become a concern; you don’t want what should be beautiful surround sound to become a confusing jumble. Listen to this webinar to understand how CEVA and Tempow provide a low power, truly wireless stereo experience scaling all the way from wireless earbuds to home audio.

    Abstract
    A recent market study from the Bluetooth SIG shows that shipments of Bluetooth audio devices are growing steadily, and set to exceed 1.2 billion units annually by 2022. This market is dominated by headsets shipments, with wireless earbuds as one of the hottest devices in the market today. And for wireless earbuds, true wireless stereo is the technology enabling this market. This webinar presents the various solutions available on the market for true wireless stereo, with particular focus on the Tempow – CEVA innovative solution.

    Join CEVA and Tempow experts to learn about:

    • Market trends in the Bluetooth audio market
    • Benefits of Bluetooth for audio streaming
    • Overview of existing proprietary true wireless stereo solutions for earbuds and speakers
    • The True Wireless Earbuds joint solution from Tempow & CEVA

    Target Audience
    Design, system and product engineers targeting Bluetooth SoC for true wireless stereo earbuds and speakers. Smartphone makers interested in designing their own earbuds products

    Speakers


    Franz Dugand
    Sales and Marketing Director, Connectivity BU, CEVA, Inc.


    Vincent Nallatamby
    CEO, Tempow

    Register HEREfor the CEVA Webinar at 10 AM CET on December 5[SUP]th[/SUP]

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    RISC-V End to End Solutions for HPC and Networking

    RISC-V End to End Solutions for HPC and Networking
    by Daniel Nenni on 11-30-2018 at 12:00 pm
    Categories: FinFET, IP, OpenFive, RISC-V, Semiconductor Services

    Semiconductor IP is one of the more exciting and most viewed topics we cover on SemiWiki, it has been that way since we began in 2011 and that trend will continue indefinitely, my opinion.

    Semiconductor IP: Total Blogs: 640: Total Views: 3253751: Average: 5084

    Based on the design starts we track, Cloud Computing is a leading semiconductor driver so High Performance Computing (HPC) and Networking IP development and deployment will closely follow including High Bandwidth Memory (HMB2) and Serializer-Deserializer (SerDes) IP.

    Specifically, higher memory bandwidth at lower power and technical capabilities (2.5D Interposer-based ASIC design in combination with the new JEDEC HBM Gen2 standard). It needs the integration of significant capacities of high-bandwidth (up-to 256GB/s for an 8-channel, 8Gb memory stack implementation) and low latency memory inside the ASIC package. Open-Silicon’s full IP subsystem solution includes an HBM2 controller, PHY and interposer I/O, and completes the critical components needed for the successful integration of HBM2 memory into ASIC system-in-package (SiP) designs.

    One of the more exciting emerging IP companies I have come across is Credo (meaning “I believe”). Credo delivers high-performance, mixed-signal semiconductor IP including SerDes and interconnect products for 25G, 50G, and 100G connectivity. Walden International led Credo’s first round of funding in 2015 and if you look at the management profiles you will see deep Marvell Semiconductor experience. I did get a chance to catch up with Jeff Twombly of Credo who is quoted below. Jeff is a long time Silicon Valley semiconductor guy, very approachable, and engaging. I highly recommend getting coffee with Jeff to get the latest on the SerDes business, absolutely.

    As you may know I am a big fan of the ASIC business and we have been working with Open-Silicon for the past two years on research, blogs, and we jointly published an eBook on Custom SoCs for IoT. Open-Silicon is now listed as a SiFive Company which we can discuss further in the comments section if you like. Which brings us to the recent announcement by Open-Silicon and Credo which is definitely worth a read:

    SiFive, Credo and Open-Silicon Showcase End-to-End Solutions for HPC and Networking Applications at SC18 in Dallas

    DALLAS, Texas – November 12, 2018 – SiFive, Credo and Open-Silicon will exhibit complete end-to-end solutions for HPC and networking applications at Supercomputing 2018 (SC18) in Dallas, TX. The co-demonstration illustrates the capabilities of SiFive’s highest performance RISC-V Core IP U7 Series, Open-Silicon’s HBM2 IP subsystem and Credo’s high performance, low power, mixed-signal 112Gbps PAM4 SerDes. Custom SoC solutions and critical IP cores, including Interlaken IP and Ethernet IP subsystems, will also be showcased.

    The SiFive Core IP U7 Series is a high-performance RISC-V applications processor featuring a dual-issue superscalar core with domain-specific customizations required for embedding intelligence from the edge to the cloud. The U7 series microarchitecture optimizes performance and power enabling high throughput systems for diverse compute workloads and form-factors. Credo’s 112G SerDes, silicon proven in advanced 7nm FinFET node, enables rapid build-out of next-generation 100G, 400G and 800G Ethernet cloud networks, and delivers higher bandwidth, lower power and optimum lane count configurations. Open-Silicon’s HBM2 IP subsystem solution, in FinFET technologies, includes an HBM2 controller, PHY and interposer I/O. It provides the highest performance and flexibility for integrating HBM directly into next-generation custom SoC 2.5D SiP solutions.

    “The SiFive Core IP U7 Series provides a compelling feature set that includes scalability, extensibility, 64-bit architectures, and a heterogenous coherent combination of real-time and application processors for next generation compute requiring embedded intelligence,” said Jack Kang, VP of Product Marketing, SiFive.

    “Credo’s silicon-proven 56G/112G SerDes IPs, combined with Open-Silicon’s SerDes Technology Center of Excellence, minimizes risk and time-to-market for developing next generation HPC and networking custom SoCs,” added Jeff Twombly, Vice President of Marketing and Business Development, Credo.

    “This collaborative demonstration with SiFive and Credo is an excellent opportunity to unveil the power of a complete end-to-end solution for next generation custom SoC solutions for high-performance and bandwidth applications,” said Shafy Eltoukhy, SVP of Operations and GM, Open-Silicon.

    About SiFive
    SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. www.sifive.com

    About Credo
    Credo is a leading provider of advanced SerDes IP. www.credosemi.com

    About Open-Silicon
    Open-Silicon, a SiFive company, is a system-optimized custom SoC solution provider. www.open-silicon.com

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    Security and RISC-V

    Security and RISC-V
    by Bernard Murphy on 11-30-2018 at 7:00 am
    Categories: Events, IP, RISC-V, Security, Tortuga Logic

    One of the challenges in the RISC-V bid for world domination may be security. That may seem like a silly statement, given that security weaknesses are invariably a function of implementation and RISC-V doesn’t define implementation, only the instruction-set architecture (ISA). But bear with me. RISC-V success depends heavily on implementors not yielding to the temptation of non-standard extensions in the pursuit of differentiation. It also depends heavily on a perception that, where it matters, implementations are at least as secure as equivalent ARM offerings.

    Whatever you may think of the ARM hegemony, you can’t deny that they are putting a lot of work into security, from the device-level all the way up to the total system. Especially in the IoT, wherever the security floodgates break (when we will really wake up to the importance of security) security-lite RISC solutions are not going to do well. Recognizing this, the RISC-V Foundation has formed a security standing committee, chaired by Dr. Helena Handschuh of Rambus.

    The technical goals of the standard continue to be in ISA refinement, so this committee will be considering extension to the privilege specification as well as extensions in support of cryptography. And of course they have a promotional goal to encourage adoption of and to further innovation around the RISC-V standard particularly with respect to security. About 25 companies are represented on the committee, from security specialists to IP vendors and large semiconductor vendors.

    One of these companies is Tortuga Logic, who I have written about before. I talked to Jason Oberg, CEO of Tortuga, about their role in this activity. Tortuga’s whole objective is security, particularly against side-channel attacks, so they should be able to add real value to the committee. Naturally they have a business interest. When they’re aligned with the standard, their tools and IP should become attractive in guiding design for anyone implementing or using RISC-V. Which should in turn provide objective measures of security and therefore build confidence around using these implementations. A virtuous cycle with Tortuga making some money along the way. (I asked Jason what they plan to do in the spirit of open support. He said they’re thinking of possibly releasing an open threat-model for RISC-V.)

    If you’re plugged into the RISC-V world, you’ll know that there is a summit next week, December 4th-5th at the Santa Clara convention center. Jason will be presenting in the afternoon of the 5th on a security verification framework for RISC-V, also Tortuga will have a booth in the exhibit hall. Their demo should be pretty interesting; they have applied their technology to analysis of the open Rocket core and will show a number of side-channel issues they found in that implementation. You might want to check out the demo if only to better understand how your current verification strategy will probably miss these kinds of problem and to realize that those deficiencies may not be easy to fix through better testbenches or more formal verification.

    You can register for the summit HERE and learn more about Tortuga Logic HERE.

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    On-Chip Networks at the Bleeding Edge of ML

    On-Chip Networks at the Bleeding Edge of ML
    by Bernard Murphy on 11-29-2018 at 7:00 am
    Categories: AI, Arteris, IP
    3 Comments

    I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse for training, and for the early incarnations of some mobile apps (mobile AR/MR for example), FPGAs in applications where architecture/performance becomes more important but power isn’t super-constrained, DSPs in applications pushing performance per watt harder and custom designs such as the Google TPU pushing even harder.


    At the high end, there is no pre-agreed set of “best” architectures. Everyone is experimenting to find the best performance per watt for their application. This is tricky. There are some needs in common with conventional computing – you want to quickly read in data, process computations, access and store to memory. However, maximally exploiting the spatially distributed nature of NN algorithms for performance and power pushes architects to distributed compute, most commonly in grids, rings or tori. These also exploit memory hierarchies, also distributed, and high-bandwidth memory (HBM) for bulk memory off-chip (or off-die in 2.5/3D packaging).

    These architectures naturally push chip size, in the example above to 400mm[SUP]2[/SUP] and larger sizes are not uncommon. So now you have a hard problem in getting to timing closure across that big die. And if that wasn’t enough, ML typically requires massive amounts of data to be broadcast for image map and weight updates. So bandwidth demand in these systems can be huge, creating potentially massive traffic congestion and power problems.

    Arteris IP has been working for many years with customers using ML technology, supporting near real-time inferencing at the edge with the likes of Mobileye, NXP, HiSilicon and others. But now they’re finding multiple companies wanting to support training at the edge, one very active direction for them coming from camera makers. And they’re seeing more activity around ML training acceleration in the datacenters. Of customers Arteris IP has announced, Baidu seems like an obvious fit here. Which in itself is interesting. After all, don’t NVIDIA dominate this space? Again, everyone’s looking for differentiation, not something you’re going to find if you’re just using the same platform everyone else is using. Not that Tegra isn’t a great solution but if you want to be at the bleeding edge, adding your own secret hardware sauce to your ML pipeline can be a way to pull ahead.

    So what does all of this take? First, if you have distributed compute, you’re going to need an on-chip network to connect all of those compute nodes and the on-chip memory hierarchy and the off-chip memory. But it’s not quite as push-button as generating the grid in the opening graphic. In a strong NoC solution maybe you can dial in rings and tori, but these architects need more. Performance (and power) depends on very tightly coupled memory, so they want to embed local caches in the configuration. But there’s no fixed formula for where; they want to experiment to understand latencies and PPA implications. Those architects want to be to interact with network generation, to control where they want holes in the grid for memory blocks.


    This goes further. High-end ML architects even want to tune the routers in the network they build, for example to add pipeline stages or FIFOs, or change the number of masters or slaves for a router or just one of the corner routers. All of these needs have implications for the architecture of the NoC generator. The standard method is compiler-centric. You dial in a bunch of parameters, interact through an interface to control details and generate. Which works very well in the processor and IP centered world for which this flow has been optimized over many years. But ML architects don’t have a standard recipe. They want to fool with almost everything, but they still want the benefit of automated generation, with all the flexibility of being able to customize the topology and the routers through that interface.

    This is the first of 3 advances offered in Arteris IP’s just-announced AI package, available as an option to their recent FlexNoC4 release. They told me they have been working on this (and other features I mention below) for multiple years with their ML-driven customers. Kurt Shuler (VP Marketing) tells me these they’ve been responding to their customer ML needs, polishing and productizing this stuff for quite a while.

    So, flexible network architecture (both logical and physical) while preserving the benefits of automating generation? Check. What about the big-die/timing closure problem? In general, timing closure across huge die isn’t a new problem. It’s very difficult to balance a clock tree across the full span of the design, so the standard solution is to use some kind of globally asynchronous, locally synchronous design technique. A popular solution is source-synchronous clocking; you forward the clock along with the data between locally synchronous domains. FlexNoC 4 includes support for a very lightweight approach that achieves this goal while minimizing congestion. The technology also provides support for multiplexing wires over long distances (again to mitigate congestion) using something they call VC-Links. Incidentally this solution is integrated with the Arteris IP PIANO timing closure package, so an architect can see where obstructions are and add virtual channels as needed.

    Finally, there’s the bandwidth problem. One aspect is broadcast; how do you distribute lots of data to many destinations without dragging the whole system down? Through intelligent distribution is the Arteris IP answer. Distribute to a limited number of broadcast stations close to the destinations, then have those stations distribute locally. Obvious when you see it, but this requires a solution that supports architecting those broadcast stations into the network.

    For traffic jams at HBM, the package provides methods to maintain high utilization of all connections into the memory controller through interleaving between initiators and targets, reorder buffers, traffic aggregation and data width conversions and support for very wide (1024 bits) connections where needed. Arteris IP have also added optimizations for datapaths, supporting up to 2048 bits wide.

    All of which reinforces that design for AI/ML is not the same as design for traditional SoC components. The challenges are different and they require significantly enhanced solutions. You can learn more about FlexNoC 4 and the AI package HERE.

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    Designer babies are here ready or not!

    Designer babies are here ready or not!
    by Vivek Wadhwa on 11-28-2018 at 12:00 pm
    Categories: General
    3 Comments

    A Chinese scientist from a university in Shenzhen claims he has succeeded in creating the world’s first genetically edited babies. He told the Associated Press that twin girls were born earlier this month after he edited their embryos using CRISPR technology to remove the CCR5 gene, which plays a critical role in enabling many forms of the HIV virus to infect cells.

    Whether the claims are true or false, one thing is clear: We are entering an era of designer babies. Scientists will soon be able to edit human embryos with the aim of eliminating debilitating disease, selecting physical traits such as skin and eye color, or even adding extra intelligence. Our understanding of the effects of the technology is in its infancy, however.

    The technology is CRISPR: clustered regularly interspaced short palindromic repeats. Discovered by scientists only a few years ago, CRISPRs are elements of an ancient system that protects bacteria and other single-celled organisms from viruses, acquiring immunity to them by incorporating genetic elements from the virus invaders. CRISPRs evolved over millions of years to trim pieces of genetic information from one genome and insert it into another. And this bacterial antiviral defense serves as an astonishingly cheap, simple, elegant way to quickly edit the DNA of any organism in the lab.

    Until recently, experimenting with DNA required sophisticated labs, years of experience, and millions of dollars. The use of CRISPRs has changed all that. CRISPRs work by using an enzyme — Cas9 — that homes in on a specified location in a strand of DNA. The process then edits the DNA to either remove unwanted sequences or insert payload sequences. CRISPRs use an RNA molecule as a guide to the DNA target. To set up a CRISPR editing capability, a lab only needs to order an RNA fragment and purchase off-the-shelf chemicals and enzymes, costing only a few dollars.

    Because CRISPR is cheap and easy to use, it has both revolutionized and democratized genetic research. Thousands of labs all over the world are experimenting with CRISPR-based editing projects. There are few regulations worldwide, even in the United States, largely because regulators don’t understand what has become possible. China has taken the lead because it puts scientific progress ahead of all concerns. It has made the most astonishing breakthroughs.

    In 2014, Chinese scientists announced they had successfully produced monkeys that had been genetically modified at the embryonic stage. In April 2015, another group of researchers in China published a paper detailing the first ever effort to edit the genes of a human embryo. The attempt failed, but it shocked the world: this wasn’t supposed to happen so soon. And then, in April 2016, yet another group of Chinese researchers reported it had succeeded in modifying the genome of a human embryo in an effort to make it resistant to HIV infection.

    The intentions may be good, but this has transgressed a serious boundary. We know too little to predict the broader effects of altering or disabling a gene. In the 1960s, we imagined rather naïvely that as time went by we would understand with increasing precision the role of each gene in making us what we are. The foundation of genetics for decades, once biology’s Central Dogma, was the hypothesis that each gene codes for a single protein. Knowing the correspondences, we would have tools useful not only for research but also for curing and preventing disease with a genetic basis and perhaps for augmenting human evolution.

    The one-gene-one-protein Central Dogma, though it continues to pervade our common beliefs about genetics, underwent conversion when scientists realized many proteins comprise several polypeptides, each of which was coded for by a gene. The Dogma therefore became one gene, one polypeptide. But what sounded the entire Dogma’s death knell was the discovery in the early 1970s that a single gene can code for more than one protein. The discovery that the human genome contains only about 30,000 genes to code for some 90,000 proteins brought that home; but what makes our understanding appear spectacularly inadequate is the discovery in 2000 that a single gene can potentially code for tens of thousands of proteins.

    In a nutshell, we don’t know the limits of the new technologies, can’t guess what lifetime effects a single gene alteration will have on a single individual, and have no idea what effects alteration of genes in sperm or ova or a fetus will have on future generations. For these reasons, we have no knowledge of whether a particular modification of the human germline will be ultimately catastrophic, and no basis for considering that tampering with heritable genes can be humane or ethical.

    With an awareness of our ignorance in this area, the 2015 announcement of genetic modification of a human embryo led to global debate, and a handful of governments temporarily banned gene editing of live human embryos as well as the genetic modifications of the human germline (the DNA that will create future generations) for imparting beneficial traits such as height or intelligence. But in February 2017, an advisory body from the National Academy of Sciences announced its support for using CRISPR to edit the genes of embryos to remove DNA sequences that cause serious heritable diseases. And the Chinese are clearly proceeding with experimentation too, as the announcement by Shenzhen researchers showed.

    The reality is that we have arrived at a Rubicon. Humans are on the verge of finally being able to modify their own evolution. The question is, can we use this newfound superpower in a responsible way that will benefit the planet and its people — or will this be a race for scientific glory and profit?

    This article is partly derived from my bookThe Driver in the Driverless Car: How Our Technology Choices Will Create the Future.

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    Achronix Assists Academics

    Achronix Assists Academics
    by Tom Simon on 11-28-2018 at 7:00 am
    Categories: Achronix, AI, eFPGA, FPGA

    In every semiconductor related field, innovation is the name of the game. Academic, non-profit and government research has been a consistent source of innovation. Look back at the US space program, basic science research and even military programs to see where much of the foundation of our current technological age came from. Indeed, you might not be sitting in front of your computer on the internet now, had it not been for ARPA’s work in developing internet hardware and protocols. Fortunately, there is a long tradition of leading technology companies helping facilitate advanced research.

    Achronix, a company with a potentially game changing product for embeddable FPGA fabric, just announced a program to give access for their technology to academic and research entities. Their Research eFPGA Accelerator Program will allow researchers to use preconfigured Speedcore eFPGA IP for their research projects. While a commercial company would probably want a fully configurable and optimized Speedcore block, researchers can work with preconfigured blocks. This helps Achronix by lowering support costs and allowing the process run more quickly.

    I recently spoke to Steve Mensor, VP of Marketing at Achronix, about this program to better understand what they want to accomplish. He said that because embeddable FPGA is new, there are lot of interesting problems that it can solve. He sees this program as a win-win. Achronix can learn from new usage scenarios that researchers devise, at the same time researchers benefit from being able to apply new technology. He is hoping that this program leads to many new ideas.

    It’s also safe to say that once students and researchers learn how eFPGA and the tools used in the flow work, down the road they may find other new applications, either academic or potentially even commercial. Steve says that this will be a big benefit to users that have low volumes and could not afford the cost of developing new instances. Using preconfigured IP is cost effective for everyone involved, and there is no real penalty in area – due to the low volumes.

    Achronix will supply fully qualified and characterized, silicon proven blocks on TSMC 16 FF+. They anticipate that AI/ML will be a big application area. eFPGA offers low latency, programmability and acceleration of parallel processing for AI/ML designs.

    In addition to purely academic users, Achronix also has announced a program called the Test-Chip eFPGA Accelerator Program will help startups and small companies, and others, by making it easy to try out new architectures in silicon that use eFPGA fabrics. This program will let companies produce evaluation volumes of SOCs that use their eFPGA fabric. Just like the academic program, it will use pre-verified silicon blocks on TSMC 16 FF+.

    Steve is betting that once institutions and companies try out eFPGA and their ACE tool set, they will see significant benefits. In the case of commercial users, this creates a lower cost and safe means to start building products with eFPGA. The Achronix website has full details on how to participate in both of these new programs.