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IEDM 2017 – Controlling Threshold Voltage with Work Function Metals

IEDM 2017 – Controlling Threshold Voltage with Work Function Metals
by Scotten Jones on 01-26-2018 at 7:00 am
Categories: FinFET, Foundries, TechInsights
6 Comments

As I have said many times, IEDM is one of the premier conferences for semiconductor technology. On Sunday before the formal conference started I took the “Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS” short course. The second module in the course was “Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture” taught by Steven Hung of Applied Materials. This excellent module was particularly timely because GLOBALFOUNDRIES and Intel gave papers on their 7nm and 10nm processes at IEDM and both processes use work function metals to control threshold voltages. In this article I will discuss this emerging process technology.

Introduction
Simply put, the threshold voltage (Vt) of a MOSFET is the voltage that is required to turn the transistor on. As optimization of power and performance have become increasingly important for mobile devices, the number of different threshold voltages available on a process have proliferated. Where one or two threshold voltages were once typical, today we are seeing four or even five threshold voltages. Multiple threshold voltages allow designers to select the best option for each section of a design trading-off power and performance.

Setting Threshold Voltage (Vt)
The Vt of a MOSFET is determined by:

  • Interface charges – because interface charges can vary over time due to traps charging and discharging, it is generally desirable to minimize interface charges and they are not used to “tune” the threshold voltage.
  • Gate dielectric (oxide) thickness – Vt varies with gate oxide thickness with Vt being reduced for thinner oxides, see figure 1. For current foundry processes, it is common to have two oxide thicknesses and sometimes three. A thinner oxide may be used in the core for low Vt – high performance transistors and a thicker oxide may be used in the I/O area to support higher voltages.

 


Figure 1. Threshold voltage versus oxide thickness at a fixed channel doping level.
  • Channel doping – for many years the main method of producing multiple Vts on the same process has been to use masked implants to dope selected channel regions. Figure 2 illustrates Vt versus channel doping. There are two main issues with channel doping to set Vts. The first is that doping the channel reduces mobility and performance. Secondly, at very small dimensions there are only a few dopant atoms in the channels and small changes in the number of dopants referred to as random dopant fluctuations (RDF) can lead to variations in Vt.


Figure 2. Threshold voltage versus channel doping at a fixed oxide thickness.

 

  • Work function – since the transition to high-k gate oxides occurred, metal gate electrodes have been used to avoid the polysilicon depletion effect. The high-k metal gate (HKMG) process typically has two types of gate electrode metal stacks, one for the pFET and one for the nFET. The dual work function metals (WFM) is part of optimizing the nFET and pFET Vts. Now we are seeing more than two WFM used to “tune” Vt. With the advent of the foundry 7nm processes (Intel 10nm process) we are seeing multiple WFMs used to tune Vts with no channel doping. This approach improves mobility in the channel and therefore performance and avoids RDF.


High-k Metal Gates
In the early days of HKMG there were two approaches, gate-first and replacement metal gate (RMG). In gate first the HKMG is formed before the transistor implants, anneals and raised source/drains. The problem with this process is that the HKMG structure must stand up to a lot of high temperature processing and achieving optimal Vts is very difficult. RMG has now become the standard HKMG process.

In an early version of RMG, an interfacial oxide, high-k gate oxide and capping layer are deposited and then covered with a sacrificial polysilicon layer. The transistor implants, anneals and raised source/drains are performed. The sacrificial polysilicon is then etched out and gate WFM are deposited. This avoids the WFMs seeing a lot of high temperatures. In the current versions of this process an interfacial oxide is grown, sacrificial polysilicon is deposited and then the transistor is formed. The sacrificial polysilicon is etched-out, the surface is cleaned and then the interfacial oxide, high-k oxide, capping titanium nitride (TiN) layer and second sacrificial polysilicon layers are deposited. An anneal of the high-k oxide is preformed and the second sacrificial polysilicon layers is etched away. The WFM is now deposited. This method avoids having the high-k oxide exposed to all the high temperature transistor formation process steps.

Two Work Function Metals
For many years the standard WFM process has been to create an n and a p WFM.

The basic process is (does not include second sacrificial polysilicon deposition, anneal and removal), see also figure 3:

  • Form interfacial oxide
  • Deposit high-k gate oxide
  • Deposit TiN cap layer
  • Deposit tantalum nitride (TaN) etch stop layer
  • Deposit TN work function layer
  • Mask and etch TiN off of nFET
  • Deposit titanium aluminum carbon (TiAlC) work function layer
  • Deposit TiN barrier
  • Deposit tungsten (W) fill
  • Planarise

Figure 3. Dual work function metals.

It should be noted that although this stack is shown flat for illustrative purposes, the films are deposited into a trench.

Four Work Function Metals
At 10nm TSMC implemented the first four WFM approach I have seen. In the process outlined below the net result is two nFET WFM stacks and two pFET WFM stacks. This would achieve two Vts and I believe channel doping is used to achieve additional Vts. Possibly there would be one nFET and one pFET with undoped channels for maximum performance and then perhaps three additional Vts with doping.

The basic process is (does not include second sacrificial polysilicon deposition, anneal and removal), see also figure 4:

  • Form interfacial oxide
  • Deposit high-k gate oxide
  • Deposit TiN cap layer
  • Deposit tantalum nitride (TaN) etch stop layer
  • Deposit TN work function layer
  • Mask and etch TiN off of everything but the high Vt pFET
  • Deposit second TaN layer
  • Mask and etch TaN2 off of the low Vt nFET and high Vt pFET
  • Deposit TiAlC work function layer
  • Mask and etch TiAlC off of the low Vt pFET
  • Deposit TiN barrier
  • Deposit tungsten (W) fill
  • Planarise

Figure 4. Four work function metals.

This process flow was developed after examining cross sections of 10nm TSMC process provided by TechInsights.

If only two Vts are required, this 4 WFM process will meet that requirement. If channel doping is acceptable, then implants may be used to provide additional Vts.

For the Intel 10nm process (similar to foundry 7nm) Intel has a base process with 2 Vts achieved with 4 WFMs and an optional 3 Vt process achieved with 6 WFMs. GLOBALFOUNDRIES 7nm process has 4 Vts achieved with 8 WFMs. These processes are not available for analysis yet and we don’t know how these 6 and 8 WFM stacks are achieved. In the next section I will discuss some of the options.

Multiple Work Function Metal Options
Multiple work function can be achieved by simply using different metals that have different work functions, but there are a limited number of suitable metals.

In the “Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture: module of the short course I took, three ways of modifying work functions were discussed:
[LIST=1]

  • Thickness modification – changing the thickness of work function metals layers changes the work function. This allows changes in the Vt over a wide range but requires multiple depositions, masks and etches and very tight thickness control. This technique results in stacks of different thicknesses and may be difficult to implement for gate-all-around.
  • Material modification – this technique introduces or removes species such as oxygen to change Vt. This technique has less range of values than thickness modification and is most effective when the layers are closer to the high-k gate oxide. This technique does not result in different thickness for each WFM stack. One technique that has been investigated for material modification is implanting nitrogen into the WFM, the concern with this technique is the implanted ions may knock metal atoms from the WFM into the high-k gate oxide.
  • Electrostatic dipole – certain elements can introduce a dipole into the high-k gate oxide, for example elements such a lanthanum (La). Dipole formation with La and aluminum (Al) was used by the IBM/GLOBALFOUNDRIES/Samsung alliance as part of their WFM scheme for their gate first process at 28nm. This technique offers a broad range of Vts but needs very good thickness control of the deposited dipole materials and thermal drive in.Conclusion
    The transition to fully undoped channels with WFM Vt control is underway. TSMC has implemented 4 WFM at 10nm, Intel ‘s 10nm (similar to foundry 7nm) will feature 4 and 6 WFM options and GLOBALFOUDNRIES 7nm will have 8 WFM. We don’t yet know how this many WFMs will be achieved but likely it will be a combination of the techniques outline in the preceding section.The change to undoped channels should improve performance and reduce Vt variations enabling lower voltage operation for lower power.

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Wanted by January 30th: Paper for DAC IP Track 2018!

Wanted by January 30th: Paper for DAC IP Track 2018!
by Eric Esteve on 01-25-2018 at 12:00 pm
Categories: Events, IP, IPnest, Semiconductor Services

DAC 2018 will take place in San Francisco in June (24 to 28) and you have a fantastic opportunity to present a paper in the IP track! In fact, the deadline has been extended to January 30[SUP]th[/SUP] to submit your proposal.

Let’s make it clear: you are not expected to send the completed paper by this date, just the following:

  • The title of the presentation
  • Abstract of 100 words
  • Category (a list is provided at the bottom)
  • Topic Area (a list will be provided)
  • Presenter(s) name, affiliation, city, state, country, and email address
  • Upload 6 slides max PowerPoint presentation (extra note is optional but preferred)

If you are not familiar with the DAC IP track, here is a summary extracted from the DAC web site:

The IP Trackis targeted specifically at practitioners. Whether you are an hardware designer, IP provider, IP core user, application engineer or verification IP user, the IP Track is an ideal place to meet and share your experiences.

This year, IP Track will include presentations, poster sessions and a rich set of invited talks/panels to facilitate information exchange and interactions. It offers a unique opportunity to network with and learn from other industry experts about best practices and current trends. There is no better way to improve your “IP IQ” in such a short amount of time.

DAC IP Track is looking for presentation and poster submissions with timely topics and high-quality contents targeting challenges, innovations and trends in IP architecture, design, integration, reuse, ecosystem, and verification IP. This includes the unique application requirements and challenges for advanced technologies, automotive, security, Machine Learning, and the Internet of Things.

Presenting a paper, especially in a highly visible conference like DAC, is a great opportunity and I tell you why. If you are part of a small to medium company involved in IP design or IP verification, one of the most challenging task is to get access to your customers. These may simply don’t know about your product or your company but would need the type of IP you are designing.

Obviously, you can invest into marcom, invest into booths, write white paper and more. But if you can also spend one day or less and write about the design or verification of your IP product and submit your proposal, this effort may be rewarded (assuming your paper is selected). You and your company will benefit from the high visibility of such a conference, and may reach people who could become new customers. Don’t forget that the paper will be listed on the DAC website, so even people who don’t physically attend to your presentation will become aware of you and your product!

But, please, don’t send pure marketing material, it would be rejected. The DAC IP track list a few conditions that your paper will have to fulfill:

· Accepted IP Track submissions (both posters and presentation slides) will be made available on the DAC website after the conference as a part of the DAC Archives.
· IP Track submission will be accepted as a 15 minute presentation or presented as a poster in a 90 minute group session.
· A good IP Track presentation addresses innovative solutions with high-quality results. The considerations used by the program committee in acceptance decisions include:oSignificance of results supported by clear, measurable criteria, including, but not limited to: improved quality of silicon, decreased complexity, and reduced time-to-market.

oAbility to overcome design challenges such as scalability and integrating IP.

oValidation of the proposed techniques using real designs, case studies, or established benchmarks.

oA good IP track presentation inspires vision and healthy discussion for advancing the design and IP community.

oQuality of material including writing, illustrations, and organization.

oProduct marketing material is inappropriate for the IP Track.

Best Paper Award, Best Poster Award: your paper or poster can be selected to get the best paper (best poster) award. In this case, you will be notified before the conference that you are in the short-list. I can tell you from experience that it’s always a great emotion when you receive this notification! But only one paper and one poster will receive the award…

Are you ready to jumpstart and write an IP focused paper?

Go to this “IP Track Presentation Submissions”

From Eric Esteve from IPnest

Category List:
·IP.01 IP Provider CPU / GPU / DSP
·IP.02 IP Provider Memory Controller / NOC
·IP.03 IP Provider Communications IP
·IP.04 IP Provider Analog / PHY / High speed interfaces
·IP.05 IP Provider Embedded Software
·IP.06 IP Provider Configurable IP / IP Compilers
·IP.07 IP sub-systems / Multi-discipline IP / Programmable logic IP
·IP.08 IP optimized for emerging markets and applications such as Automotive, IoT, Mobility, Networking, Cloud, Security, Resilience, Etc.
·IP.09 IP Management / Assembly / Strategy / Roadmap
·IP.10 IP Verification / Validation

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Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench
by Bernard Murphy on 01-25-2018 at 7:00 am
Categories: Arm, EDA, Synopsys

There seems to be a general sense that we have the foundations for block/IP verification more or less under control, thanks to UVM standardizing infrastructure for directed and constrained-random testing, along with class libraries providing building blocks to simplify verification reuse, build sequence tests, verify register behavior and more. Not that this is trivial; UVM is still a complex animal requiring a lot of training and learning on the job. There continue to be debates about features and extensions: what should be standardized and what should be left to vendor solutions for example. Evolution naturally, but along a fairly clear path.


REGISTER HERE for the Webinar, on January 31[SUP]st[/SUP] at 10am Pacific

The same claim couldn’t be made for SoC and subsystem-level verification, at least until relatively recently. You’re still going to build testbenches using the UVM standard, but a bunch of what UVM offers for block-level verification is less useful at the system-level; for example, constrained-random is a hopeless approach to effective system-level testing. There are other important areas to optimize also, among which getting to a working testbench is the most obvious barrier to starting system-level verification.

At the SoC level, testbenches are much more than a stimulus/monitor/cover shell around a DUT: configuring the design, swapping IPs for VIPs with their transactors, assertions and covers for protocol verification (across the many protocols common in an SoC), along with adding hooks for validating against verification plans, adding performance testing, stress testing and coherency testing. When you consider also that many of these IP come from different sources, with different verification assets, assembling these testbenches is a complex and time-consuming task, often taking days to weeks to get to first effective verification.

But it doesn’t have to be that way. Synopsys’ VC AutoTestbench can assemble an SoC testbench in hours. This will import the DUT description, select and configure VIP, instantiate and connect these within the DUT and build out the test environment. They have this down to a pretty simple 5 step process. DUT and VIPs are read in and configured as IP-XACT, clock, reset and ad-hoc signals can be configured automatically and a testbench drops out. None of this requires protocol expertise or even UVM expertise. You’re up, simulating, and debugging in Verdi in hours rather than weeks. That sounds like a real-time saver.

REGISTER HERE for the Webinar, on January 31[SUP]st[/SUP] at 10am Pacific

Webinar Abstract
Today’s highly complex SoCs typically include multiple embedded processors, a memory subsystem, several interfaces to standard and custom protocols and a sophisticated interconnect architecture. These designs come together from IPs to subsystems to the full SoC, with system-level verification typically done late in the project cycle. Current verification environments don’t scale well from the IP- to SoC-level, are effort-intensive and time-consuming to build, and inherently error-prone. Due to time-to-market pressures, system-level verification to functionally verify the numerous system configurations is often insufficient and incomplete. Hence, there is a pressing need for automation in SoC verification, starting from testbench generation and bring-up.
In this Synopsys webinar, we will discuss how to reduce the time-to-first-test from weeks to hours by automating the process of testbench generation with Synopsys VC AutoTestbench. We will also include a demo of this flow using a real-world design and Synopsys AMBA VIP. Specifically, you will learn:

  • How to quickly and easily generate a complete SystemVerilog/UVM verification environment
  • How to efficiently reuse SoC-level testbenches for IP & interconnect verification
  • How to bring-up the auto-generated testbench and run tests from the Synopsys AMBA VIP test suites

Speakers:

Vaishnav Gorur
Product Marketing Manager – Verification Group
Synopsys

Vaishnav Gorur is currently Staff Product Marketing Manager for Debug & SoC Verification Automation products in the Verification Group at Synopsys. He has over 12 years of experience in the semiconductor and EDA industry, with roles spanning IC Design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and an M.B.A. from University of California, Berkeley.


Satyapriya Archarya
Senior Manager – Applications Engineering – Verification Group
Synopsys

Satyapriya Acharya is a Senior AE Manager at Synopsys, where he manages the use of Synopsys Verification IP for ARM AMBA protocols with several key customers. He has been involved in the development, verification and deployment of Synopsys Verification IP for the AMBA 3, AMBA 4 and AMBA 5 specifications. He has over 15 years on experience in design and verification.

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Designing an SoC for 3D TV Without using the Funny Glasses

Designing an SoC for 3D TV Without using the Funny Glasses
by Daniel Payne on 01-24-2018 at 12:00 pm
Categories: EDA, Siemens EDA

In the blur of activities at DAC last year I visited the Mentor booth a few times and had just a few minutes to glance at a 3D TV display that didn’t require me to wear any funny glasses, kind of novel I thought at the time because I’ve read that the market of 3D TV sets is being hampered by requiring viewers to wear glasses. The design team responsible for implementing an SoC for 3D TV without the use of glasses is called StreamTV Network, and they just described their journey in a white paper. So, what kind of 3D are we talking about here?

Well, these graphical gurus at StreamTV have figured out how to take the existing 2D video content and then add their Ultra-D technology layer on top of that, all in real time using their secret sauce (i.e. proprietary real-time algorithms). The team decided to go ahead and create a proof of concept SoC, even before they knew critical requirements like:

  • Silicon process node
  • Interfaces
  • Protocols
  • Memory
  • Bandwidth

The engineers decided to take a High Level Synthesis (HLS) approach to create their proof of concept, and they used the Catapult HLS tool in the process. Inside of their SoC is a Real-Time Conversion (RTC) IP block that has a 2D depth estimation function that creates a depth map. Then the image and depth map get sent to the Ultra-D block to create a stereo depth map.

In the above diagram you can see two BW images, the depth maps where a whiter color means that the image is closer to the viewer and black means the image is farther away.

A conventional SoC design flow would have an algorithm design team coding in C++, then a digital design time manually coding in RTL with an error-prone and time consuming process of going from C++ into RTL code:

The StreamTV team heard about the HLS approach from an NVIDIA engineer and started talking with Mentor about the possibility of using Catapult, so they started out with a portion of C++ code as a sample. AEs from Mentor spent some time onsite to help push the C++ code through the Catapult tool and the StreamTV engineers could quickly simulate the RTL code from Catapult to verify that it was working OK. So the new flow was more automated than the conventional SoC design flow:

Some of the benefits in using an HLS flow include:

  • C++ is the golden source for the algorithm and digital design engineers
  • Only one language to be concerned with
  • Direct how hardware gets synthesized with HLS directives

For an FPGA prototype using Altera parts the RTL code will run at 150 MHz, while choosing a TSMC process node the RTL code is much faster at 450 MHz.

During the design process there is block-wise verification run where the algorithm engineers wrote C++ functions that are then re-used as a testbench for the RTL generated code, so no manual steps were involved to verify. With the C++ being the golden source then all team members have a single language: Software, SW test, Verification testbench, Hardware. Having a unified source helped get the product out quicker than older design flows with multiple abstraction layers and manual steps.

Did the SteamTV team learn their new HLS flow by simply reading the fine manuals? Not really, they instead relied on local AE support to get up to speed with Catapult by learning best practices and avoiding pitfalls along the way. These first-time HLS users reported that they reduced SoC development time by at least 50% compared to previous designs, and that a big plus was being able to make last-minute changes because the time to generate RTL code was so fast.

The team even kept track of how much manual RTL they had to write versus HLS-generated, then how that impacted their debugging time:

What surprised me was to see that with only 5% of their design using manual RTL coding that the debug time for that code was disproportionately large at 80% of all debug time. Learning to place HLS directives created 3X more bugs at 15% of the total debug time compared to just learning how to code HLS at 5% of the debug time.

Once the StreamTV engineers learned the new HLS flow and did their first project they are not returning to their former flow again. The Catapult technology proved itself quite capable for these video challenges in 3D TV.

To read the complete 10 page White Paper click here.

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Context is Everything – especially for autonomous vehicle IP

Context is Everything – especially for autonomous vehicle IP
by Tom Simon on 01-24-2018 at 7:00 am
Categories: Automotive, IP, Silicon Creations

GM has just announced that it will introduce a car with no steering wheel or pedals in 2019. According to their statement, they have already planned four phases of their autonomous driving system, and they will plan many more. However, before we jump into this latest car and not grab the wheel for a spin, it is reasonable to ask about the reliability of the driverless electronics.

However, to put the safety of automotive automation in perspective we should look at the safety of how cars operate today. The largest single cause of automobile accidents is distracted driving. A related statistic is that one third of all accidents involve straying from the driving lane. Autonomous driving systems will be hands down better at sustained vigilance than humans. Indeed, this is the impetus for self-driving cars – we won’t have to try to focus on driving during our trips, and can be as distracted as we wish. I for one look forward to this.

The lingering question is how well will these systems operate. Advances in AI have helped improve the software element of these systems. As software quality improves, it reveals system hardware as the next area of focus. As I have written before, there are standards to help ensure reliability. The two main standards of interest are ISO26262 and AEC-Q100. Anyone building a system or a chip intended for automotive use needs to be thoroughly acquainted with both of these standards.

Safety in these systems relies on the biggest and the smallest components. Each need to be designed and assessed with the ultimate application in mind. One of the most poignant examples of how a very small but important component can lead to system failure is the Challenger explosion in 1986. In that case O-rings on the solid rocket booster were operated outside of their designed operation specifications, leading to catastrophic failure of the spacecraft and a loss of life.

Silicon Creations, a leading supplier of high performance analog IP, recently presented at the Reuse 2017 conference in Santa Clara on the topic of developing IP suitable for use in safety critical systems in automobiles. Andrew Cole, Silicon Creations’ VP, presented the session.

Andrew started off with a review of Silicon Creations, highlighting their strong growth since their founding in 2006. They have development groups in Krakow and Atlanta and their products span 180nm down to proven silicon at 7nm.

Because IP such as PLL’s and SerDes are ultimately used as part of larger designs, they cannot be certified by themselves. Andrew spoke about two fundamental concepts in automotive safety, Safety Element out of Context (SEooC) and Fault Time Tolerance Interval (FTTI). SEooC basically says that you must understand the use case for a sub-unit such as a PLL before you can properly assess its safety performance. To harken back to the Space Shuttle failure, we can see a similarity with the O-rings performance. They worked adequately for launches above 54 degrees, but at freezing temperatures they failed. The operating environment is an essential consideration when evaluating safety.

Once we are given a specific use case it is then possible to talk about failures and the allowable time to detect and correct them. Once again, without a use case we cannot really have a meaningful discussion of system level reliability. FTTI is concerned with system level design to detect failures and given the severity and criticality of the failure, how long the system can tolerate the malfunction, until it can be corrected. A failure in the entertainment system is nothing like a processor failure in the autonomous driving system. The former can wait for a visit to the dealer, the latter must be corrected or dealt with in fractions of a second.

The presentation, which can be downloaded from the Silicon Creations website, also discusses several design approaches and considerations for assuring system level certification of systems that use IP blocks such as their PLL’s and SerDes. Another topic he grapples with in the presentation is AEC-Q100 grading and testing. AEC-Q100 can be a sore point for products with small production volumes because it requires destructive testing of costly quantities of fabricated parts. Additionally, some care must be used when defining the mission profile for a chip, and its consequently incorporated IP.

The hope is that autonomous vehicles with lead to fewer accidents and improved safety. This cannot come about unless the entire supply chain is ready to step up and participate in a meaningful effort to meet and exceed safety standards. Silicon Creations is clearly making the effort and reaping favorable results. The slides used in Andrew’s talk can be found on their website. I highly recommend looking them over.

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TSMC 5nm and EUV Update 2018

TSMC 5nm and EUV Update 2018
by Daniel Nenni on 01-23-2018 at 12:00 pm
Categories: Foundries, Lithography, TSMC
4 Comments

The TSMC Q4 2017 earnings call transcript is up and I found it to be quite interesting for several reasons. First and foremost, this is the last call Chairman Dr. Morris Chang will participate in which signifies the end of a world changing era for me and the fabless semiconductor ecosystem, absolutely. TSMC announced his retirement with Mark Liu, who has been co-CEO along with C.C. Wei since 2013, replacing Morris as Chairman and C.C. Wei taking over the role of single CEO. Earnings calls were much more interesting when Morris Chang participated especially in the Q&A session when he questioned some of the questions. Here is his good-bye:

I really have spent many years with some of you, many years, more than 20 years. Although I think most of you probably haven’t attended this particular conference that long. But having here almost 30 years I think, yes. And I enjoyed it, and I think that we all — at least I hope that I had a good time. I hope that you had a good time, too. And I will miss you, and thank you very, very much. Thank you. Thank you. Thank you.

The call started out with Laura Ho and financial recaps but also revenue by technology:

10-nanometer process technology continues to ramp strongly, accounted for 25% of total wafer revenue in the fourth quarter. The combined 16/20 contribution was 20% of total wafer revenue. Advanced technologies, meaning 28-nanometer and below, accounted for 63% of total wafer revenue, up from 57% in the third quarter. On a full year basis, 10-nanometer contribution reached 10% of total wafer revenue in 2017. The combined 16 and 20 contribution was 25% of total wafer revenue. Advanced technology, 28-nanometer and below, accounted for 58% of total wafer revenue, up from 54% in 2016.

This really is good news for TSMC since the more mature nodes (40nm and above) are more competitive thus lower margined. It will be interesting to see when TSMC lowers that advanced node bar below 28/22nm, probably in two years when 7nm hits HVM and 5nm is ramping.

Laura ended her remarks with a solid Q1 guidance:

Based on the current business outlook, we expect first quarter revenue to be between USD 8.4 billion and USD 8.5 billion, which is an 8.3% sequential decline but a 12.6% year-over-year increase at the midpoint and represent a new record high in terms of first quarter revenue.

Mark Lui started his prepared remarks with an introduction to the TSMC “Everyone’s Foundry” strategy:

Firstly, I would like to talk about our “Everyone’s Foundry” strategy. Being everyone’s foundry is the strategy TSMC takes by heart. Through our technology and services, we build an Open Innovation Platform, where all innovators in the semiconductor industry can come to realize their innovation and bring their products to life. As our customers continue to innovate, they bring new requirements to us, and we need to continuously develop new capabilities to answer them. In the meantime, they utilize those shared capabilities such as yield improvement, design, utilities, foundation IPs and our large-scale and flexible capacities. In this way, this open innovation ecosystem expands its scale and its value. We do not compete with our customers. We are everyone’s foundry.

The translation here in Silicon Valley is that TSMC does not compete with customers or partners which is a direct shot at Samsung, my opinion. Mark also talked about the latest semiconductor killer app and that is cryptocurrency mining which is booming in China:

Now on cryptocurrency demand: In the past, TSMC’s open innovation ecosystem incubates numerous growth drivers for the semiconductor industry. In the ’90s, it was the PC chipsets; then in the early ’20s, the graphic processors; in the mid- to late ’20s, it was chipset for cellular phone; recently, start 2010, it was for smartphones. Those ways of innovation continuously sprout in our ecosystem and drive the growth of TSMC. Furthermore, we are quite certain that deep learning and blockchain technologies, which are the core technology of cryptocurrency mining, will lead to new waves of semiconductor innovation and demand for years to come.

Mark then switched to 5nm (N5) and EUV readiness. According to Mark, N5 is on track for Q1 2019 risk production which gives plenty of room for Apple to get 5nm SoCs out in time for 2020 Apple products. I have not heard any fake news about Apple switching foundries which is a nice change. TSMC and Apple are like peanut butter and jelly…

EUV is also progressing with high yields on N7+ and N5 development. Some customers have mentioned getting EUV at the contacts and vias at 7N before getting EUV for metals and shrink at 7N+ which makes complete sense to me.

Mark also mentions that EUV source power is at 160 watts for N7 with N5 development activities at 250 watt waiting in the wings. This all jives with what Scott Jones presented at ISS 2018 last week. Mark’s EUV pellicle comment however left me with a question:

EUV pellicle making has also been established with low defect level and good transmission properties. So we are confident that our EUV technology will be ready for high-volume production for N7+ in 2019 and N5 in 2020.

I’m curious to know what “good transmission properties” are. From what I am told they need to be 90%+ but they are currently in the low 80% range. Does else anybody know? Can someone share their pellicle wisdom here? The other EUV question I have is about the 10% performance and density gain between 7N and 7N+. Is that EUV related or just additional process optimization? I will be in Hsinchu next week so I can follow-up after that.

All-in-all it really was a good call, you can read the full transcript HERE.

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Simulation and Formal – Finding the Right Balance

Simulation and Formal – Finding the Right Balance
by Bernard Murphy on 01-23-2018 at 7:00 am
Categories: Arm, Cadence, EDA

Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation. Formal excels at finding problems in shallow but very broad state graphs and avoids a good deal of the overhead in testbench setup, while simulation has the advantage over formal in deep sequential problems, mixed-level (AMS, SystemC) and asynchronous behavior modeling. Unsurprisingly, many verification teams already use both to maximize signoff quality and throughput.


The trick is finding the right balance. Sticking to simulation may be easy but that doesn’t help if it takes you longer to get to signoff than your competitors or if that signoff still misses important problems. Equally an over-enthusiastic view of how widely you can use formal may get you bogged down in tangled abstractions and constraints with an unclear view of what you really have or have not signed-off at the end of it all. Fortunately, a lot of experience has grown up around this topic; Infineon and one of the Cadence IP teams shared their experiences at CDNLive and Jasper User Group events. Also, Marvell added some important input on optimizing simulation turn-times.

Based on their CDNLive presentation, I would characterize this Infineon team as cautious mid-range users in the world of formal; neither pushing the envelope in complex system verification or heavy usage, nor at the very early stages of adoption. They are using formal to look for corner cases in ~10-20% of test-cases then re-testing those in simulation, and using formal standalone (no simulation backup) in ~5-10% of cases. They start with a common split between blocks:

  • Formal-friendly: low sequential depth, control, data transfer, simpler data transform and concurrent blocks of these types. Interesting to note, per Pete Hardee (product management director at Cadence) that the simpler datapath blocks (think CSA) are starting to appear in the formal-friendly set.
  • Formal-unfriendly: high number of state elements, high sequential depth, complex datapath elements (think Wallace-tree)

Infineon made use of a number of pre-packaged apps in JasperGold, including the connectivity app and the control and status register app. They also created some of their own properties for specialized checks, especially at IP boundaries. Infineon put a lot of work into determining coverage from these proofs which they then merged with simulation coverage, both to confirm the correctness of their split between formal and simulation and to discover where they could reduce simulation effort in coverage. Quite interesting – take a look at how they scaled back effort in their UVM development after examining what they felt was already well-proven around register-file testing.


The Cadence IP group also uses formal verification and their input is in some ways even more revealing. They have to optimize to their business goals independent of tools teams and they have to satisfy a very wide range of potential use models. Interestingly, the team that presented acknowledged initially an even more cautious view of formal, seeing it as a specialized capability playing no major role in serious signoff (sound familiar?). They chose to step up to more active usage on a CCIX block (a new standard for chip-to-chip cache coherence messaging), where they ran simulation and formal methods in parallel.


A big goal again was to get meaningful coverage from formal and to this end the IP group used several approaches:

  • Classic formal coverage based on full and bounded proofs, with coverage analyzed using proof-core methods. They view this as valuable for finding bugs but not primary for signoff
  • Something Cadence calls state-swarm where the search for bugs is driven by end-to-end properties, but is guided by multiple cover-points along the way, in what amounts to a random walk (they view this as somewhat like to a constrained random analysis). This was the IP group’s main signoff criterion, for me a variant on the proof-depth cover-point approach.
  • Guide-pointing which is similar to state-swarm except that proving must hit the cover-points in order (this is more like a formal variant on directed testing)

The second and third cases here are ways to reach out beyond conventional formal cycle-depth limits in what is generally known as bug-hunting, not usually considered a contributor to formal coverage, but it seems like the IP group are confident these methods are sufficiently structured that they can be an effective contributor.

Meanwhile, while verification teams look for ways to offload work for simulation, what remains for simulation gets harder. Marvell talked at the same event about the turnaround time challenge in simply compiling and elaborating designs now running to a billion gates (you read that right – a billion gates in simulation). Even for simulation, that can run to many hours. When you’re tweaking a design, you really want to make this as incremental as possible to minimize major down-times between runs. Making compile incremental is easy – you can do that with Makefile-like methods. But incremental elaboration isn’t so easy; that’s where you’re flattening the netlist and optimizing for simulation performance, which tends to be a chip-wide operation.

Cadence now supports, in its Xcelium Parallel Logic Simulation, a technique it calls Multi-Snapshot Incremental Elaboration (MSIE), which allows for user control of partitions in elaboration to enable reuse from earlier elaborations (replace only partitions that have changed). Bottom line, Marvell reported improvements of 30-100X in TAT over monolithic compile/elaboration run-times. Adam Sherer (product management group director at Cadence) also noted that Xcelium is now supported on ARM servers, which means that massive simulation workloads can be pushed into datacenters hosting tens of thousands of ARM cores in dense new server-architectures.

Back to the balance. Simulation is still the main workhorse, especially for huge designs and giant workloads. Formal adds a first-class complement to that effort, contributing not just in proving and bug hunting but also in coverage, relieving simulation of some important components of signoff. Speakers at the conference also noted that where simulation and formal were run side-by-side, formal found some problems not found by simulation, and vice-versa. Both add to a higher quality result, as long as you get the balance right.

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How many engineers does it take to get an IoT security certificate?

How many engineers does it take to get an IoT security certificate?
by Diya Soubra on 01-22-2018 at 12:00 pm
Categories: IoT, Security

Spoiler alert, the answer is none!

Let me take you back to the beginning to explain that answer.

For the sake of this discussion, I will reduce a complex IoT solution to three fundamental blocks:

  • IoT node
  • IoT Gateway
  • IoT Server

The IoT node is a sensor that converts analog, physical world context into digital data. The node has to have a processor to run an IoT protocol stack and a radio to connect to the network. The technology for building nodes is abundant. Every week there is a release of best-in-class devices such as this one:

For the radio part, in-between LoRa, SigFox and NB-IoT, system designers have a wide choice to fit each specific vertical application. SigFox seems to be so successful that it has to be attacked with fake news to slow it down.

There is also an abundance of IoT node stacks. Choice is always a good thing to have as a vibrant ecosystem is essential in any industry:

Express Logic’s X-Ware IoT Platform™ to Bring Industrial Grade Connectivity to Thread® Networked Devices

Amazon Free RTOS

ARM Mbed

ARM Coretex-A7 based industrial IoT Gateway From Cascademic Solutions

The conclusion so far is that we have the technology to build and connect a trillion end points in a cost efficient manner.

Moving up, the IoT Gateway benefits from the economy of scale of mobile phones. The same devices used in mobile phones are fit for purpose for gateways. Raspberry Pi copycat boards are on the market for $9.

For gateways, the concern is about software and the ease of bringing web developers to integrate IoT nodes into their web infrastructure. The offer is abundant.

Universal IoT Gateway Middleware – Speed up IoT Development

Once we reach the server side we enter the well established domain of the cloud and cloud software where compute power and storage are infinite. True, we need a new service for IoT node management but that is an add-on to the cloud infrastructure, not a new one. Server software is about converting digital data into information to make decisions which is where the value resides.

Get started with Azure IoT Hub Device Management

IoT solution providers are abundant too. They do magic to pull together all these building blocks into a coherent end to end solution.

KILKA-TECH Portfolio

IOTA Data Marketplace

Smart Energy

Even the subject that I have been ranting about for a long time seems to be en route to be resolved, the IoT Data Market place that removes the need for data brokers. This is the ultimate goal for IoT, automatic node to node contracts on the fly.

At this point we should all be feeling very warm and fuzzy. We have solved all the issues blocking the deployment of billions of nodes. right? Yes, except for the question relating to liability in case of a security breach.

Arm took the initiative to highlight this to the industry by issuing a security manifestoand by releasing a Platform Security Architecture.

For IoT, we are talking about thousands of companies and verticals. How does a company manage the liability from a security breach across millions of nodes? Usually there is a set of industry specific regulations that one can certify a solution against and thus limit the liability in case of a hack.

Given the lack of governmental IoT security regulations then there is no certification possible hence the number of engineers required to certify an IoT node is zero. et voila!

Yes, I know, it took a while to get to this point.

In the past five years the industry has taken giant steps to supply all the building blocks required to release the value locked in IoT deployment, at scale. We are at the finish line with IoT security certification and regulations. Relativity tells us that time runs slower in political circles than in hi-tech. Eventually we will start to see regulations issued world wide for IoT security. Once the regulation is in place then we need to sort out the logistics of certification for a trillion nodes with firmware that changes over time. Meanwhile may be we should explore self certification in the spirit of the security manifesto!

Thousands of verticals with millions of nodes each, such exciting opportunities!

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Autonomous Automobile Update ISS 2018

Autonomous Automobile Update ISS 2018
by Daniel Nenni on 01-22-2018 at 7:00 am
Categories: ESD Alliance, Events
2 Comments

As a car enthusiast and a semiconductor professional the latest automotive trends are of great interest to me. My father raced sports cars and I remember being part of the pit crew (but not really) and impatiently waiting for my turn to drive. The years before my 16[SUP]th[/SUP] birthday when I could legally drive were the slowest in my life, definitely.

Today I am told that my grandchildren will not need to learn to drive thanks to autonomous cars and other forms of autonomous transportation which makes me happy but also sad that they will not have that level of responsibility. Driving really is a big part of life experience and I wonder how my grandchild will get along without it.

The question in my mind has always been not IF but WHEN we have fully autonomous cars on the road and that timeline in my head is getting much shorter. Technology is certainly moving forward but the big “driver” in California is traffic. When your average commuting speed is 10-20 miles per hour on Highway 101 the safety risks of autonomous driving are dramatically reduced. And quite possibly distracted driving will be replaced by tickets for sleeping while driving.

In Silicon Valley construction is still booming with both high density commercial and residential buildings but the one constant is the roads, they are not changing so our only hope is technology. Eliminating the human factor of transportation with autonomous cars above and below ground which will ultimately lead to a transportation system like the Hyperloop.

At ISS 2018 Dr. Maarten Sierhuis (Director of Nissan Research Center Silicon Valley for Nissan North) gave us an autonomous update which was quite interesting.

Maarten leads a team of researchers tasked with developing autonomous vehicles, connected vehicles, and Human-Machine Interaction and Interfaces to help shape the future of intelligent transportation. Previously Maarten spent 12 years at NASA where he created a computer language that was used to develop an intelligent system for all communication between Mission Control and the International Space Station. He also developed an autonomous system to monitor and give advice to astronauts during spacewalks.

Maarten’s slides were not made available but I did find a recent article on Wired.com “Nissan’s path to self-driving cars?” which is déjà vu of his presentation. In regards to city autonomous driving:

“There is so much cognition that you need here,” Sierhuis says. The driver—or the car—has to interpret the placement of the cones and the behavior of the human worker to understand that in this case, it’s OK to drive through a red light on the wrong side of the road. “This is not gonna happen in the next five to ten years.”

According to Maarten a human will need to be in the loop in a supervisory role which Nissan now calls “Seamless Autonomous Mobility”. Think call center for autonomous cars that may need human intervention or ONSTAR on steroids. Even better, think NASA and the supervision of autonomous and teleoperated satellites and vehicles since Maarten is from NASA.

Bottom line: From what I have read, there are close to 300 companies developing autonomous automotive technology so we will definitely get there. In China it will be mandated by the government. In California it will be mandated by the brutal gridlock and increasing highway fatalities due to human error/ignorance, absolutely.

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A New Year’s resolution: Turn off computers

A New Year’s resolution: Turn off computers
by Vivek Wadhwa on 01-20-2018 at 7:00 am
Categories: General
4 Comments

Facebook’s recent acknowledgment that social media may be making its users feel bad in some cases is a significant milestone. So far, the technology industry hardly has talked about the downsides of their products. Now a realization seems to be setting in that perhaps something has gone wrong along the way.

Academic research that Facebook cited in a corporate blog post documented that when people spend a lot of time passively consuming information they feel worse. For example, reading Facebook posts for even 10 minutes can put people in a bad mood, and clicking or liking too many links and posts can have a negative effect on mental health. Some researchers also believe that reading rosy stories about others leads to negative comparisons about one’s life and that being online too much reduces in-person socializing.

Social media may well be making many of us unhappy, jealous and anti-social.

While Facebook said that as a result of the assessments, it would make some changes to its platform (e.g. give people more control of what they see and help with suicide prevention), it also highlighted some of the benefits of using the social network. It pointed to research it helped conduct which concludes that “sharing messages, posts and comments with close friends and reminiscing about past interactions” can make people feel better. Facebook said it is working with sociologists and scientists to find ways to enhance “well-being through meaningful interactions” and more-active engagement.

“In sum, our research and other academic literature suggests that it’s about how you use social media that matters when it comes to your well-being,” Facebook said. It posits that if we engage or interact with others more on its platform, we will be happier.

But that approach doesn’t seem to be an effective solution for those who can’t pull themselves away from such platforms. The Pew Research Center estimates that 24 percent of teens go online “almost constantly,” for example. It is becoming a matter of addiction.

]In July 2016, former Google “design ethicist” Tristan Harris published the essay “A Slot Machine in Our Pocket,” which detailed the many ways in which technology affects people’s minds and makes them addicted. He drew a direct line of descent to phones and computer screens from the numerous techniques that slot-machine designers use to entice gamblers to sit for hours losing money.

These techniques are similar to the work of psychologist B.F. Skinner, who in the 1930s put rats in boxes and taught them to push levers to receive a food pellet. They would push the levers only when hungry, though. To get the rats to press the lever repeatedly, even when they did not need food, he gave them a pellet only some of the time, a concept now known as intermittent variable rewards.

The casinos took variable rewards to a new level, designing multiple forms of rewards into slot machines. Those machines now bring in the majority of casino profits. Players not only receive payouts at seemingly random intervals but also partial payouts that impart the feeling of a win even if the player in fact loses money overall on a turn.

These techniques entice humans to keep playing, because our brains are hard-wired to become addicted to variable rewards, as Skinner had found. And it is intermittent variable rewards that have us checking our smartphones for emails, new followers on Twitter or more likes on photographs we posted on Facebook.

The “bottomless bowl” of information we are served also leaves us always seeking more.

]Cornell University researcher Brian Wansink led a 2005 study that found that people who ate soup from bowls that had a tube in the bottom, which constantly refilled themselves, consumed 73 percent more than those who ate out of normal bowls. And they felt no more satiated. This is the effect Netflix has when it auto-plays the next episode of a show after a cliffhanger and you continue watching, thinking, “I can make up the sleep over the weekend.” And it is the effect that Facebook, Instagram and Twitter have in tacking on their scrolling pages and updating news feeds, causing each article to roll into the next.

This doesn’t seem to be a fair fight. The tech industry is constantly mining our data, using artificial intelligence to learn our habits and building tools to have us returning for more. We can turn off our applications, but some of us are subconsciously addicted to them.

So we need to be aware of what we are up against. Technology, when used correctly, can be wonderful. But perhaps the best solution is just to use technology in moderation.

Remember when we would just pick up the phone and call someone rather than emailing them and creating greater misunderstandings? This may be an old-fashioned choice, but the right one. And maybe we should just turn away from our screens sometimes and meet our friends and family in person.

This is based on my forthcoming book,Your Happiness Was Hacked: Why Tech Is Winning the Battle to Control Your Brain–and How to Fight Back. You can pre-order this now!