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More Negative Semiconductor News

More Negative Semiconductor News
by Robert Maire on 09-24-2018 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

The amount of negative news and information about the semiconductor industry seems to be increasing at a faster rate. Micron put up a better quarter than expected but more importantly guided less than expected. We are surprised that the street is surprised as the decline in memory pricing is well known and Micron has been clear about it. It seems like investors and analysts may not be paying attention or hoping that reality isn’t true. Even if Micron’s earnings get cut in half, its still trading at a low valuation. Investors seem to be pricing in a downside disaster.

There is also a report in the news that Samsung will cut back on memory production in 2019 in order to prop up pricing in the face of slowing demand. Demand is still up just not up as fast as expected. We have written several reports in the past about our “OMEC” (Organization of Memory Exporting Companies) idea and Samsung is the Saudi Arabia of the memory industry. It does have the power to prop up pricing by adjusting supply. It may not be a bad thing for memory makers not such much for memory users.

The problem is that if Samsung is planning on cutting memory supply growth in 2019 it obviously is also going to cut chip equipment purchases even further as there is not a reason to buy equipment to increase supplies further. This also belies the idea of a one quarter downturn, for the September quarter, that some equipment companies and analysts had stated as fact.

Our recent checks indicate that the December quarter for chip equipment is weaker than suggested last quarter and perhaps even weaker for fabrication equipment than the recent “walk back” by KLAC.

We think that the December quarter for LRCX, AMAT and TEL will likely be down, perhaps another 10% sequentially rather than the “positive trajectory” Lam had called for on their last conference call, which would have supported September as the trough quarter.

We are more firmly of the view that September is not the trough and that there is probably further downside from there. At this point we think its difficult to call the trough or bottom as the news flow continues to be negative.

LRCX back track?
We think that Lam will likely have to back track on their September trough comment. At best they may be able to pull business into December to make it look flatter but we think things have deteriorated since their last update. We have been suggesting that $150’s has been a “trough” for the stock but we could potentially break through that support level depending on the level of capitulation. The recent comments attributed to Samsung pulling back on supply add to the risk as they may make the September equipment delay become a cancellation.

Global Semiconductor Alliance Executive Forum
This past week when we were is silicon valley, the GSA held its executive forum of “C level” types from the chip industry. We have heard from several people that the tone and outlook at the conference was much more muted.
It sounds like the consensus is for chip growth to slow from its 20% prior pace to a more leisurely 0% to single digit % rates.

We don’t think this is as bad as some investors may react as memory has been at an unsustainable pace and the expectation is still positive rather than the historical cyclicality which goes more negative in down cycles.
Our sense is that most, if not all, of the cooling has been on the memory side of the industry with foundry/logic being relatively fine.

Monterey Masks
This past week also saw the SPIE photomask and EUV Lithography conference in Monterey. It sounds as if things are progressing very well on 7NM. We have heard that there are a lot of 7NM”tape outs” that will likely build a good backlog of leading edge product. EUV continues to make progress towards a more HVM like model though it still has the well know issues of resist & pelicles etc;.

Lasertec Mask Porn
We heard that Lasertec of Japan showed some racy EUV mask images at SPIE from their mask inspection tool. Mask inspection remains one of the aforementioned issues and it would appear that Lasertec continues to make progress on that front and has come out of “stealth mode” a bit by publicly demonstrating capabilities.

Seen on EBAY- “Two lightly used ASML 3400s, best offer, pick up only”
Now that GloFo has officially canceled their 7NM program there are some idle, hardly used 3400 ASML EUV scanner collecting dust in Malta. There is also a 3300 that was an early tool which is also turned off. It seems a shame to waste these tools and we assume they will find a new home elsewhere. Maybe someone in China will buy them to jump to the head of the line rather than wait for ASML to build a new tool.

This could potentially impact ASML’s delivery schedule or build schedule if they replace tools already in the build queue for another customer. This may reduce the EUV tool count in the near term.

Is Micron dropping out of EUV?
The 3 ASML tools at GloFo may not be the only EUV scanners available. We have heard that Micron may be dropping out of the EUV program and shutting down its ASML 3300. That would bring the number to 4 dead EUV tools.

This may further add to EUV questions but it shouldn’t. We are not surprised as we have never expected Micron to use EUV as memory makers just don’t need it and can’t cost justify it, not today anyway. It was likely a nice R&D program that Micron can shut down to save costs as memory pricing weakens. It just adds another tool to the used tool market. I wonder how much it costs to ship an EUV tool to China? Probably a lot as it takes a $10M crane just to load it into the fab.

The stocks
We don’t see a lot of positive news this past week that suggests a quick bounce back. We think the stocks remain under pressure and could see another down leg after reporting the September quarter. We don’t like being part of the “spear catching” competition in the market and continue to view the downside risk as much larger than the upside potential of most of the stocks.

We still think Micron is cheap and has gotten cheaper but don’t want to put new money to work fighting the tape. KLAC is probably the best defensive play in chip equipment especially after its correction.

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Neural Network Efficiency with Embedded FPGA’s

Neural Network Efficiency with Embedded FPGA’s
by Tom Dillinger on 09-21-2018 at 12:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP

The traditional metrics for evaluating IP are performance, power, and area, commonly abbreviated as PPA. Viewed independently, PPA measures can be difficult to assess. As an example, design constraints that are purely based on performance, without concern for the associated power dissipation and circuit area, are increasingly rare. There is a related set of characteristics of importance, especially given the increasing integration of SoC circuitry associated with deep neural networks (DNN) – namely, the implementation energy and area efficiency, usually represented as a performance per watt measure and a performance per area measure.

The DNN implementation options commonly considered are: a software-programmed (general purpose) microprocessor core, a programmed graphics processing unit (GPU), a field-programmable gate array, and a hard-wired logic block. In 2002, Broderson and Zhang from UC-Berkeley published a Technical Report that described the efficiency of different options, targeting digital signal processing algorithms. [1]

The figure below (from a related ISSCC presentation) highlights the energy efficiency of various implementations, with a specific focus on multiprocessing/multi-core and DSP architectures that were emerging at that time:

More recently, Microsoft published an assessment of the efficiency of implementation options for the unique workloads driving the need for “configurable” cloud services. [2] The cloud may provide unique compute resources for accelerating specific workloads, such as executing highly parallel algorithms and/or processing streaming data inputs. In this case, an FPGA option is also highlighted – the relative merits of an FPGA implementation are evident.

The conclusion presented by Microsoft is “specialization with FPGA’s is critical to the future cloud”. (FPGA’s are included in every Azure server, with a unique communication network interface that enables FPGA-to-FPGA messaging without CPU intervention, as depicted above.)

Back to DNN applications, the Architecture, Circuits, and Compilers Group at Harvard University recently presented their “SMIV” design at the recent Hot Chips Conference (link).

The purpose of this design tapeout was to provide hardware-based “PPA+E” metrics for deep neural network implementations, having integrated four major options:

 

  • a programmable ARM Cortex-A53 core
  • programmable accelerators
  • an embedded FPGA block
  • a hard-wired logic accelerator

The Harvard design included programmable accelerators, with a unique interface to the L2 memory cache across an ARM AXI4 interface, in support of specific (fine-grained) algorithms. The hard-wired logic pursued a “near-threshold” circuit implementation, with specific focus on optimizing the power efficiency.

The evaluation data from the Harvard team are summarized below, for representative Deep Neural Network “kernels”.

As with the Microsoft Azure conclusion, the efficiency results for the (embedded) FPGA option are extremely attractive.

I was intrigued by these results, and had the opportunity to ask Geoff Tate, Cheng Wang, and Abhijit Abhyankar of Flex Logix Technologies about their collaboration with the Harvard team. “Their design used a relatively small eFPGA array, with four eFLX tiles – two logic and two DSP-centric tiles.”, Geoff indicated. (For more details on the tile-based strategy for building eFPGA blocks, include the specific MAC functionality in the DSP tile, please refer to this earlier Semiwiki article – link.)

“The Harvard team tapeout used the original eFLX DSP tile design, where the MAC functionality is based on wide operators.”, Cheng indicated. Flex Logix has recently released an alternative tile design targeted for common neural network inference engines, with options for small coefficient bit widths (link).

“We are anticipating even greater efficiency with the use of embedded FPGA tiles specifically developed for AI applications. We are continuing to make engineering enhancements to engine and memory bandwidth tile features.”, Geoff forecasted.

Returning to the Harvard results above, although the PPA+E metrics for the attractive, a hard-wired ASIC-like approach is nonetheless still optimal for power efficiency (especially using a near-threshold library). What these figures don’t represent is an intangible characteristic – namely, flexibility of the deep neural network implementation. Inevitably, DNN algorithms for the inference engine are evolving for many applications, in pursuit of improved classification accuracy. In contrast to the eFPGA and processor core designs, a hard-wired logic network would not readily support the flexibility needed to make neural network changes to the depth and parameter set.

“Our customers consistently tell us that design flexibility associated with eFPGA DNN implementations is a critical requirement – that is part of our fundamental value proposition.”, Geoff highlighted.

The analysis data from the Harvard SMIV design contrasting processor, programmable logic, and hard-wired DNN implementations corroborates the high-level trends identified by Berkeley and Microsoft.

The traditional PPA (and licensing cost) criteria for evaluating IP needs to be expanded for the rapidly-evolving application space for a neural network inference engine, and must include (quantifiable) Efficiency and (more subjective)Flexibility. The capability to integrate embedded FPGA blocks into SoC’s offers a unique PPA+E+F combination – this promised to be an exciting technical area to track closely.

-chipguy

[1]Zhang, N., Broderson, R.W., “The cost of flexibility in systems on a chip design for signal processing applications.”, Technical Report, University of California-Berkeley, 2002.

[2]Putnam, A., “The Configurable Cloud — Accelerating Hyperscale Datacenter Services with FPGA’s”,2017 IEEE 33rd International Conference on Data Engineering (ICDE),
https://ieeexplore.ieee.org/document/7930129/ .

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Systems Design vs Integrated Circuit Design

Systems Design vs Integrated Circuit Design
by Daniel Nenni on 09-21-2018 at 7:00 am
Categories: Wally Rhines

This is the sixteenth in the series of “20 Questions with Wally Rhines”

Electronic design automation (EDA) began and grew with the integrated circuit (IC) design business probably because IC design grew in complexity faster than printed circuit boards. The race for superiority in PCB design evolved in parallel, however, and has become increasingly important as system design moves to more advanced EDA.

Daisy, Mentor and Valid, founded in 1980 and 1981, supported a combination of IC and PCB design. Both technologies required schematic capture and layout but simulation was primarily an IC design technology. Mentor and Daisy targeted both IC and PCB design while Valid specialized in PCB. At the same time, companies like Racal Redac (Europe), Cadence, SciCards (on VAX), Intergraph and others competed for the PCB market. As much as the IC market, competitive advantage in PCB design and layout (and eventually manufacturing) resulted from strategic acquisitions as well as organic technology development.


Computervision, Calma and Applicon were the “Big 3” electronic design environments that preceded the Daisy, Mentor, Valid era. But the GE acquisition of Calma, which had a very strong IC layout capability, demonstrated how large companies can easily mismanage the acquisition of fast moving, small, high tech companies, and the value of Calma was quickly lost. Daisy and Mentor went head to head and Mentor ultimately won the majority of the systems companies (and even owns the remnants of Daisy today through Mentor’s acquisition of Veribest from Intergraph), a historical event that gives Mentor its strength today in system design as systems companies (particularly aerospace, defense and automotive) rarely changed EDA suppliers, even as they adopted IC design tools to complement their PCB tools.

A critical shift occurred in the early 1990’s. Mentor’s PCB capability came from the acquisition of CADI. Cadence had acquired tools as well and both Zuken and Racal Redac had strong positions grown from organically developed tools. In 1990, Cadence and Mentor had approximately equal market shares, with Zuken and Racal Redac making up much of the remainder of the PCB market. Cadence made a very bold move, taking advantage of the fact that Mentor was in a period of weakness due to its struggles with Version 8.0. Cadence acquired Valid, announcing that the overlap between Cadence and Valid PCB design tools would be quickly resolved by eliminating the losers and crowning the winners. This turned out to be a difficult strategy since ALL of the users from both Cadence and Valid lost some portion of their design flow. That forced all the Cadence and Valid users into a competitive re-evaluation of all the alternatives. Zuken gained a little and Mentor gained a lot, while Cadence kept some. The result: By 1999, Mentor had 20% of the PCB market, Cadence 17% and Zuken, who had acquired Racal Redac to complement its Japan strength with a European supplier, had 16%. By this time, the dot com crash was beginning and Zuken reduced investment while Cadence focused on IC design. Mentor, who was still troubled by the Version 8.0 problems, continued a heavy rate of investment in “system design” including PCB, as an area of #1 market strength, and continued to gain market share in PCB, peaking at a market share of about double its nearest competitor.

Over the next two decades, all this history had an effect on strategic evolution. The original companies that needed to move toward EDA standardization in the 1980’s were largely systems companies. They needed standardization in design methodologies, libraries and tools across their disparate divisions. Even though two thirds of Mentor’s revenue ultimately came from IC design, the original adopters of EDA remained as a stable base of customers, particularly those who manufactured cars, planes and trains, or were involved in aerospace and defense. Mentor was able to capitalize upon that large market share and, thanks to some developments along the way, developed a leading position in electronic wiring and embedded software for those kinds of systems.

As much as anything, this systems capability is what made Mentor so attractive to Siemens’ software division as they looked to extend their “digital twin” platform from design, product life cycle management, mechanical CAD and manufacturing simulation to the electronic dimension of the digital twin.

There was another reason that Mentor’s system design businesses succeeded despite the difficulties of the Falcon Version 8.0 transition. Russ Henke, who managed the PCB business at that time, did not believe that Version 8.0 would ever work. So he followed a path, common in many companies, of quiet non-compliance. He instructed his PCB team to develop a “wrapper” to interface to Version 8.0, just in case it worked, and then proceeded to invest in the traditional PCB design business, consistently growing PCB revenue throughout the period of Version 8.0 chaos and into the 1990’s.

There was another beneficial offshoot of the Version 8.0 transition problems. The Mentor sales force had very little to sell after the announcement that Version 7.0 would not be extended but would be replaced by Version 8.0 whenever that environment became available. An innovative sales team working with the “Value Added Services” group sought out new users for the existing products that were not affected by the Version 8.0 transition. PCB schematic capture was one of those products. They found a local customer in Portland, Freightliner, who manufactured trucks and is now owned by Daimler. Convincing them to move from manual wiring design to EDA can’t have been easy but they became the first adopters of a “field-developed” product named “LCable”, a name that reflected its use in the design and verification of cabling and wire harnesses for trucks and cars. Adoption by other automotive and aerospace companies proceeded slowly but, over the decade starting in 1992, the complexity of automotive and aerospace electronics increased so much that the need for EDA became apparent. By year 2000, the business was blossoming but had outgrown its original roots in PCB design and layout. Martin Obrien joined Mentor from Raychem and brought with him a detailed knowledge of how automotive, aerospace and defense companies thought about electrical wiring architectures. That became one of the valuable core businesses of Mentor over time. Today, the “Capital” family of integrated electrical system design products has become the leading system connectivity design environment, extending from concept through simulation, topology, bill of materials, factory form boards for manufacturing and maintenance after the sale. Siemens has become a teaching customer but the Capital family is intensely focused on providing an open environment that can help Siemens’ competitors as much as it helps Siemens.

The 20 Questions with Wally Rhines Series

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Apogee Pipelining in Real Time

Apogee Pipelining in Real Time
by Alex Tan on 09-20-2018 at 12:00 pm
Categories: EDA

Pipelining exploits parallelism of sub-processes with intent to achieve a performance gain that otherwise is not possible. A design technique initially embraced at the CPU micro-architectural level, it is achieved by overlapping the execution of previously segregated processor instructions –commonly referred as stages or segments. Pipelining for timing fixes has become mainstream option in design implementation space, especially when designers had exhausted other timing closure means at the physical design step (such as optimizing wire utilization or resource sharing in the logic cone).

Anatomy of pipelining
Pipeline involves the use of flip-flop and repeater insertion –although some designers tend to focus on flip-flop insertion part, as it is assumed that the implementation tools are to perform repeater insertion by default (such as during synthesis stage or placement/route optimization).

Ideal pipelining should consist of equal stage latency across the pipeline with no resource sharing between any two stages. The design clock cycle is determined by the time required for the slowest pipe stage. Pipelining does not reduce the time for individual instruction execution. Instead, it increases instruction throughput or bandwidth, which can be characterized by how frequent an instruction exits the pipeline.

Pipelining can be applied on either the datapath or control signals and requires potential hazards monitoring. Ideally speaking, pipelining should be done closer to the micro-architectural step as adding flip-flops further down the design realization translates to perturbing many design entities and iterating through the long implementation flow.

SoC Design and Pipelining Challenges
With the recent emerging applications such as AI accelerators, IoT, automotive and 5G, two top challenges encountered by the SoC design teams are scalability and heterogeneity. The former demands an increased latency in the design, while the later requires a seamless integration of interfaces and models.

In the context of timing closure, there are two entry points for injecting pipelining to manage latency. The first is done post static timing analysis (STA). By identifying large negative slack margin among logic stages, designers could provide concrete data points to the architecture team (or RTL owner) for pipelining. This reactive step may be costly if excessively done as implied iteration to the RTL-change translates to resetting the design build.

On the other hand, pipelining can be also performed early on the RTL codes, during micro-architectural inception. While doing it at this stage provides ample flexibility, code architect tends to be conservative due to lack of an accurate delay estimation and being critically aware of increased flop usage impact to the overall design PPA. Hence, some designers have adopted a semi-manual method. It involves rule-of-thumb formulas combined with some SPICE simulations and spreadsheet tracking to arrive at pipeline budgeting plus an involved placement constraints to manage its implementation. This approach is tedious, iterative and prone to over-design as it may include guard-banding to cover backend optimization inefficiencies such as detours due to placement congestion or wire resource shortages.

Avatars and automatic pipelining
At DAC 2018 designer/IP track poster session, Avatar and eSilicon showcased the outcome of their collaboration in achieving successful pipelining through the use of automatic stage-flop insertion performed by Avatar’s Apogee. Avatar Apogee is a complete floor-planning tool that enables fast analysis of design hierarchy and early floorplanning exploration. It shares common placement, routing, and timing engines with Aprisa, the block level, complete placement and route tool (please refer to my earlier blog for other discussion on these tools). Based on its customer feedback, Avatar has introduced in its 18.1 release an automatic pipeline flip-flop insertion feature. This feature automatically adds stage flops on feedthrough nets during floorplanning stage using Avatar’s Apogee new command insert_stage_flop.

Delving further into the feature, first the long top level nets are routed by Virtual Flat Global Router by taking into account any existing congestions, blockages and macros inside the hierarchical partitions. Next, feedthroughs are assigned to the appropriate partitions and stage flops are added based on user specification that includes distance or flop count.

Similar to the mainstream method of pushing buffer into the hierarchy, after its addition the pipeline flops will be pushed into its hierarchical partition with the push_cell command. Subsequently, the module level netlist are automatically updated with the new hierarchical cell instance and the corresponding port gets created at this level as illustrated in Figure 3.

Results and Comparison

Using a large Mobile SoC design as a test case and Apogee’s automatic approach, the design was implemented and routed. The tabulated results show that there were 18% fewer stage flops needed and a 22% saving in flip-flop power with minimal DRC and timing violation (significant reduction in both TNS and WNS slacks).

The total process takes about 2 hours to auto-insert as compared to 3 weeks of manual efforts and multiple iterations to reach to the final flop count. On top of that, timing and routability were challenging with the manual approach. With Apogee, timing and congestion aware automatic placement ensure both routability and timing convergence of the design.

In summary, designers can use Apogee’s new automatic stage flop insertion feature to reduce iterations and also get better stage flop count leading to lower sequential power. The flow also supports netlist update and reports that simplifies downstream formal verification process. According to Avatar Integrated Systems, it plans to expand the capability to auto insert or delete pipeline flops at the block-level placement optimization step in Aprisa –to further improve QoR at block level.

For more details on Avatar’s Apogee please check HERE and Aprisa HERE.

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Supporting ASIL-D Through Your Network on Chip

Supporting ASIL-D Through Your Network on Chip
by Bernard Murphy on 09-20-2018 at 7:00 am
Categories: Arteris, Automotive, IP

The ISO 26262 standard defines four Automotive Safety Integrity Levels (ASILs), from A to D, technically measures of risk rather than safety mechanisms, of which ASIL-D is the highest. ASIL-D represents a failure potentially causing severe or fatal injury in a reasonably common situation over which the driver has little control. Certification to one or more of these levels requires demonstrating that a system can guarantee better than a specified probability of failure, generally requiring increasing levels of failure mitigation, analysis and supporting documentation with each level.

Semiconductor component providers have opted in many cases for certification to component levels below D for cost and/or time-to-market reasons. But this is changing. As electronic content in our cars is increasing, distinctions between what does and does not critically affect safety are blurring. An ECU that might be used in an ASIL-B function today could become interesting for use in an ASIL-D function next year. Consequently, OEMs are extending their demands for ASIL-D certification across more components, to ensure they’re covered no matter what the application.

This ramps up effort demanded in safety assurance in more designs. Certainly component functions must demonstrate mitigation to an appropriate level, but also special care is needed in integrating those components together, commonly through a NoC interconnect. There are three approaches that designers can take to ASIL-D compliance for that network-on-chip:

  • Complete replication (in this case the NoC), either duplication with comparison checks which will report a failure (where it is sufficient to warn the driver that a function has failed) or triplication with majority voting where a failure in one function can be overridden by outputs from two good functions (where simply knowing a system has failed is not enough). Still, complete duplication or replication of a NoC would be a very expensive option.
  • Another acceptable approach is to provide path diversity. If a component fails in one path, there should be other paths through which system operation can continue to work, possibly after updating routing tables. In effect the system can heal around bad nodes and continue to operate. The challenge here is that the designer must prove that all possible paths have backup paths, again likely to be expensive. A second consequence is that performance impact from possible rerouting has to be characterized, potentially as rigorously as for the good part. And finally updating the routing is a software function which will take time and adds further risk, and that must also be characterized and mitigated.

  • A less expensive and disruptive approach is to replicate only those functions within the NoC that must be replicated, such as control blocks, and to use ECC on interconnect wires to correct single-bit errors and flag 2-bit errors. This approach still meets the ASIL-D requirement, avoids all the complications associated with path diversity and has limited area overhead since control blocks represent a relatively small percentage of the overall NoC area.

For a way to meet these new stringent requirements, the last method above is difficult to beat. Adding 8-bits of ECC to a 64-bit link increases the size of the NoC by a little over 10%, versus doubling the size if duplicating the NoC. The solution is entirely in hardware and errors are corrected instantaneously with no need for software reconfiguration and no extra latencies. Finally, validating fault coverage and building a comprehensive FMEDA for the configured network can be completed with existing tools, compared with a path diversity approach which would require analysis over both hardware and network reconfiguration software.

To learn more about Arteris solutions for ASIL-D-compliant NoC interconnect, go HERE.

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Semiconductor IP Reality Check

Semiconductor IP Reality Check
by Daniel Nenni on 09-19-2018 at 12:00 pm
Categories: AI, eSilicon, IP
3 Comments

A robust, proven library of IP is a critical enabler for the entire semiconductor ecosystem. Without it, ASIC design is pretty much impossible, given time-to-market pressures. Said another way, designing IP for your next chip simply doesn’t fit the schedule – most teams have barely enough time to integrate and validate pre-existing IP. Without solid IP coverage, new process nodes also become somewhat irrelevant for the same reasons. So, designers and foundries care about IP a lot.

7nm is where a lot of the action is these days regarding IP delivery. Datacenter, networking, AI and 5G infrastructure all have a thirst for the power and performance delivered by this node. So, there are lots of claims out there regarding 7nm IP. “World’s first, industry-leading, silicon-proven, robust” are just some of the words you’ll find in all the marketing material available for 7nm IP. The question is, how do you separate the hype from reality, and more importantly how do you truly reduce risk?

Simulation results, silicon data and number of tape outs are all important parts of the homework needed to find IP that is truly “robust”. Lately, there is another dimension to the problem worth considering as well. Beyond the IP working in silicon, does all the IP work well together? Before you bet the farm on your next 7nm design project, are you confident that all the IP will play well together? A completely validated library of IP can still cause huge headaches of it all doesn’t work together. Integration risks are very real, as are the risks associated with modifying IP to hit the required power, performance or area target.

The concept of IP that works well together and supports customization for a target application makes a lot of sense. Recently, eSilicon announced two such IP offerings for data center and AI chips, which SemiWiki covered here. eSilicon calls the concept an “IP platform”. I’m sure other marketing terms will emerge.

Recently, there have been a couple of announcements from eSilicon that bring these platforms closer to home. It turns out a high-performance SerDes is a critical enabler for both platforms. Last week, eSilicon announced very encouraging results from the silicon validation of its 56G 7nm SerDes. Their press release stated: “… lab measurements confirm that the design is meeting or exceeding the target performance, power and functionality. Based on these results eSilicon has begun to demonstrate its test chip to key customers.” So, contact eSilicon if you want to see what their SerDes can do, first hand.

This week, eSilicon announced that theirneuASICä platformis available for customer designs. Some detail about the what’s in neuASIC were disclosed:

“The neuASIC IP platform has been through several 7nm tapeouts. The platform includes the following compiled, hardened and verified functions:

  • Configurable multiply-accumulate (MAC) blocks
  • Single-port SRAM
  • Pseudo two-port and pseudo four-port SRAM
  • Ternary content-addressable memory
  • Pitch match memory
  • GIGA memory
  • WAZPS (word all zero power saving) memory
  • Transpose memory
  • Re-mapper – low power cross-bar
  • Convolution engine
  • 56G SerDes
  • HBM2 PHY

The platform also provides a software AI Accelerator Builder function that provides PPA estimates of the chosen ASIC architecture before RTL development starts.”

So, another reason to contact eSilicon if you’re considering a 7nm AI ASIC. I would check out both of these platforms if you want to reduce integration risks, absolutely.

Also read: eSilicon Announces Silicon Validation of 7nm 56G SerDes

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Integrated Power Management IP to Decrease Power and Cost

Integrated Power Management IP to Decrease Power and Cost
by Eric Esteve on 09-19-2018 at 7:00 am
Categories: Dolphin Design, IP

This blog is the synthesis of a white paper “New Power Management IP Solution from Dolphin Integration can dramatically increase SoC Energy Efficiency”, which can be found on Dolphin Integration web site.

The power consumption generated by complex chips was not a real issue when the system could be simply plugged in the wall to receive electricity. The most important feature used to be raw performance, expressed in GHz or MIPS, and was used to market PC to end-user, for example.

Nevertheless, with the huge adoption for wireless mobile devices in the 2000 and later, the metric has changed. For battery powered devices, the time between two battery charge became almost as important as the MIPS power delivered by the phone/smartphone. That’s why efficient but costly external power management solution (7$ for the iPhone 6, up to $14 for the iPhone X) have been implemented in smartphone.

With the massive adoption of battery powered system expected in IoT, industrial or medical, power efficiency is becoming a mandatory requirement, together with low system cost. To reach these goals, SoC will have to be architectured for low-power and integrate power management IP on-chip.

In fact we realize that power consumption is also becoming a key concern in automotive application (ADAS) or sever/network infrastructure. These applications will have to be much more energy efficient, for different reasons like reliability (automotive) or cost (raw electricity and cooling cost in data center). In short, the entire semiconductor industry will have to offer more energy efficient devices, at the right cost. The way to do it is through defining power aware architecture and design chips integrating power management IP.

In this white paper “New Power Management IP Solution from Dolphin Integration can dramatically increase SoC Energy Efficiency”, Dolphin Integration has reviewed all the solutions available to decrease SoC power consumption. The first technique is to define and manage power domains inside the SoC, well-known in the wireless mobile industry, but other techniques can be considered.

Dynamic voltage frequency sclaing (DVFS), near threshold voltage, body biasing, globaly asynchronous localy synchronous (GALS) are also reviewed and discussed in this paper. But a low-power SoC has much smaller noise margin, and special care must be taken to preserve signal integraty in this SoC. In other words, you need experts to support you when implementing these new power management solutions.

In the second part of the paper, the author explains how implementing power management IP in customer’s SoC. The design team has to start from the architecture level to define “power-aware” SoC architecture.The the first task for the designer will be to identify the various functions belonging to the same power domain. This power domain is not simply defined by voltage, but in respect with the functionality of the various blocks expected to be part of the same task in a given power mode.

Once you have split the chip in power islands (memory, logic, analog, always-on, etc.) it’s time to control, gate (power gating, clock gating) and distribute power and clock in the SoC. This will be done by implementing the various power management IPto power the SoC core, and the designer will select controlling power switches, VREG or Body Biasing generator and clocks gating anddistribution, all part of the power network IP port-folio from Dolphin Integration.

The implementation of the SoC power mode control is made straight-forward, thanks to a modular IP solution (named Maestro). This power mode control IP is equivalent to an external Power Management IC (PMIC), similar to those integrated in a smartphone. Maestro will manage start-up power sequence, power mode transition and optimize the power regulation network.

Dolphin Integration claim offering faster TTM and lower cost for customer selecting their power management IP solution, instead of trying to design a low-power SoC on his own. As the design team implement the power management controller (Maestro) as an IP in the SoC, the sytem BOM is lower than using an external PMIC controller (remember the impact of PMIC on the iPhone 6 and X BOM).

Faster TTM is made possible, thanks to technical support from expert engineer, from top level (power-aware architecture definition) to design phase (implementation of the various power management IP). This expertize in low-power design will allow escaping traps, like new noise issues due to mode transition for a SoC partitioned in power domains, or signal integrity suceptibility to crosstalk when operating at extremelly low voltage level.

In the Moore’s law golden age, a chip maker had just to re-design to the next technology node to automatically benefit from higher performance and lower power consumption-at the same time. Today, the semiconductor industry is addressing new applications like edge IoT, medical wearable devices and many more, requiring low-cost IC probably designed on mature technology nodes.

Frequently battery powered, these SoC require an ultra-low power consumption, which can only be reached by using power management techniques. In this white paper, Dolphin Integration describes these new techniques and how to implement power management IP from the architecture level down to the back-end. This is not an easy task, especially when doing it for the first time. That’s why the SoC design team need technical support from low-power design experts and a silicon proven IP portfolio to release an energy-efficient device, on line with the time to market requirement.


To see the White Paper, go to this link

ByEric Esteve fromIPnest

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Beyond DRC and LVS, why Reliability Verification is used by Foundries

Beyond DRC and LVS, why Reliability Verification is used by Foundries
by Daniel Payne on 09-18-2018 at 12:00 pm
Categories: EDA, Siemens EDA

Reliability of ICs isn’t a new thing, because back in 1980 I was investigating why a DRAM chip using 6um technology was having yield loss due to electromigration effects. I recall looking through a microscope at a DRAM layout and slowly ramping up the Vdd level then suddenly the shiny aluminum interconnect started to change colors and actually bubble because of the high currents, then the metal evaporated. We never could identify the cause of that reliability failure, so it’s kind of haunted me all of these years.

IC designers today will start out a new project by requesting the foundry files for DRC (Design Rule Check), LVS (Layout Versus Schematic) and PEX (Parasitic EXtraction) so that they can perform physical verification tasks to ensure high-yielding silicon and meet timing specifications. In addition to these checks there are an increasing number of reliability checks that need to be done, like:

  • ESD (Electro Static Discharge)
  • LUP (Latch-up)
  • Interconnect reliability
  • Electrical overstress

The number one foundry is TSMC, so no surprise that they have also been at the forefront of providing reliability checks for:

  • ESD
  • LUP
  • Point-to-point resistance
  • Current Density
  • Layout-based rules

Another foundry TowerJazz has been offering reliability checks for automotive IC designers as they follow the ISO 26262 standard for functional safety. These checks include:

  • ESD
  • Charge Device Model (CDM)
  • Analog design constraints

    • Device alignment
    • Symmetry
    • Orientation/parameter matching

Both TSMC and TowerJazz support Mentor’s EDA tool Calibre PERCfor the reliability checks mentioned above.

When adopting a set of foundry reliability design rules you need to understand what these rules are doing, and how your company reliability goals align with them. As a starting point the foundry rules for ESD and LUP can be used, then your team or company can decided to extend the rules to check for certain conditions:

  • Each IP is implemented OK
  • LUP that is context aware
  • Interconnect analysis
  • Stacked device in context of full chip
  • Power ties correct per well

Best practice is to run the reliability checks on each IP block of your chip, so that with final integration there are no surprises that need to be fixed. Reusing IP on a new project but with multiple power domains is another good reason to run reliability checks, as shown below:


Multiple power domains require validation

Verifying IP individually is a good start, but not sufficient for full-chip integration because context matters. Here are three cases where context matters:

  • ESD and EOS protection
  • Voltage-aware DRC
  • CDM checking for point-to-point resistance values


Reliability checking with full-chip context

If the bulk node is connected to a higher voltage level than the gate, then it causes a reliability issue for EOS. We do voltage-aware DRC checks to verify that time-dependent dielectric breakdown (TDDB) isn’t happening. Avoiding CDM issues is accomplished through detailed point-to-point resistance checking.

Summary
I’ll never forget the transition from manual DRC and LVS to automated, what a relief for IC designers. The same thing is happening with reliability checks, so start using the foundry-supplied reliability rule checks then add to them as needed for your design and reliability goals. The Calibre PERC tool has been around for a while and it’s ready for your designs and supported by the major foundries.

White Paper
Mentor has an 8 page White Paper on this topic, so start the download process here.

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Webinar: Multicycle Vectorless Dynamic IR Signoff for Near 100 Percent Coverage

Webinar: Multicycle Vectorless Dynamic IR Signoff for Near 100 Percent Coverage
by Bernard Murphy on 09-18-2018 at 7:00 am
Categories: Ansys, Inc., EDA

Check this webinar out – Mediatek will share a novel approach to early IR drop estimation. Competition in system design has become even more intense because potential markets are huge and there are more players with deep pockets chasing those markets. Wherever you are in those value chains, you want to shift everything left to accelerate schedules. But there’s a challenge in that goal; what do you do if the step you want to accelerate depends on simulation vectors? Dynamic IR signoff is one such application.

REGISTER HERE for this webinar on October 2[SUP]nd[/SUP], 2018 at 9am PDT.

You could wait until late in design but then you take the risk that you’ll find a significant weakness when you’re almost out of time. If you start early, you can use a vectorless approach, but the general view has been that these are too inaccurate to provide effective guidance. Necessity (or at least competition) apparently is the mother of invention. MediaTek will share in this webinar how they use a vectorless approach to get to very high IR coverage, isolate hotspots and increase confidence in their final signoff.

REGISTER HERE for this webinar on October 2[SUP]nd[/SUP], 2018 at 9am PDT.

Summary
Next-generation mobile, automotive and networking applications require the use of advanced SoCs to deliver greater functionality and higher performance at much lower power. For these SoCs, the margins are smaller, schedules are tighter while costs are higher. Faster convergence with exhaustive coverage is therefore imperative for first time silicon success. For next generation applications, the numbers of vectors for which you need to run simulations have increased multi-fold. It is nearly impossible to uncover potential design weaknesses when you are simulating a handful of vectors for just a fraction of second. How do you ensure you have enough design coverage? The common approach for dynamic IR signoff uses vector-patterns with true delay information. This approach is performed late in the design cycle, requires long simulation time and yields limited IR coverage due to limited vector-patterns. Published traditional vectorless approaches produce unsatisfactory IR coverage and correlation to vector-patterns. Attend this webinar to learn how MediaTek’s novel multicycle vectorless flow uses a design power target, selectively sets a high toggle rate and enables state-propagation features in ANSYS-RedHawk. The new flow achieves 97 percent IR coverage of non-memory cells and 100 percent IR coverage of memory cells, captures IR hotspots and reduces run time by 3X, accelerating signoff processes and improving power grid quality.

Speakers
Annapoorna Krishnaswamy, Product Marketing Manager at ANSYS

Huajun Wen is a distinguished engineer at Mediatek. She is currently responsible for developing new IR signoff flows to ensure robust and efficient power grid designs of Mediatek products. She has comprehensive knowledge and expertise in modeling and reducing IR from PMIC to transistors. Her experiences span chip power modeling and characterization, physical design and timing methodology, and on-chip power conversion techniques. Prior to joining Mediatek at 2013, Huajun was an IBM Senior Technical Staff Member, holding various physical design leadership positions on IBM Power and Mainframe processors designs as well as Cell Processor design used in the Sony Playstation3. She published 20+ technical papers and holds 10+ US granted patents. Huajun received her Ph.D. in solid state physics from Free University Berlin, Germany.

About ANSYS
If you’ve ever seen a rocket launch, flown on an airplane, driven a car, used a computer, touched a mobile device, crossed a bridge, or put on wearable technology, chances are you’ve used a product where ANSYS software played a critical role in its creation. ANSYS is the global leader in engineering simulation. We help the world’s most innovative companies deliver radically better products to their customers. By offering the best and broadest portfolio of engineering simulation software, we help them solve the most complex design challenges and engineer products limited only by imagination.

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Facebook and WhatsApp are not just flawed they are downright dangerous

Facebook and WhatsApp are not just flawed they are downright dangerous
by Vivek Wadhwa on 09-17-2018 at 7:00 am
Categories: General
6 Comments

Facebook’s woes are spreading globally, first from the U.S., then to Europe and now in Asia. A study by researchers at the University of Warwick in the U.K. has conclusively established that Facebook has been fanning the flames of hatred in Germany. The study found that the rich and the poor, the educated and the uneducated, and those living in large cities and those in small towns were alike susceptible to online hate speech on refugees and its incitement to violence, with incidence of hate crimes relating directly to per-capita Facebook use.

And during Germany-wide Facebook outages, which resulted from programming or server problems at Facebook, anti-refugee hate crimes practically vanished — within weeks.

As The New York Times explains, Facebook’s algorithms reshape a user’s reality: “These are built around a core mission: promote content that will maximize user engagement. Posts that tap into negative, primal emotions like anger or fear, studies have found, perform best and so proliferate.”

Facebook started out as a benign open social-media platform to bring friends and family together. Increasingly obsessed with making money, and unhindered by regulation or control, it began selling to anybody who would pay for its advertising access to its users. It focused on gathering all of the data it could about them and keeping them hooked to its platform. More sensational Facebook posts attracted more views, a win-win for Facebook and its hatemongers.

In countries such as India, WhatsApp is the dominant form of communication. And sadly, it is causing even greater carnage than Facebook is in Germany; there have already been dozens of deaths.

WhatsApp was created to send text messages between mobile phones. Voice calling, group chat, and end-to-end encryption were features that were bolted on to its platform much later. Facebook acquired WhatsApp in 2014 and started making it as addictive as its web platform — and capturing data from it.

The problem is that WhatsApp was never designed to be a social-media platform. It doesn’t allow even the most basic independent monitoring. For this reason, it has become an uncontrolled platform for spreading fake news and hate speech. It also poses serious privacy concerns due to its roots as a text-messaging tool: users’ primary identification being a mobile number, people are susceptible everywhere and at all times to anonymous harassment by other chat-group members.

On Facebook, when you see a posting, you can, with a click, learn about the person who posted it and judge whether the source is credible. With no more than a phone number and possibly a name, there is no way to know the source or intent of a message. Moreover, anyone can contact users and use special tools to track them. Imagine the dangers to children who happen to post messages in WhatsApp groups, where it isn’t apparent who the other members are; or the risks to people being targeted by hate groups.

Facebook faced a severe backlash when it was revealed that it was seeking banking information to boost user engagement in the U.S. In India, it is taking a different tack, adding mobile-payment features to WhatsApp. This will dramatically increase the dangers. All those with whom a user has ever transacted can harass them, because they have their mobile number. People will be tracked in new ways.

Facebook is a flawed product, but its flaws pale in comparison to WhatsApp’s. If these were cars, Facebook would be the one without safety belts — and WhatsApp the one without brakes.

That is why India’s technology minister, Ravi Shankar Prasad, was right to demand, this week, that WhatsApp “find solutions to these challenges which are downright criminal and violation of Indian laws.” The demands he made, however, don’t go far enough.

Prasad asked WhatsApp to operate in India under an Indian corporate entity; to store Indian data in India; to appoint a grievance officer; and to trace the origins of fake messages. The problems with WhatsApp, though, are more fundamental. You can’t have public meeting spaces without any safety and security measures for unsuspecting citizens. WhatsApp’s group-chat feature needs to be disabled until it is completely redesigned with safety and security in mind. This on its own could halt the carnage that is happening across the country.

India — and the rest of the world — also need to take a page from Germany, which last year approved a law against online hate speech, with fines of up to 50 million euros for platforms such as Facebook that fail to delete “criminal” content. The E.U. is considering taking this one step further and requiring content flagged by law enforcement to be removed within an hour.

The issue of where data are being stored may be a red herring. The problem with Facebook isn’t the location of its data storage; it is, rather, the uses the company makes of the data. Facebook requires its users to grant it “a non-exclusive, transferable, sub-licensable, royalty-free, worldwide license to use any IP content” they post to the site. It assumes the right to use family photos and videos — and financial transactions — for marketing purposes and to resell them to anybody.

Every country needs to have laws that explicitly grant their citizens ownership of their own data. Then, if a company wants to use their data, it must tell them what is being collected and how it is being used, and seek permission to use it in exchange for a licensing fee.

The problems arising through faceless corporate pillage are soluble only through enforcement of respect for individual rights and legal answerability.

For more, read my book “Your Happiness Was Hacked: Why Tech Is Winning the Battle to Control Your Brain — and How to Fight Back” and follow me on Twitter:@wadhwa.