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Why Did Ambiq Micro Select HiFi-5 DSP IP for Next Generation MCU?

Why Did Ambiq Micro Select HiFi-5 DSP IP for Next Generation MCU?
by Eric Esteve on 11-06-2018 at 6:00 am
Categories: Automotive, Cadence

Ambiq Micro has built a family of voice processing MCU dedicated to battery powered, energy sensitive systems, supporting mobile application like wearable. The company is facing two strong challenges: support computationally intensive processing (NN-based far field) and speech recognition algorithms, while offering “ultra-low power” devices. When Ambiq claim to build ultra-low-power devices, it’s really the case: the company has developed a unique and proprietary technology, the Subthreshold Power Optimized Technology (SPOT™) platform (SPOT architecture uses transistors biased in the subthreshold region of operation).

These two challenges are clearly in contradiction: intensive processing built in energy-sensitive devices, this sounds like the perfect definition of energy-efficiency! According with Aaron Grassian, VP of marketing, Ambiq Micro, “Porting the HiFi 5 DSP to Ambiq Micro’s SPOT platform enables product designers, ODMs and OEMs to take the most advantage of technology from audio software leaders like DSP Concepts and Sensory by adding voice assistant integration, command and control, and conversational UIs to portable, mobile products without sacrificing quality or battery life.”

Tensilica HiFi 5 DSP core is the new generation of voice dedicated DSP, it can be interesting to look at the main changes with the previous HiFi 4 DSP core. MAC capability has been multiplied by 2X, leading to 2X audio (pre- and post-) processing. For NN processing, the HiFi 5 offer 4X MAC capability versus HiFi 4, including 32 16×8 or 16×4 MACs per cycle. Moreover, the new HiFi NN library offers a highly optimized set of library functions commonly used in NN processing (especially speech). And software backward compatibility with the complete HiFi product line is guaranteed, totaling over 300 HiFi-optimized audio and voice codecs and audio enhancement software packages.

Such a voice dedicated DSP has to support voice pre-processing functions, like beamforming (or spatial filtering), noise reduction and accoustic echo cancellation (AEC), and speech recognition : features extraction, NN processing layers and language decoding. As a side note, Cadence Tensilica HiFi DSP should be pretty good IP core, as the company claims 95 licensees for HiFi DSP worldwide, and ship 1 billion cores annualy (probably a bit less IC when you integrate several cores in the same chip).

Clearly, there is a dramatic rise in popularity of digital home assistants (Alexa and the likes) that features voice UI experiences, leading to a new wave of innovation in far-field processing algorithms and in neural network-based speech recognition. It’s now clear that the processing power has to be at the edge device and not in the cloud, and there are good reasons to support this architecture. The consumer demand is for lower latency, increased privacy and more natural voice UI interactions and the processing work load on device has to increase rapidly to make the end-user happy.

For OEM also, voice-controlled User Interfaces are becoming more important. For example, in many of today’s in-car, voice UI infotainment platforms end up training the driver (as opposed to the other way around). And consumer adoption of voice assistant technology in home is encouraging car manufacturers to embrace voice. Moreover, automotive voice assistants require local voice recognition, pushing again for more processing power in the edge device. In fact, cloud is not always available, and, again, latency is a concern for consumer experience.

If we agree that speech recognition should be done locally, how to enable this trend? You need more advanced NN algorithm techniques at first, and high-performance DSP cores available at the edge. But you also need lower-precision NN memory weights to reduce the memory size and bandwidth requirements, to build an economically viable and energy-efficient edge device. If you can meet these conditions, you can address privacy concerns, low latency demand and enable on-device speech recognition.

For example, to meet power and memory bandwidth efficiency, the HiFi 5 offers natively support for lower precision weights: 8-, 4-, 2- and even 1-bit, Viterbi decode support and 8-bit SIMD element support for sorting, searching for string processing.

I don’t know if your kitchen looks like this above pictured, if it’s the case you will probably count several Tensilica HiFi 5 DSP at home, all located at the edge!

ByEric Esteve fromIPnest

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The Changing Face of IP Management

The Changing Face of IP Management
by Alex Tan on 11-05-2018 at 11:00 am
Categories: Cliosoft, EDA, IP


Aristotle once said “The whole is greater than the sum of its parts”. The notion of synergism echoes the importance of leveraging design IPs to the maximum extent with the rest of the system under development, in order to ensure a successful SoC design outcome in a shorter development cycle.

SoC design cost and entry point
For over a decade design IPs have increased in complexity and have steadily grown to become the starting point of most SoC designs today. Foundries such as TSMC have disclosed data regularly showing a steady increase on silicon proven IP offerings to keep pace with frequent shift in process technologies and design applications. As shown in figure 1, the number of itemized IPs has doubled to more than 16,000 over the years, accompanied by numerous process technology collaterals (200+ PDK; 9000+ technology files).

On the other hand, many fabless companies including top-performer startups attempt to establish value differentiation in their products through innovations leading to internal IP development efforts that eventually translate to candidates for patented technologies. Other design teams may bridge the gap between shorter design cycles and having marketable products by reducing the overall design risk and cost through a mix of externally proven interface IP blocks (such as Ser-Des, PCI-e, etc.) and internally developed IPs containing their core technology.

Based on a recent Semico research data, SoC design cost –including IP integration cost—is surging, and prompting designers to exercise prudence in their design selection such as in choosing the right IPs, target technology nodes, the correct version of the PDK and the type of design implementation (FPGA vs ASIC).

IP stakeholders, design IP management and designHub
Designers are often wearing dual hats: one as IP developers while designing new blocks, and the other as IP users or integrators. An ideal IP management solution should be capable of serving this dual usage types and bridge the gap between the IP developers and IP users within a company. Most IP users prefer to be able to trace the IP to see its usage, process nodes available, have access to IP developers to have any queries answered, compare IPs and have access to open issues, as well as the available documentation for the IP.

Yet the IP developers –-who will build, check and populate the design building blocks — are often concerned about the support they have to provide for the IP. Managing and answering the constant queries on the IPs after all takes time. Other challenges for the IP developer is in keeping the IP secure, keeping track of the different versions of the IP and the data associated with each revision, the process nodes and the PDKs used. Moreover, with the IP information fragmented across multiple applications such as issue tracker, meeting minutes, documents, emails etc, it becomes challenging to collate all the information in one location for easy access for the IP user.

Given the rise of IPs and the IP subsystems being used, it becomes more important to have a flexible IP ecosystem that could facilitate the growing needs and use models of semiconductor design companies –in building system level designs as well as frequent auditing and update needs due to product refresh.

More importantly, every company has a large number of internal IPs which could be leveraged to build new SoCs. Unfortunately the lack of confidence in the internally used IPs compells design teams within a company to look at alternatives which can include either developing their own IP or buying another IP. Such a choice tends to affect the bottom line of the company.

The correct solution would be to facilitate the bridging of the gap between the IP developer and user by providing an ecosystem wherein the IP user can qualify the IP easily and browse through the available documentation collated from different applications such as document control systems, emails, issue tracking systems, etc. Moreover to reduce the support burden for the IP developer, it becomes necessary to have a knowledgebase around every IP which can be used by the users to have their queries answered.

 

designHUB is ClioSoft’s answer to the problems faced by design teams today. It is an enterprise IP management solution which addresses the needs of IP developers and users alike. As an IP ecosystem, designHUB bridges the gap between IP user and IP developer for internal IPs by enabling users to leverage a growing knowledge base of the IPs to resolve any issue they may have. It is easily configurable to meet the IP reuse requirements of most design companies and manages a complex matrix of IP attributes such as process nodes, nodlets, foundries, IP functionality, IP usage, etc. without intimidating the user. As a result, any user can provide a wide array of attributes to find and compare an IP. designHUB is also capable of tracking the variations of an IP through its various stages of evolution and has built-in analytics to report IP usage and its various nuances.

IP reuse, security and ecosystem
Design reuse provides an opportunity for design teams to plan ahead and target parts of their incepted designs to be used in future product developments. Having access to all the information regarding an IP enables designers to make more qualified decisions on which IPs to use for their SoC. But it becomes necessary to choose a platform which can match the growing needs of your enterprise as well as the new evolving technologies.

designHUB IP management promotes design reuse within a company by providing an easy-to-use dashboard to manage the process of creating and publishing IPs as well as their derivatives. Most importantly, it is DM agnostic. Most companies have either no DM, one DM or many DMs (such as SOS7, Perforce, Git, Subversion). It becomes important to have a IP management system which works with all types of DM or no DM –as no company wants to reinvent the wheel for internally developed IPs. If there is any IP, which that can be reused within the company, the idea is to leverage it to the maximum extent possible. As a flexible IP reuse ecosystem, designHUB can help designers to map reuse requirements and select the most suitable IPs for their SoCs.

To recap, selecting the right entry point (technology, IPs) and a robust IP management solution is key in reducing potential risks of over-budgeting and failure in SoC design. For more details on ClioSoft’s designHUB check HERE.

Also Read

Data Management for SoCs – Not Optional Anymore

Managing Your Ballooning Network Storage

HCM Is More Than Data Management

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Is ARM TechCon Really Worth it?

Is ARM TechCon Really Worth it?
by Daniel Nenni on 11-05-2018 at 6:00 am
Categories: Arm, Events, IP
5 Comments

The ARM TechCon organizers are asking me what I thought of this year’s conference so here it goes. As you know I am a big fan of ARM TechCon and feel it is one of the better conferences for SoC design. This year however I noticed a big change in demographics. Maybe the location change had something to do with it but I definitely saw different faces this year. I also saw fewer faces. I’m sure the conference organizers will come out with some big numbers but in my opinion it was a down year in regards to qualified attendees, especially the ones I met in the exhibit hall.

I signed more than 200 Prototypical books in the S2C booth, mostly the first day but maybe 50 or so on day two. When I sign books I get to talk to the people and I always ask where they work and what they do. This year it was overwhelmingly software development versus chip design. In looking at the 200+ badges that were scanned by S2C you will only find a handful of actual chip designers. In fact, the number of people off the street just collecting give away stuff was inordinately high. I attribute that to the location, downtown San Jose versus Santa Clara, the high tech hub of Silicon Valley. Location location location.

According to the S2C sales person who covered the booth, only about 10 of the 200+ people who got books were qualified ASIC prototyping leads. In the other booths I talked to qualified leads were in the single digits so the book give away gave a bit of an edge. The cost of the booth and related fixings was about $10,000 which gets you to about $1,000 per lead. Of course, getting out there and being seen counts but it is very hard to financially justify.

That being said, my constructive criticism is to move ARM TechCon back to Santa Clara and reduce the cost of participation for emerging companies. The EDA and IP ecosystem has changed due to acquisitions. There are now a handful of very large and medium sized companies with many, many small companies. The landscape is changing yet the conferences fight to stay the same, not good.

One of the reasons we started SemiWiki was to give emerging companies a fighting chance against the bigger EDA and IP companies by providing a level playing field for branding and demand creation. Of course the big companies were quick to join and they do drive a significant amount of traffic for the greater good of SemiWiki. We are, however, still focused on helping emerging companies in all aspects of business (funding, sales, marketing, business development, acquisition, etc…) and will continue to do so, absolutely.

Last week we were at the Linley Processor Conference. Linley does a very nice job, in fact, I would say they do the best regional conference in regards to content and cost. The first keynote was standing room only at the Santa Clara Hyatt (my favorite location). Linley Gwennap did a great presentation on “Breaking Bottlenecks in Processor Design” which we will blog about later.

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Connected Cars High Tech Low Demand

Connected Cars High Tech Low Demand
by Roger C. Lanctot on 11-04-2018 at 6:01 am
Categories: Automotive
1 Comment

The latest reliability report from Consumer Reports which dumped on domestics and rained glory upon Asian imports highlighted a conundrum facing car makers. The more effort car makers put into innovation, the greater the risk of consumer confusion, system failure and lousy reliability scores.

The picture is even worse if one takes into account key areas of innovation sweeping the industry including: electrification, connectivity, autonomous operation and car sharing. The one attribute all of these value propositions have in common is low consumer demand.

Strategy Analytics surveys of consumer car buying priorities typically show an interest in reliability, fuel efficiency and safety while the industry responds with complexity. The technology laggards in Japan and South Korea walk away with the bouquets year after year.

Factor in the prevalence of smartphones and the onset of digital assistants and the bulk of high tech auto gear is regarded as irrelevant or prohibitively expensive by consumers. This means that all of the billion dollar investments that the auto industry is making in startups, acquisitions and in-house development are targeting low demand, high cost applications.

Two applications, in particular, stand out: connectivity and car sharing. Car makers feel compelled to embrace connectivity for safety reasons (eCall mandate in Europe for automatic crash notification), cybersecurity protection, software updates and vehicle diagnostics. But consumers are less than enthusiastic.

Given the high cost of adding an embedded wireless connection, auto makers are desperate to recover their investments with subscription-based services or marketing platforms. The most egregious example of this effort by car makers to directly monetize vehicle connections is GM’s Marketplace – a privacy violating, driver distraction quatch being foisted on unsuspecting consumers.

Marketplace is redundant and irrelevant. The auto industry is poised on the threshold of an app-less future. Driver and passenger interactions with on-board and off-board content, services and applications will be driven by AI-infused voice interfaces not on-screen icons.

Connectivity remains a hard sell because car makers continue to demand a price rather than including it in the cost of the vehicle. Even wireless carriers – such as Deutsche Telekom and Verizon – are losing interest in the subscription-based model and abandoning the connected car market to the likes of AT&T, Vodafone, KDDI and T-Mobile.

The other application with a weak market pulse is car sharing. Car makers and some rental companies have tapped into rivulets of consumer interest, but a true groundswell remains elusive. The muted response is readily attributable to the fact that the market leaders are ruled by their legacy car rental and vehicle sales operations.

There is a lot of talk of the rise of mobility services and transportation-as-a-service platforms – but market fragmentation and an attention deficit means crucial advertising and marketing dollars are directed toward selling and renting cars, not toward sharing cars. Where’s Clay Christensen when you need him?

The only creative destruction underway in transportation is coming from pure play ride hailing companies like Gett, Uber, Grab, Lyft and others. A simple message of a cheap, convenient transportation alternative translates into rapid adoption and market penetration.


After more than 20 years of car sharing (some might say 50 years) only 260,000 cars globally are available as part of car sharing programs large and small, free floating and station based. Is the sector ripe for transformation and rapid growth? Perhaps.

What could change the demand scenario for connected and shared cars? Two things. Car companies need to build in connectivity and make connectivity an intrinsic element of owning, sharing, renting or simply operating a car. The onset of 5G technology will help.

As for car sharing? It may take the rise of pure play car sharing startups like Mevo (Australia), Zazcar (Brazil) or Car2Go (Israel) to shake things up. Car buyers are telling car makers they’re pretty content with the status quo. It’s going to take a marketing jolt or a fundamental business model shift to alter the underlying market dynamics. If legacy car makers can’t deliver, startups (like Tesla) will step in – rather, are stepping in.

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Q4 Hiring remains strong Outlook for Q1 2019

Q4 Hiring remains strong Outlook for Q1 2019
by Mark Gilbert on 11-04-2018 at 6:00 am
Categories: IoT, Semiconductor Services

Things are going quite well in the Valley, ESPECIALLY if traffic is any indication. I still remember the BUST with the empty office buildings and light traffic, back in the early 2000’s…while I wish for traffic like that always, I certainly prefer the busy times, guess you cannot have it all. The more traffic, the more jobs; they invariably go hand in hand as a sign.

As for ARM Techcon, it seemed busy enough, though with the new layout and location made it somewhat difficult to compare to previous years. This year, the conference moved to the San Jose Convention Center, which is a much larger footprint than the Santa Clara CC, where it has been previously held, for many years. The show did seem larger and attendance was robust with most of the folks I chatted with telling me, they were having a good show. Daniel Nenni, famed top dog at SemiWiki, signed so many of his new book (his 6[SUP]th[/SUP] I think), that he would not even give me one for fear of running out…so I just took one when he wasn’t looking. I will make him sign it next time and then sell it on EBAY.

Needless to say that IOT devices, Software, Hardware and all the functionality and issues associated with them, are going through the roof. Security is essential, and we picked up a new client doing just that, and needing new people. Obviously, DAC is far more in my wheelhouse (with my 21[SUP]st[/SUP] coming up), but I must say that we are moving far quicker into IOT, than I could have imagined and quite happy about the add-on business. The reality is, there are several connections between EDA/Semi and IOT and not only do some of the skills often blend, but many people that left EDA, have moved into IOT. Most of the skill-sets are obviously different, but fortunately for me, I have had several friends who have moved over and given me the opportunity to help them find new people. Now that I have been doing IOT placements for the last several years, and having numerous placements under my belt, I understand the domain so much better and am learning more about this new area, every day. I think the same can be said for domains like AI and Machine Learning.

Hiring is still strong and the H-1 Visa situations (and there are many) have complicated hiring. Engineers on H-1s and thinking about changing jobs, have more to consider in this climate of uncertainty.

As for hiring, the reality is that right now, we are on the high side of what I call the PENDULAM SWING, and that swing changes every several years. I have seen many! The PENDULAM SWING is when either the momentum, advantage is on the Company or Candidates side…right now, the pendulum is at its highest point, with companies needing people and the candidates having more control of their destiny, without the pressure or fear that the opportunity in front of them, is their only option. Companies must take note of this and make sure they do not lose a viable candidate in hopes of finding someone better…it is quite the risk to take today with no guarantees if they will or how long that can take.

I was swamped in back to back meetings preparing for next year. By all indications, next year will start strong, as strong as this year is ending. I for one certainly hope so.

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UMC the Next China Chip Embargo?

UMC the Next China Chip Embargo?
by Robert Maire on 11-03-2018 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

The DOJ last week released a previously sealed indictment against UMC, Jinhua and three individuals for stealing Micron trade secrets. The indictment is very damning of UMC with very specific semiconductor technology files that were stolen by UMC related people then passed on to Jinhua through its joint development with UMC.

DOJ UMC indictment link

The indictment clearly lays out that UMC and individuals were responsible for the actual theft and that Jinhua was the recipient of the stolen goods. Usually the thief is treated more harshly than the receiver of stolen goods. The only thing that has likely kept UMC off the embargo list for now is that they are Taiwan based and are probably cooperating as fast as they can for fear of being put out of business.

To be clear Jinhua/China is far from innocent as UMC was just their henchmen.

UMC is clearly frightened as they have immediately severed all ties with Jinhua and tried to distance themselves. They canceled the DRAM joint development. Continuing the joint development would be pointless anyway now that Jinhua can’t get tools needed from the US to get a fab to work.

We would not be surprised if the stolen Micron information finds its way to other Chinese fabs such as Yangtze. That would likely result in an immediate embargo of the new receiver of stolen goods.

Its also obvious that if UMC gets embargoed that they would be forced out of business at some point as it would be difficult to keep their fleet of US made tools operating in their fab.

However we would not be surprised to see UMC get added to the embargo as it makes logical sense to punish the thief as well as the receiver. After the US initiates the embargo, there will likely be a quick settlement similar to ZTE where UMC will pay a huge fine and be forced to change out management just like ZTE did.

In the meantime, shipments to UMC will be halted just like shipments to ZTE were halted for several months. Just like in the ZTE case, US companies will be hurt as they won’t be able to do business with UMC, so it will be in the interests of the US to settle as well after US equipment companies scream.

Even though UMC is not a big spender it could be yet another down tick of overall Capex going into 2019. We think the embargo weapon could be used after the election when the fallout doesn’t matter, so we would stay tuned.

The stocks
This is obviously a very, very big potential negative for UMC. Its a positive for Micron, and a positive for TSMC. Its obviously a negative for semiconductor equipment companies in the US and ASML as well. We remained concerned as to what China’s response will be in the escalating tit for tat, and then how the US will respond in turn. We don’t think we have seen the last Asian company to be embargoed by the US, we expect more to follow.

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Playing the Long Game with 56G SerDes

Playing the Long Game with 56G SerDes
by Daniel Nenni on 11-02-2018 at 12:00 pm
Categories: 5G, eSilicon, IP

IP has always been a hot topic on SemiWiki with quite a bit of our readers doing the “make versus buy” analysis. SerDes is one of the more difficult “makes” so it is mostly a “buy” analysis made by networking class ASIC architects and a handful of other applications that demand high performance and throughput. Based on the recent traffic patterns, data centers and the coming 5G infrastructure are spiking SerDes interest, absolutely.

The new SerDes twist is “long reach”, a term I was not completely familiar with so I got on the phone with my goomba Mike Gianfagna at eSilicon. He put me in touch with Hugh Durdan, Vice President, Strategy and Products at eSilicon and Matt Burns, Technical Marketing Manager at Samtec Inc. Samtec is a privately held electronic interconnect solutions company that enables the SerDes “reach beyond the rack” implementation – high-speed serial communication over an eye-popping five meters of copper cable.

“eSilicon will demonstrate true long-reach capability for the most demanding system environments in next-generation 25 and 50 Tb/s switches with Samtec Twinax Flyoverä Cable Assemblies. Developers can accelerate their time to market with a high-performance, flexible, easy-to-configure SerDes that targets all of the common Ethernet, Fibre Channel and CPRI standards as well as proprietary rates common in data center and 5G
wireless infrastructure applications.”


5-meter prototype Samtec EBCM Series ExaMAX® Backplane Cable Assembly

Q: What’s different about the SerDes you are announcing?

A: from eSilicon. There are several things that set this device apart. It is a full DSP (transmit and receive) 56G SerDes in 7nm with true long-reach performance. Many other so-called DSP-based SerDes are in reality a hybrid with a digital transmit path but an analog receive path, which impacts performance. We also offer exceptional control and configurability through a graphical user interface that talks to the firmware running on an embedded SiFive processor built into the SerDes. From the GUI, users can access all monitoring features such as non-destructive eye diagrams, SNR & BER, bathtubs, histograms and power measurements.

Q: Regarding this “reach beyond the rack” demo, why is this significant?

A: from eSilicon. Customers want to leverage existing infrastructure and drive higher and higher data rates through legacy backplanes. With our ability to achieve low bit error rates over very long channels we enable customers to extend the life of their existing equipment vs. having to do a “fork-lift upgrade”. Data center customers also want extreme flexibility in connecting systems to each other. Thanks to the highly robust design of our SerDes and Samtec’s cable products, we are able to offer 56G operation over five meters of copper cable.

A: from Samtec. At 56G data rates, trace lengths on a PCB get really short. There are numerous design techniques engineers can use to combat this: advanced PCB laminates, additional PCB layers or clock and data recovery and retimers. Samtec’s solution is to get the signal out of the noisy and lossy PCB into low-noise, ultra-low-skew twinax copper cable as soon as possible. Long length copper cable also enables a paradigm shift in system architecture in the data center, whether inside the rack or beyond that rack.

Q: Tell me a little abou Samtec as my readers may not be familiar with your company. What do you make, where does it fit in the end product?

A: from Samtec. Samtec has been the service leader in the connector industry since our founding in 1976. At our core, we continuously support our legacy flexible stacking headers and sockets. Additionally, we are expanding our high-performance interconnect portfolio into backplane, board-to-board, precision RF, optical engines and high-speed cable assemblies based on our Twinax Flyover™ technology.

Q: Tell me about the long cables. What’s involved in manufacturing them? Why are they so accurate?

A: from Samtec. One key factor is our manufacturing process. Our twinax cables are co-extruded with low Dk FEP dielectric using real-time closed-loop control. This high-precision process eliminates the inconsistencies of individually extruded dielectric twinax cabling. Our cables are grounded via twinax copper alloy, eliminating the need for a drain wire. When combined with our high-performance connectors, the results are 56G data rates over the longest backplane cable assemblies in the industry.

The demonstration will be conducted in the Samtec booth #521 at Supercompute in Dallas from Nov. 12 – 15. Sign up now for a private briefing HERE. And Matt Burns has a nice blog series HERE.

AbouteSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com

About Samtec
Much more than just another connector company, Samtec puts people first with a commitment to exceptional service, quality products, and convenient design tools. We believe that people matter, and taking care of our customers and our employees is paramount in how we approach our business. This belief is deeply ingrained throughout the organization, and means that you can expect exceptional service coupled with technologies that take the industry further faster. www.samtec.com

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Basic Techniques for Managing EDA Business

Basic Techniques for Managing EDA Business
by Daniel Nenni on 11-02-2018 at 7:00 am
Categories: Wally Rhines

The “20 Questions with Wally Rhines” series finale

During the period from 1997, I had the privilege to work with Greg Hinckley, a superb “out of the box” thinker and excellent operational manager. We had such a common view of the world that we almost always agreed upon the best approach to problems and opportunities and hardly needed to confer, although we regularly did discuss almost all significant issues. One of our common attributes was a contrarian attitude. If everyone else was headed in the same direction, opportunity must lie in a different direction. That “Do what others aren’t doing” served as a guidepost for our moves at Mentor.

Following are some of the approaches that Greg or I brought to Mentor, or that evolved from combining our previous experience through interaction together

  • Listen for silence
    • Divisions, product groups, people and managers are always vying for the attention of top management and will usually let you know the good things they are doing
    • If you never hear from, or about, an entity in your organization, there are two possibilities:
      • They are doing nothing worthwhile and make no difference to the company, in which case they should be eliminated, or
      • They are trying to hide something, in which case they should be investigated

       

     

  • Life never gets any easier
    • Ignoring the problems of today only forces you to deal with bigger problems tomorrow
    • Never hope that excess inventory will be any easier to sell in the future than it is today—-write it off now
    • Never assume that an overdue account will find a way to pay you in the future—-it’s even less likely than the present

     

  • What you do infrequently, you do poorly
    • Send an annual invoice, not a quarterly one, for your customers to renew their maintenance contract — the person who deals with it will have to depend upon you to tell him how to handle it
    • Restrict the unfavorable options in your contracts so that customers only deal with them at renewal time. If they have to deal with options regularly, they will become very good at it.
    • Don’t expect your own organization to become efficient at things they rarely deal with—try to automate those things or consolidate them with someone who deals with similar issues regularly

     

  • Making rational decisions based upon data is more important than being right all the time
    • Can you provide a rational basis for why you are making the decision?
    • If you turn out to be wrong, you can retest your rationale and make a better decision next time
    • You may be wrong but at least you’re rational

     

  • Budgeting starts at the top
    • Asking organizations to determine how much they need to spend in the coming year (or quarter, month, day, etc.) is a worthless exercise and a waste of company resources—–the answer will almost always be more than the company can afford
    • Budgeting must start with an objective sales and revenue decision, heavily influenced by those who will have to achieve the sales. Budgets can then be developed that will fit into that sales and revenue plan.
    • Never be tempted to increase the revenue forecast when the cost budgeting pressures appear insurmountable. It will be even more difficult to reduce the budget later when the revenue comes in at (or below) the realistic level that is lower than the optimistic revised forecast.

     

  • In a chip company, management needs to focus first on what is NOT working. In a software company, management should focus first on what IS working.
    • Problems in a semiconductor company (low yields, rapidly falling prices, excess inventory, etc.) can bankrupt you quickly; fixing them has immediate, measurable benefit.
    • In a software company, inventory is unimportant and incremental revenue nearly equals incremental pre-tax profit. Costs are largely fixed because they are mostly people-related and people should not be treated as a variable expense. Incremental revenue is everything so maximum effort should be focused upon using existing resources to produce additional revenue.

     

  • Spend your time doing what others are NOT doing
    • Strategies that are similar to what the other mainstream companies are doing will rarely develop any unique advantage for your customers
    • Needs that are not being addressed offer more opportunity than those that are receiving lots of attention

     

  • For an employee, it is a great success for management to adopt your idea and claim it as its own, even if you are not acknowledged as the creator. For management, it is a great success to see employees act upon your idea and claim it as their own, even if they do not acknowledge you as the source.
  • In technical software, users rarely change the product they are using until it becomes incapable of completing the required task—not when it becomes, slow, inefficient, hard to use or unpopular.
    • Benchmarking with competitive products results primarily in price competition for the customer to secure a lower price to continue using the same software
    • Companies that offer a new and improved product would be better off to use their time by:
      • Participating in benchmarks of new applications that can’t be handled by the older, competitive tool, or
      • Finding new applications for the tool where there is not already an incumbent supplier.

       

     

  • When you acquire an EDA competitor, you don’t eliminate competition—-you create it. In EDA, people are the competitors and they keep doing what they are good at doing by creating new companies whenever the one they are working for is acquired.
  • A new product or service is not really profitable until you receive your first order from a customer with whom you’ve never interacted
    • As long as orders come only from direct effort and interaction by your own organization, you are expending too much money for the revenue you are achieving
    • When word of mouth and third party support start generating orders, you’ve gone viral and have a winning, profitable product

     

  • If you only play defense, your competitor will eventually score.
    • You must counterattack to make your competitor play defense
    • Selling your new, innovative products to your existing customers may be a starting point but success comes only when you penetrate new customers who are usually already served by your competitor
    • Statistically, your competitor will eventually get lucky if he keeps attacking your accounts and is not burdened with defense of his own accounts if you don’t attack them.

     

  • When your company is not number one is a specific market, always compare yourself to the leader(s). When, or if, you become number one, never compare yourself to anyone.
    • Market communication is all about consideration to purchase. You want to be considered when purchasing decisions are made so the association with the leader enhances the possibility of customer comparison of the leader’s product or service with yours.
    • If you are number one in a market, it’s counterproductive to provide your customer with a list of competitors to evaluate, even if you think your product is superior.

     

This is not meant to be a complete formula for successful EDA management. It’s a collection of ideas that aren’t normally discussed in business management training. Yet I believe that these observations, combined with other standard good management practices and an unwavering commitment to ethical treatment of customers, employees and shareholders, helped Mentor to recover from a difficult period and ultimately demonstrate leadership and success in a difficult high technology business.

The 20 Questions with Wally Rhines Series

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Designing Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP

Designing Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP
by Camille Kokozaki on 11-01-2018 at 12:00 pm
Categories: Automotive, IP, Synopsys

As new automotive Advanced Driver Assistance System (ADAS) based product releases intensifies while a more stringent set of safety requirements are mandated, it is not surprising that subsystem and electronic suppliers are looking for pre-designed and ISO 26262 certified IP that can address both imperatives of schedule and safety when being integrated into SoCs. Add to that the necessity of lower power and higher performance, you begin to look at newer architectures that minimize footprint, risk, and effort and maximize the performance at the same time.

Traditionally, the electronic control units (ECUs) for individual ADAS applications have been placed throughout the car: the forward collision avoidance ECU located in the windshield, park assist ultrasonic sensors, and the processor in the rear. ECUs integrate the multiple ADAS applications into centralized domains to combine multiple ADAS functions. The new class of integrated domain controller ECUs utilizes data transferred from the car’s remote sensors such as cameras, LIDARs, radar, ultrasonic, and other sensors to the integrated domain controller for processing by a high-performance ADAS system-on-chip (SoC).

The IP in the integrated ADAS domain controller SoC must also meet the highest Automotive Safety Integrity Levels (ASILs), must be designed and tested for grade 1 and 2 temperatures, and must fully adhere to the automotive quality management process. In addition, to meet the power and performance requirements of the new integrated ADAS domain controller SoC architecture, designers are moving to more stringent process technologies, such as FinFETs, making it even more important to use automotive-certified IP in advanced foundry processes.

A Shift to Integrated ADAS Domain Controller SoC Architectures

According to the August 2016 Traffic Safety Facts Research Noteby the National Highway Traffic Safety Administration (NHTSA), “the nation lost 35,092 people in crashes on U.S. roadways during 2015, a 7.2% increase which is the largest increase in nearly 50 years.” It was analyzed that about 94% of those accidents were caused by human error, and the rest by the environment and mechanical failures.

The opportunity to reduce car accidents is making automotive ADAS even more critical. Automatic emergency braking, pedestrian detection, surround view, park assist, driver drowsiness detection, and gaze detection are among the many ADAS applications that assist drivers with safety-critical functionalities to reduce car accidents. Figure 1 shows an integrated ADAS domain controller SoC with a centralized ECU where data from numerous sensors travels to a central ECU and is then processed via an ADAS processor.


Figure 1: Data from sensors travel to a central ECU and are processed via a vision processor

High volumes of data are driving the adoption of 64-bit processors for automotive ADAS applications. The shift from a distributed architecture to a more centralized ECU is more prevalent, and since the ECUs are integrated, the ADAS SoCs are becoming very complex, requiring the latest semiconductor features, semiconductor process technologies, along with other technologies for ADAS domain controller SoCs:

  • Ethernet manages high data volume including time-sensitive data and reduces point-to-point wiring
  • LPDDR4/4x operates at data rates of up to 3200 megabits per second and beyond, which speeds up the DRAM operations in automotive-grade SoCs
  • MIPI standards like MIPI Camera Serial Interface and Display Serial Interface provide high-performance connectivity in imaging and display applications
  • PCI Express has high-reliability processor-to-processor connectivity for 4G radios or the future 5G radios and external SSDs
  • 5G and IEEE standards, like 802.11p, help provide real-time updates of maps or images to and from the Cloud, and vehicle-to-vehicle or vehicle-to-infrastructure communications
  • Security protocols in hardware and software for data protection to and from connectivity via USB, WiFi or Bluetooth
  • Sensor and control subsystems offload the host processor and fuse sensor data to manage the different type of sensor data provided by the sensors
  • More advanced manufacturing process technologies from the traditional 90-nanometer (nm), 65-nm and 40-nm to more advanced 16-nm, 14-nm, and even 7-nm FinFET processes

Safety-critical applications are significantly increasing the adoption of ADAS SoCs. However, it is required that the ADAS SoC along with all semiconductor components including the IP that is integrated into the SoC meet the ISO 26262 functional safety standard.

Meeting ISO 26262 Functional Safety Standard Requirements

ISO 26262 is a standard that defines the impacts of failures in automotive systems at four different Automotive Safety Integrity Levels (ASILs): A, B, C, and D; ASIL D is the highest level of functional safety. The ISO 26262 standard defines all the processes, development efforts, and standards that automotive development organizations must implement and comply with when developing products for safety-critical systems. A key objective of ISO 26262 standard is to minimize the susceptibility to all types of random hardware failures, including permanent failures or transient failures, by:

  • Defining the functional safety requirements when developing products
  • Applying rigor to the development process
  • Defining a safety culture
  • Implementing safety features to minimize the impact of hardware failures
  • Assessing and analyzing the impact of safety features to ensure mitigation of hardware failures

Industry-accredited inspection companies, such as SGS-TUV Saar, are available to audit products and processes for compliance and certification of ISO 26262.
The ISO 26262 certification process includes multiple steps, policies, and reports and must start from the very beginning of product development. For example, the Failure Mode Effect and Diagnosis Analysis (FMEDA), a report that development teams generate, provides all the information regarding the adherence to ISO 26262 from a functional safety perspective.

Created by design and verification engineers, the report is a critical component of an ASIL assessment, not just for evidence of compliance but also for design targets and a rating assessment at the end of the development flow. Designated safety managers, separately from the development organization, who are fully trained to monitor the development process, milestones and product reviews, ensure all the documentation and traceability is completed throughout the SoC development flow as defined by the standard.

The FMEDA report also includes a summary of the safety features, their development, and verification. It clearly documents the safety features contained in the products and how these products react to the random faults that are injected into them. The FMEDA report is mandatory and is given to all parties involved in the product review process.

How ISO 26262 Certification is Implemented

A standard SoC or IP product development flow starts with register-transfer level (RTL) design, which is then implemented, verified, and validated in hardware and software in the final prototypes. An ISO 26262 compliant development adds additional steps over the standard design process including at the very start when defining a core architecture and specification. Designers define a safety plan that includes safety features and goals. The product team and safety manager review the safety plan and strategy to achieve the designated functional safety for the end application.

It is important to conduct a failure analysis by injecting faults to assess the safety level and the system’s reaction to those faults. The FMEDA shows a fault injection analysis for both permanent and transient faults to assess the impact. The analysis and assessments are clearly documented in the FMEDA report as part of the ISO 26262 certification process along with the safety manuals. This entire process is shown in Figure 2.

Figure 2: An example of a standard SoC or IP design with additional ISO 26262 certification steps and requirements

The safety manual in the ISO 26262 certification process defines the safety features in the product, which is critical to the operation of the product. The standard provides some guidelines as to the effectiveness of safety features that can detect possible failures. Safety features for IP product design fall into three categories: protection mechanisms, replication, and various.

  • Protection mechanisms, such as protecting the interface between the IP in the SoC architecture with the protection of elastic buffers, parity protection on the data path and configuration registers, and error correction code protection for both writes and reads.
  • Replication is a safety feature category that includes duplicating (or triplicating) key modules and using voting logic to ensure redundancy.
  • Various includes parity checks for all the state registers, single cycle pulse validity, various dedicated interrupts, and hot state machine protection for bad states.

The process to meet ISO 26262 functional safety certification is stringent from creating the FMEDA report, designating a safety plan that defines safety features for the target ASIL, to employing a safety manager and documenting and reviewing every milestone with all the stakeholders. In addition to meeting ISO 26262 functional safety requirements, integrated ADAS domain controller SoC development teams and the rest of the supply chain, including the design IP provider, must adhere to automotive reliability and quality requirements.

To meet the automotive reliability standard as defined by the automotive industry, automotive SoCs and IP must be designed and tested to meet very low defect densities which are measured by Defects Parts Per Million (DPPM). The automotive industry has a requirement for less than one DPPM, encouraging designers to set a goal of zero defects per million throughout the automotive product lifetime of 15 years.

Meeting temperature grade is another reliability requirement. For ADAS, the highest level of operating temperature is Grade 1 which requires up to 125 degrees Celsius ambient or 150 degrees Celsius junction temperatures. Each company within the automotive supply chain has a proprietary temperature mission profile to which they design and test their products. SoC and IP designers who are developing products for the different ADAS applications take the temperature mission profiles into account during the development process. Different requirements such as electromigration, transistor aging, and transistor self-heating must be considered against the temperature mission profile for the different devices.

Synopsys offers a portfolio of automotive-certified IP that is ASIL Ready ISO 26262 certified, designed, tested for grade 1 and 2 temperatures, and fully adhere to the automotive quality management process. For information view the DesignWare IP for automotive SoC web page.Based on a technical bulletin posting By Ron DiGiuseppe, Automotivie Segment Marketing Manager, Synopsys

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Wi-Fi Standards Simplified

Wi-Fi Standards Simplified
by Bernard Murphy on 11-01-2018 at 7:00 am
Categories: Ceva, IP, Mobile
3 Comments

In the world of communications, the industry fairly quickly got a handle on a naming convention for cellular technology generations that us non-communication geeks could understand – 2G, 3G, 4G and now 5G, (though some of us could never quite understand the difference between 4G and LTE, at least as those terms are widely and no doubt inexpertly used). This is a nice steady progression, easy for us uncultured masses to remember, with no confusing affixes.

Bluetooth has from the beginning followed a largely similar convention in generation naming from 1.0 up to current BT 5 which drops the ”.0” on the name, not coincidentally aligning numerically with the latest cellular standard. There is a sub-generation of 4.0 (at least initially), known widely as BLE (Bluetooth Low Energy) but we generally understand that this is a low-energy variant on the underlying standard.

Wi-Fi on the other hand soldiered on in geekdom, oblivious to the needs of the masses, by sticking a bewildering array of postfixes on the root 802.11 standard name. I guarantee that no-one in the general public would have any idea what you were talking about if you asked them about say 802.11n, whereas many would profess at least some familiarity with 5G, if with the name only. The Wi-Fi Alliance recognized this wasn’t great for marketing and has recently switched to a much easier naming convention, at least for the most recent generations.

For the newer generations of the standard, 802.11n becomes Wi-Fi 4, 802.11ac becomes Wi-Fi 5 and 802.11ax becomes Wi-Fi 6. For 802.11a/b/g I hear differing stories. Fortune magazine says that these names won’t change. Another contact says (plausibly) that these will be known as Wi-Fi generations 1, 2 and 3. Now isn’t that easier to understand? You may not know what they are but all of us can understand that as you progress from Wi-Fi 1 to Wi-Fi 6, you get better technology at each stage, for which you are prepared to shell out more money (see, that’s marketing).

We’re a bit more sophisticated than that, so what are 4-6? Wi-Fi 4 (aka the “n” version) supports transmission rates 5-6 times faster than the Wi-Fi 3 version, higher reliability and supports MIMO (multi-input, multi-output) where multiple antennae at receiver and/or transmitter further boost reliability and transmission rates.

Wi-Fi 5 (aka the “ac” version), introduced in 2014, increases rates by a factor 2 or more and more efficiently uses bandwidth so more users can be served at speed in one network. However, more efficient usage is only in the downlink. So you can all watch cat videos with minimal buffering but the network bogs down if you all want to share with friends. Wi-Fi 6 (aka the “ax” version), expected to be ratified by the end of 2019, goes one step further, packing multiple users more effectively in both downlink and uplink, serving an expected 4X improvement in throughput in high user density environments (think of a stadium). It also offers a 25% improvement in peak data rate.

So Wi-Fi generation naming is now understandable and mostly aligned with cellular and Bluetooth naming. There’s an apparent disconnect in that the latest Wi-Fi is Wi-Fi 6, whereas cellular is at 5G and Bluetooth is at BT5. But the official Wi-Fi 6 is a year away so perhaps numeric synchronization isn’t too far off. When we’re checking out phones or other devices, we should reasonably soon be able to look for all communications to be at level “N” (maybe 6?) no matter what the underlying technology. That will make life a lot simpler, certainly for me.

I have to thank Franz Dugand, Sales and Mktg Director for Connectivity at CEVA for these insights. Naturally CEVA has a wide range of Wi-Fi IPs across these standards, including Wi-Fi 6, ranging from low-power to high-performance to multi-gig rates. CEVA have been in the Wi-Fi core licensing business since 2002 so they’re very well known and established in the space. You can learn more about their RivieraWaves Wi-Fi platforms HERE.