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Narrow-Band IoT Adoption Grows as IP Options Narrow

Narrow-Band IoT Adoption Grows as IP Options Narrow
by Bernard Murphy on 03-22-2019 at 12:00 am
Categories: Ceva, IoT, IP

Cellular as a method to communicate with the IoT is on a tear for obvious reasons. It’s long-range with no concerns about the lesser reach of Bluetooth or Wi-Fi, it needs no added infrastructure since it already works with 2G/3G/4G (and ultimately 5G I presume) and it’s designed for ultra-low power, supporting those devices expecting to run on a coin-cell battery for 10 years. Commercial cellular IoT networks are blossoming across the world, with a total of 69 launches by 33 operators in 34 counties as of Q4, 2018; and NB-IoT represents 80% of all deployments.

For the big cellular players with in-house communications design expertise this is just another direction to grow. But this is IoT, with lots of new silicon design teams, so the market is likely to be more fragmented than more familiar mobile markets. Many of these players, not all new ventures, lack silicon communications expertise so depend on proven IP to handle the modem.

There used to be a number of providers in the NB-IoT space. CEVA, still very much active, has well-established expertise in cellular and introduced their first Dragonfly NB-IoT solution early last year and their eNB/Rel 14 release of that product more recently. ARM was pursuing NB-IoT with its Cordio platform but announced late last year that they would no longer pursue this direction. Commsolid, another IP supplier in this space, was acquired by Goodix and now makes chips rather than IP. When you’re building an IoT solution, modem chips are one way to go of course but if you want ultra-low power and ultra-low cost (which you generally do for high volume edge devices) it’s a lot more attractive to look at integrated ASIC solutions with the modem in an IP.

Which puts CEVA in an enviable position in serving this expanding market. In their eNB-IoT release they have also added multi-constellation GNSS positioning support, satisfying a need for location services in the majority of new IoT products, whether mobile or fixed (an interesting market wrinkle in itself; I have written about this before). A report from DNB Markets (on Nordic Semiconductor following MWC 19) confirms this. DNB are confident in cellular IoT prospects based on what they saw at the event and noted CEVA’s enabling position in driving competition in this space, citing interest coming from semiconductor companies who don’t have cellular expertise, but also from non-semiconductor companies who want to build their own chipsets and modules.

Nurlink, a China-based IC design company specializing in cellular IoT wireless communications, recently announced the introduction of their NK6010 eNB-IoT SoC powered by CEVA-Dragonfly. This supports all eNB-IoT frequency bands and major global carriers, as required to support certification of devices on any eNB-IoT commercial network around the world. Nurlink’s goal is to drive adoption of their chip in IoT devices such as smart meters, wearables, asset trackers and industrial sensors. They added that they’re now engaged with (mobile network) operators worldwide to certify their SoC.

That certification step shouldn’t be ignored. To be allowed onto the networks, you have to prove your device will play well with others in real life (not just in the lab), according to MNO expectations. If you’re already not a communications expert, this can be daunting. CEVA works hard to make this transition as smooth as possible. While MNOs will not certify IP, CEVA have built their own silicon based on the IP which they have been running through test trials at Vodafone’s IoT Future Lab in Düsseldorf, Germany. Using those open lab facilities which provide a realistic end-to-end live environment of the NB-IoT technology, CEVA connected to the Vodafone NB-IoT network and demonstrated end-to-end IP connectivity with its test chip running an eNB-IoT compliant software stack. This provides a “pre-certification”, not an official signoff but getting as close to compliance as possible short of proving it in the end-product, which should simplify certification for product developers.

Lastly, how low can you go on power? Integrating the modem into your ASIC automatically reduces power from a multi-chip solution. On top of that, Dragonfly is designed for additional power reduction down to a few micro-amps in sleep-mode through dedicated instructions to support power-saving mode (LTE PSM), also through support for LTE eDRX (extended discontinuous reception). Since communication should be relatively infrequent for applications intended for eNB-IoT, getting to 10-year battery life should be achievable as long as you don’t hog power in your application or sensors.

Want to learn more about CEVA Dragonfly? Click HERE.

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ARM, NXP Share Usage, Challenges at Synopsys Lunch

ARM, NXP Share Usage, Challenges at Synopsys Lunch
by Bernard Murphy on 03-20-2019 at 7:00 am
Categories: Arm, EDA, FPGA, IP, Prototyping, Synopsys

Synopsys runs a “Industry verifies with Synopsys” lunch at each DVCon, which isn’t as cheesy as the title might suggest. The bulk of the lunch covers user presentations on their use of Synopsys tools which I find informative and quite open, sharing problems as much as successes. This year, Eamonn Quiqley, FPGA engineering manager from ARM and Amol Bhinge, R&D emulation and verification HW director from NXP, shared their experiences.

Eamonn hails from Ireland where they are great spellers but terrible pronouncers as I think the saying goes (half of my relatives are from the Cork area); pronouncing his name challenged most of the other speakers (it’s “Aymon” by the way). He talked about providing enterprise-class FPGA-based verification at ARM at their Trondheim, Redhill and Austin facilities. Here FPGA means FPGA-prototyping using HAPS.

I’m guessing this isn’t the only enterprise-scale use of FPGA prototyping, but it’s the first I have seen and it’s pretty impressive. We’re getting more familiar with datacenter-based emulation, but this is HAPS prototyping in long aisles of cabinets (I counted at least 12 per side in one image), each with multiple bays of prototyping systems. Looks just like a regular datacenter aisle but without the flashing lights on the cabinets (all the flashing lights are on the systems inside).

The goal of course is to provide global access and resource sharing with resilience (reliability, maintainability) and to optimize use of resources, also to provide flexibility in how these systems can be used. The trick in meeting the flexibility goal is to provide configurability in a controlled/limited range of options. This they accomplish through a number of widely-used (for them) configurations, from 1 to 16 FPGAs. The most heavily used configuration has 4 FPGAs, with each FPGA connected to the others. They add another S104 system to this to extend to support 8 FPGAs, which he said was designed to cover many needs and could be adapted if needed. They use these configs most commonly for CPU debug. For GPU debug they double this up again, allowing for up to 16 FPGAs. Cabling and configurations are designed to support multi-design mode (MDM) to maximize usage at all times.

Debug on FPGA prototypes is always tricky; after all they’re designed for speed rather than deep and broad visibility. Eamonn said that they find that deep-trace debug works really well if you know what you want to look at, capturing up to 2k signals at 17MHz, whereas global state visibility, running at 100k cycles/hour, works well if you know roughly whenyou want to look but not where.

Amol (NXP) opened with an interesting stat. Did you know that every new car contains at least 100 NXP products? I didn’t but it doesn’t sound unreasonable given the level of automation we’re now seeing even in entry-level cars. Rather than talking about specific verification objectives, Amol provided an entertaining and enlightening tour through challenges he still sees in SoC verification.

He kicked off with an interesting statement. Verification tools provide many flavors of coverage, but in his view it is already difficult to address just one type at a reasonable level across multiple domains. He views coverage closure as a long pole for multiple reasons: exclude files for IPs are not as reusable as they should be, it is difficult to deal with tie-offs, constants and parameters (he suggested these need added focus in verification flows) and they’re still struggling to get coverage on IPs.

He made an interesting point –there should be more investment in coverage for IO muxing. I know this is an area already covered as an app by formal tools (in fact he mentioned this area when he discussed formal tools), but I also know that IO muxing architectures can be highly custom, even from design group to design group within a company. I wonder how much effort is required to configure these apps to custom structures? Perhaps so much that many verification groups still resort to simulation-based signoff, in which case coverage metrics would certainly be interesting?

Amol said they worry particularly about false passes, whether checkers, assertions or VIPs may themselves contain errors or may overlook certain possibilities. He noted they had found parameter errors and tieoff errors which should have been caught but were not. He particularly likes Certitude, Z01X and the VC Formal FTA App in tracking down problems of this nature.

Gate-level verification continues to be important (thanks to automotive I believe) and they have found defects at this level which escaped RTL verification. A problem here is turn-around time, in tool run-time (he mentioned running 44 gate-level test cases took many months) and also in debug. He likes shaking out possible bugs earlier in RTL, and he cited VC Formal FXP as a useful tool in this area. But he still sees need for more work in tools and methodologies.

Amol wrapped up with a request for more support in performance verification, particularly along targeted paths such as PCIe to DDR or core to DDR. He mentioned need for more standardization and innovation in this area.
Overall, entertainment and insight into what can be possible for enterprise level FPGA prototyping and where yet more development is needed. And a free lunch – what more could you ask for? To watch the event, click HERE.

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The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part II

The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part II
by Camille Kokozaki on 03-20-2019 at 5:00 am
Categories: IP, RISC-V, SiFive

During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, configurable memory for application tuning and other heterogeneous combination of real time and application processors. Some recently announced products is Huami in Wearable AI, Fadu SSD controller in Enterprise, Microsemi/Microchip upcoming FPGA architecture. Customization comes in 2 forms, customization of cores by configuration changes and by custom instructions in a reserved space on top of the base instruction set and standard extensions, guaranteeing no instruction collision with existing or future extensions, and preserving software compatibility.

Palmer Dabbelt, SiFive Software lead manager compared the complexity of x86 instructions to the simplicity of RISC-V. The current state of RISC-V specifications includes:

  • User Mode ISA spec: M extension for multiplication, A extension for atomics, F and D for single and double precision floating point, C extension for compressed 16-bit
  • Privileged Mode ISA spec: Supervisor, Hypervisor, Machine modes
  • External Debug spec: Debug machine mode software over JTAG

Some resources are listed below [SUP]1[/SUP].

Mohit Gupta, SiFive VP SoC IP covered the SoC IP solutions for vertical markets. SoC/ASIC design is nowadays turning into an IP integration task for cost and design cycle time reasons. No single memory technology is applicable to all designs; power, bandwidth, latency tradeoffs are needed for each custom requirement; SerDes interfaces vary by application and selection is based on power and area optimization. The DesignShare partners provide their differentiated IP at no initial cost for verification and integration, built on top of RISC-V cores and foundational IP helping the development cost and reducing needed expertise.

Krste Asanovic, SiFive Co-Founder and Chief Architect outlined the Customizable RISC-V AI SoC Platform.


The AI accelerator design metrics for ‘inference at the edge’ are cost/performance/power; for ‘inference in the cloud’ latency, throughput/cost matter most. For ‘training in the cloud’, the only metric that matters is performance.

In order to lower cost, power and service latency, Unix Servers can be dropped and replaced by self-hosting accelerator engines along SiFive RISC-V Unix multi-cores.

SiFive’s Freedom Revolution consists of:

  • High-bandwidth AI and networking applications in TSMC 16nm/7nm
  • SiFive 7-series RISC-V processors with vector units
  • Accelerator bays for custom accelerators
  • Cache-coherent TileLink interconnect
  • 2.4-3.2 Gb/s HBM2 memory interface
  • 28-56-112 GBs SerDes links
  • Interlaken chip-to-chip protocol
  • High speed 40+ Gb/s Ethernet

In development E7/S7/U7vector and custom extensions, accelerator bays, 3.2 Gb/s HBM2 in 7nm and higher performance RISC-V processors.

Jay Hu, CEO DinoplusAI rounded out the presentations’ portion of the Symposium. He provided a market overview that showed Deep Learning ASIC having the highest growth

He emphasized that 5G Edge cloud computing and ADAS/Autonomous driving require predictable and consistent ultra-low latency (~0.2ms ResNet 50), high performance and high reliability high precision inference (the CLEAR diagram summarizes the technology platform and positioning.

DinoplusAI provided a latency comparison with NVIDIA Tesla V100 and Google TPU 2

___
[1]Software Resources: Fedora, Debian, OpenEmbedded/Yocto, SiFive blog

Part II

(Part I can be found here)

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Qualcomm Intel Facebook and Semiconductor IP

Qualcomm Intel Facebook and Semiconductor IP
by Daniel Nenni on 03-20-2019 at 12:00 am
Categories: Arteris, IP, NetSpeed Systems, Sonics
2 Comments

What does Qualcomm, Intel, and Facebook have in common? Well, for one thing they all bought network onchip communications (NoC) IP companies. As I have mentioned before, semiconductor IP is the foundation of the fabless semiconductor ecosystem and I believe this trend of acquisitions will continue. So, if you are going to start a company inside the fabless ecosystem make it semiconductor IP, absolutely.

In 2013 Qualcomm acquired the Arteris FlexNoC product portfolio, but Arteris retained existing customer contracts and continued to license and enhance FlexNoC for customers. Qualcomm does not maintain any ownership interest in Arteris and Arteris is nowArterisIP. This was one of my top 5 IP acquisitions along with Denali, Virage, MIPS, and ARM. Not only did Arteris get a VERY nice exit, they parlayed to play again another day. And today ArterisIP has more than 100 employees, more than $20M in revenue, and new technology and products coming out every year. Make no mistake about it, ArterisIP is a fierce competitor and owns the NoC market. We have been covering Arteris since 2011 with 77 blogs viewed close to 300,000 times.

In 2015 Intel purchased the NetSpeed team. We started covering NetSpeed in 2015 and published 26 blogs garnering close to 100,000 views. NetSpeed worked closely with Jim Keller (former Apple) at Tesla. Jim went to Intel and the NetSpeed team followed, simple as that.

In 2019 Facebook acquired Sonics which, from what I have heard, was another team acquisition. It is supposed to be a secret as to where they went but there are no secrets in the fabless semiconductor ecosystem or, more importantly, on LinkedIn:

Sonics Our Next Chapter
More than 20 years ago, we started this business with the belief that the next generation of chips would be defined by networking techniques. Together, we have helped our customers achieve massive success, putting more than 5 billion chips into the marketplace – including, perhaps, the device on which you read this post.

It’s been amazing to see our vision come to fruition. Two decades of development later, we continue to believe that silicon IP solutions are the key to developing groundbreaking products.

Today, we’re excited to announce that we are moving on as a team. As part of this opportunity, we will be winding down our business.

We are deeply proud of our journey from a small Silicon Valley startup to a viable business. We could not have accomplished this without the support of our customers, vendors and our team. Thank you all for believing in our vision and supporting us.
Thank You!

We started covering Sonics in 2013 and published 38 blogs that earned more than 100,000 views. In 2016 Sonics pivoted from NoC to energy processing (power management) so they have not really been focused on NoC but they were definitely still in the game and have an excellent team. From what I have been told, a former Sonics employee already worked at Facebook so that is how it started.

With more than 100 IP companies (that I know of) inside the semiconductor ecosystem you are probably wondering why there were only (3) NoC contenders. I know I was until I talked to some IP folks and found out that network onchip communications is INCREDIBLY hard. Congratulations to ArterisIP, well played.

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The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part I

The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part I
by Camille Kokozaki on 03-19-2019 at 5:00 am
Categories: IP, RISC-V, SiFive

SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip providers and design/foundry services. He stated that, moving forward, the areas of focus will include standards/specs, ecosystem growth, awareness and education.


Sunil Shenoy, SVP RISC-V IP BU, outlined the SiFive elements of leading the semiconductor design revolution with a global presence and reach including 12 offices, 320+ employees and 300+ tape outs so far and expertise in cloud chip design, RTL, physical design, silicon and design platforms on top of having the nucleus of the key RISC-V inventors, and a deep pool of technical and management talent.

The industry adoption for RISC-V is growing from Western Digital’s transitioning of 1 Billion+ cores per year to RISC-V, NVIDIA’s all future GPUs using RISC-V, India adopting RISC-V as national ISA, US DARPA mandating RISC-V in recent security proposals. Design wins are occurring in microcontrollers, wearables, networking, communications and storage.

The current challenges in hardware designing minimum viable products include cost, time and expertise. Currently a leading-edge technology node chip development costs $500M+ for 7nm, takes 2 to 4 years to develop and requires numerous experts in at least 14 disciplines.

In order to accelerate the innovation cycle addressing slow development, increased cost and increasing dependency on many experts, SiFive is reshaping the Silicon business by enabling free and open instruction set architecture, simplifying custom silicon development with templates and providing easy access allowing design in the cloud.


SiFive offers Core IP product Series (E, S, 2/3/5/7 Series, and U 5/7 Series). With 32 and 64 embedded Cores (some multi core capable) and 64-bit high-performance or multi-core application cores. The graph above summarizes the features by application, performance, cost targets of the core portfolio of offerings. Embedded RISC-V development can occur on platform boards such as HiFive 2 and the higher performance Linux capable HiFive Unleashed with expansion board.

Taking a page from the Software industry built on software stacks, SiFive is enabling the creation of a hardware stack where the customization is the focus with the lower stack levels mostly automated reducing cost and improving schedules while maintaining consistency of the design flow process.


SiFive also is enabling a DesignShare ecosystem where third party IP providers allow early integration and verification of their content in a safe cloud-based environment and where SiFive manages the NDA/contract and collects NRE/royalties at the appropriate time simplifying the customer-vendor interface and process.
The figure below shows a sample of the growing list of the participating IP providers. SiFive had the world’s first cloud Tape-out with Microsoft (Freedom U540) and the world’s first RISC-V SSD controller (FADU).


Simon Davidmann, Imperas CEO then followed, addressing getting the best approach from RISC-V with Application-targeted custom instructions. RISC-V adopters can be developing internal cores, are IP providers, creating open-source IP, enabling open source ecosystem as a business, or taking advantage of open-source RTL by incorporating in their products. Two types of adopters can either be creating new architectures with a ‘freedom to innovate’ key requirement or adopters where ‘free’ is the key requirement in order to support research, education, FPGA platforms and open-source communities.

The innovators want to add their own custom extensions and need quality simulation models to debug and analyze the custom instructions and to do RTL design verification. Imperas provides the high-performance CPU models, modeling technology with instruction-accurate verification simulators, tools, debuggers for embedded software development, debug and test purposes. Imperas Fixed Platform Kits (FPK) allow delivery models to customers and partners for pre-sales evaluation and development.


Megan Wachs, SiFive VP of Engineering discussed HiFive Freedom RISC-V Development Platforms. Two SiFive chip platforms include Freedom Everywhere (TSMC 180nm) and Freedom Unleashed (TSMC 28nm) allow customers to customize their SOC by combining pre-integrated configurable SoC architectures, processors, interconnect, off-chip interfaces, on-chip IP from a catalog of SiFIve and DesignShare partner IP providers along with the customer’s own IP. The HiFive1 Arduino-compatible RISC-V Development Board is sold out but a refresh is coming soon. The HiFive Unleashed, the first multi-core RISC-V Linux development board can be ordered on crowdsupply.com for $999.

The Freedom SDK along with SiFive’s Platforms allow configurability of the number and type of cores, includes peripherals and memory map with per-peripheral configurability. SiFive’s Open Source repository allows building one’s own Linux-capable FPGA image.

Ravi Thummarukudy, Mobiveil CEO highlighted RISC-V based platforms for SSD and IoT applications. Mobiveil provides IP and services for high speed interfaces, switches, bridges, memory controllers. To address data center energy and I/O bottlenecks, Mobiveil has a computational storage solution with filtering, scanning, data compression and many other features such as reducing I/O contention and improved power (up to 70% power savings) resulting in improved network performance, lower cost and latency. Mobiveil presented their configurable NVMe SSD Controller platform and reference design and the IoT SoC development platform.

Shafy Eltoukhy, SiFive SVP/GM Custom SoC BU outlined the SSD custom SoC solution with CPU features for the Storage applications using 64-bit real-time addressability for Big Data and real-time applications for Fast Data. AI uses cases for SSD helping in failure prediction, storage tuning, adaptive caching are some examples of what RISC-V can help address.

The Physical Design Platform features a robust silicon engineering methodology with comprehensive checklists throughout the analysis, exploration, implementation and tape-out phases. Custom SoC metrics include 140+ million units shipped with an average 25 DPPM, 300+ tape-outs spanning 100 different end applications for 150 unique customers from tier-1 system companies to startups.

Darrin Jones, Sr Director Technology Development for Azure Cloud Services Infrastructure put in perspective the semiconductor market exceeding 1 trillion devices in 2018 with about 6% CAGR since 2000. Azure boasts 2 million miles of intra data-center fiber, 55 Azure regions, 100+ data centers with millions of servers deployed. The Azure silicon development allows the design execution and verification, place and route and physical verification for advanced nodes such as 7nm with faster product iterations. SiFive, Cadence Design Portal and EDA tools and TSMC VDE are all deployed on top of the Microsoft Azure cloud infrastructure. Performance, price and agility are combining to offer compelling solutions that are seeing adoption.

End Part I

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Surviving in the Age of Digitalization

Surviving in the Age of Digitalization
by Daniel Nenni on 03-18-2019 at 7:00 am
Categories: EDA, Events, Siemens EDA

There was an interesting keynote at DVCon last month. It was titled “Thriving in the Age of Digitalization” which introduced the concept of digital twins for design and production. It was presented by Fram Akiki who is a relative newcomer to EDA but has an interesting history so I will start there.

Fram and I got started in the semiconductor industry at about the same time (early 1980s). He spent 21 years at IBM them 10 years at QCOM and is now in EDA so I asked him about his journey:

After 2 internships with IBM in Burlington, VT, I started full-time with IBM after college as a mixed signal IC designer. My first 10 years with IBM were in design and development roles across mixed signal, logic and microprocessor ICs. I had some very interesting experiences, including working on some of the industry’s first analog CMOS designs for networking and graphics to PowerPC designs for Apple Macs (Remember that?).

During my next ten years at IBM, I held management/executive positions within the Custom Logic group of IBM Microelectronics. I had the opportunity to lead some large engagements with graphics companies like nVidia and processors for leading gaming console manufacturers like Microsoft, Sony and Nintendo. These engagements led IBM to bring up a 300mm facility in East Fishkill, NY and launch the “Common Alliance” technology development platform.

The move to a fabless company (and the West Coast) is what I refer to as my “mid-life crisis.” After many years of engagements and travel to California, I decided to make the move to Qualcomm to experience life further down the supply chain. After a few years leading the foundry operations team, I had the opportunity to be one of the executives helping to lead Qualcomm’s diversification from the smartphone to the broader connected market. Two key projects in this diversification were Gobi (the industry’s first globally enabled cellular module) and Windows on Snapdragon (Qualcomm’s ARM-based processors targeted for compute applications).

Joining Siemens (including the Mentor acquisition) was attractive to me for a number of reasons. Throughout my time at IBM and Qualcomm, I had the opportunity to be a heavy user of EDA software, including Mentor products for IC design, simulation and PCB. My experience has spanned a broad portion of the semiconductor and electronics supply chain. The concepts of Ideation, Realization and Utilization that we talk about as part of the digital twin and digital thread really resonates with not only the challenges I have seen, but the opportunities that I see moving forward.


The digital twin concept really hit home with me after the recent Boeing 737 Max problems. As a pilot myself I can tell you that flying is 99% boredom and 1% sheer terror. The 1% sheer terror for me is stalling the plane. Stalling is when the angle of the wings is too high for the airspeed and the plane literally stops flying and drops out of the sky. The response of course is to jam the nose down to get it flying again (wind flowing under the wings) then resume climbing.

From what I have read, the Boeing 737 MAX planes falsely indicated stalls which the plane automatically corrected by forcing the nose down. The pilots tried to correct but were defeated by the plane’s “failsafe” automation. There have been two similar crashes so the 737 MAX planes are grounded until a fix can be provided. We will have to wait until the investigation is completed but over automation will always be a concern. I have this same concern with fully autonomous cars. There will definitely have to be a full grown digital twin before I trust my life to one, absolutely.

Bottom line:
With the increased end product complexity that semiconductors enable, verification will continue to be the biggest challenge and in some cases it will be a matter of life or death.

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I Finally Understand Brexit

I Finally Understand Brexit
by Roger C. Lanctot on 03-17-2019 at 7:00 am
Categories: Automotive

I have gazed across the Pond in bafflement over Brexit until two days ago. I now grasp the depth and breadth of British anxiety over political and legal ties to Brussels and it boils down to regulatory over-reach.

Yesterday, the European Commission announced that it had adopted new rules “stepping up the deployment of Cooperative Intelligent Transport Systems (C-ITS) on Europe’s roads.” What the commission has actually done is to create a de facto mandate of a 20-year-old Wi-Fi-based wireless technology (dedicated short range communication or DSRC) for collision avoidance and toll paying applications in a manner likely to cost thousands of lives and reverse decades of vehicle connectivity progress.

This is only the latest chapter in the EU’s misguided efforts to use its regulatory power to influence automotive design decisions. A more than decade-long effort to require automatic crash notification technology resulted in an eCall mandate which came into force nearly a year ago requiring all new type approved cars in Europe to come with a module capable of directly calling the nearest public service access point (PSAP) to report a crash – in the event that one has occurred.

The EU eCall mandate placed an undue financial burden on car makers and the PSAPs to support an application based on an outmoded technology specified by the Commission. The objective was to save 1,200 lives annually. The equivalent of this EU mandate would be, in the U.S., for the Federal government to require all cars be outfitted with OnStar. It’s clear to me that neither consumers nor auto makers would welcome such a mandate – in spite of its life-saving potential.

The same sentiment applies to the ITS-G5-related vote this week. The EC wants to mandate a 20-year-old Wi-Fi technology for collision avoidance, toll payment and other applications – creating another financial burden with little anticipated investment return.

There is a lot at stake. The EU, generally and admirably, has half the annual per-100,000 miles fatality rate as the United States. With 1.2M people dying on highways annually on a global basis, preserving that life-saving leadership is essential.

One must ask, though, at what cost? Estimates of the cost of full deployment of DSRC technology in the U.S. run to $100B. Is the EU prepared to take on that burden? A cellular-based solution would offload much of that expense onto the existing wireless carriers, which are capable of recapturing those investments from resulting commercial revenue.
China has a highway fatality rate several times the level of the U.S. China is opting for 5G and C-V2X technology for collision avoidance and other safety and non-safety-related applications. The U.S. Department of Transportation has shifted to a technology agnostic stance, while adopting cellular technology for other safety-related applications.

In spite of growing global ambivalence, if not hostility, toward DSRC-based ITS-G5, the EC saw fit to make a decision likely to have the impact of a mandate. That mandate, will require that cellular modems find a way to communicate with DSRC systems if they want to access prioritized ITS safety messages.

The scope of the EC’s malpractice and malfeasance is enough to cause one to forgive the more than 15M British citizens that voted to Brexit. First eCall. Now ITS-G5. Please, show me the way out of this regulatory-obsessed regime.
How can the current trajectory be reversed?

According to the EC announcement: “The Commission decision takes the form of a Delegated Act. The publication of the Delegated Act is followed by a two-month period during which both the European Parliament and the Council may oppose its entry into force.”

In the words of one observer: “There is very little room for maneuver at this point. Opponents might prepare to trigger the review clause 33 to propose a new technology, but this will eventually require a “backward compatibility” with ITS-G5.”

Status:
European Parliament (EP) text has been officially submitted. EP has now two months to raise an objection on the file, otherwise the Delegated Act is adopted.

Procedure to raise an objection:

An objection against the Delegated Act can be driven and raised via:

1. TRAN Committee – members of the committee vote with simple majority

2. One political party (e.g. EPP) – irrespective of its size – the members of one political group support a motion for objection

3. Alignment of minimum 38 MEPs – (from different parties/irrelevant if members of TRAN) support a motion for objection

4. If (1) or (2) or (3) is successful – text goes for vote in the EP Plenary – to pass the motion for objection 376 MEPs should vote in its favor

  • Next meeting of TRAN Committee when the Delegated Act steps will be decided is April 8.

  • The Member States in the Council should vote with qualified majority in support of the motion to object against the proposal for Delegated Act – this means out of 28 ministers and these 16 ministers should represent at least 65% of the total EU population.

Observers of the European Commission might be distracted by ongoing Brexit debates or might consider the organization somehow irrelevant or unworthy of their attention. One thing is clear: The European Commission is neither irrelevant nor unworthy.

The organization has the power to make decisions with lasting impact both negative and positive. The most dangerous of those decisions are the ones specifying, regulating or mandating particular technologies.

The process leading up to the mandate for eCall created massive uncertainty in connected car technology deployments for European auto makers resulting in delayed deployments, lost investments and time and, certainly, additional loss of life. It also resulted in the introduction of the so-called “dormant SIM,” a device that will only connect in the event of a crash.

The run up to the de facto ITS-G5 mandate similarly injected confusion and delay of new technology adoption in the automotive market. The outcome is likely to be two parallel vehicle-to-vehicle technology paths being implemented simultaneously – ITS-G5 and C-V2X – with all of the cost, complexity and delay that that implies – and a corresponding and continuing loss of life.

So, yes, I finally understand Brexit. I get it. The EC can’t seem to stay in its lane when it comes to regulating automotive wireless technologies. Further participation in the EC is pointless and resistance is futile. Ergo Brexit.

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China Innovation Forum and ES DESIGN West

China Innovation Forum and ES DESIGN West
by Daniel Nenni on 03-15-2019 at 7:00 am
Categories: ESD Alliance, Events, Semiconductor Services

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I had a chat with Bob Smith, Executive Director of ESD Alliance, about the upcoming SEMI conference in China. More than 100,000 people are expected to attend which is beyond my comprehension. SEMICON in San Francisco is maybe 20,000 people which is the largest conference I attend. I’m not sure if the Design Automation Conference ever hit 20,000 but now it is under 10,000. As you can imagine, Bob and staff are having a good time since joining SEMI last year, absolutely.

Bob also mentioned that Registration is now open for the inaugural ES Design West conference which is co-located with SEMICON West in San Francisco July 9-11. This is now the most comprehensive semiconductor/electronics conference I know of and the exhibitors are already lining up (Cadence, Synopsys, Mentor, etc…). Keynotes include one of my favorites Aart de Geus (Synopsys) and Lisa Su (AMD) amongst a host of others.

On a side note take a quick look at this SEMI sponsored “Contact Protocall” trailer and let me know what you think in the comments section.

Back to China, Bob did some digging in their MSS database to see what the trends for EDA and IP look like and came up with the following observations:

  • Between 2015 – 2018 combined sales of EDA tools and semiconductor IP in China grew at a CAGR of 20%+
  • During the same time period, the overall worldwide growth of combined EDA and IP was about 8%
  • Looking just at EDA during that same time period: China 23% CAGR; Worldwide 8% CAGR
  • In 2018, the estimate is that China will have accounted for roughly 8% of worldwide revenue for EDA and IP sales

I will talk to Bob again when he gets back from China but here is a look at the conference abstract and a link to the conference page. It is interesting to note that I know only two of the 20+ presenters so it is not the same-old-same-old.

Abstract:
SIIP China, SEMI Innovation Investment Platform, aims to be one of the most collaborative and influential investment platform for global semiconductor industry by leveraging SEMI global industrial resources, together with global industrial capital and intelligence. SIIP China: SEMI Innovation and Investment Forum, is one of SIIP China’s brand activities held simultaneously with the annual SEMICON China. Besides the Forum, the SIIP China series include Matchmaking Sessions, Theme Discussions, Regular Industry Investment Gathering and Overseas Delegations.

New applications such as Artificial Intelligence, Cloud Computing, Big Data and IoT are bringing big changes to the semiconductor industry. It is expected that 5G will have even more dramatic effects on our daily lives by its higher speed, bigger capacity and low latency. The global semiconductor industry is entering a major period of transition. Being the biggest integrated circuit consumer market in the world, China has been keeping a two-digit growth these years. The trade friction may have added some uncertainty however we look forward to the promising future from the global perspective. No matter how erratic the external environment is, funds, technology, products and talents have always been the key driving forces for the entire eco-system of semiconductor to grow steadily and healthily.

SIIP China: SEMI Innovation and Investment Forum 2019 will focus on the latest policies, diagnose the current situation of the industry, analyze the capital flows and forecast the future. The New-tech Panel will discuss about how deep learning, big data & cloud computing, 5G and manufacturing will bring dramatic changes to the semiconductor industry and what the perspectives of the China market will be.

In 2018, SEMI completed the integration of Electronic System Design Alliance (ESDA). Consisting of major EDA, IP, and fabless companies, ESDA acts as the central voice to communicate and promote the value of the semiconductor design industry as a vital component of the global electronics industry. The ESDA integration brings key capability and further enhances SEMI’s supply-chain coverage and SEMI’s vertical application platforms such as Smart Transportation, Smart Manufacturing and Smart Data as well as key enabling technologies including AI, 5G, and Machine Learning. During the ESDA Executive Panel, leading companies such as Alibaba, Mentor, Synopsis, Unisoc and Cadence will talk about their cutting-edge technologies.

About the Electronic System Design Alliance
The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner representing members in the electronic system and semiconductor design ecosystem, is a community that addresses technical, marketing, economic and legislative issues affecting the entire industry. It acts as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. Visit www.esd-alliance.org to learn more.

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Traceability and Design Verification Synergy

Traceability and Design Verification Synergy
by Daniel Payne on 03-14-2019 at 12:00 pm
Categories: EDA, General, Perforce

The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We’ve all heard the maxim, “Work smarter, not harder.” A white paper just came out from Methodics on a smarter approach, Traceability for the Design Verification Process, so I’ve taken the time to read the 9 pages and then present my findings. The three activities in electronic systems that can be smartly made to work together are:

  • Requirements Management
  • Design Management
  • Verification Management

When you’re designing something safety critical then you’re likely following a standard like ISO26262 and DO-254, where traceability is part of the FuSa specifications. In a utopian world you could follow a linear process, like:

1. Write requirements

2. Perform design

3. Verify that the design meets requirements

4. Ready for production

In reality, we have iterations between step 3 verification and step 2 design, and even from verification back to a change or clarification of the requirements. Remembering what has been verified and on what version of iteration it happened is critical for a smart work flow, so traceability matters a lot.

At the start of an electronic system design the verification of the design is happening in parallel with the actual design, while later on in the process the design has settled down and stopped changing so there’s a shift to completing all verification work, resulting in bug fixes or performance tweaks in order to meet the specifications. So throughout the verification process a smart flow will be able to track each design release with specific verification results. With such traceability your team can reproduce a bug condition and verify that the design fix now passes all regression tests.

In the first diagram shown above you can see the three inter-related activities: Requirement management, Design management and Verification management. What ties all of these activities together is the Percipient tool, because it’s an IP Lifecycle Management platform (IPLM) that can manage IPs, workspaces and verifications. In Percipient you define a project release and that includes all of the IP being used, plus verification tests and results. This is also called the Bill of Materials (BOM).

With Percipient there’s a traceable path from requirements to both design and verification, so when there’s a change in requirements then you know which parts of the design and verification need to be updated as well. Workspaces are built and managed with Percipient, so it always knows with each release what the top-level IP and all lower-level IP blocks are, along with the dependencies. As your team runs verification tests they are kept track of by this IPLM framework, along with release tracking. Here’s a diagram of a design hierarchy and test frame to show the interactions that are tracked by Percipient:

In the lingo of Percipient all of the design blocks, even new content, are called IPs in the workspace. When a test frame runs then this workspace keeps track of that run and the verification results. Instead of relying on human memory about which tests have been run on each IP or workspace, the Percipient tool is doing the verification tracking for us, leaving kind of an audit trail as shown below:

With this methodology you will know the version of the top IP in your workspace, the user running each test, the status of the test, how much run time it took, and any extra arguments that were passed to the test. Each team member using this tool flow will automatically have their verification activities stored by default, then the results can be retrieved as needed.

The automatic benefit of verification traceability means that you can track which tests were run in each workspace created with each release, and know which engineer ran the test. There’s no ambiguity about what tests have been run and verified on your project.

Let’s say that your team is building an electronic system for automotive use and that you will adhere to the ISO26262 requirements, providing proof about:

  • Known versions of all IP blocks
  • Design content of each IP by version
  • All tests run and passed on all IPs, per version

If it took 10 versions to achieve a stable design that met all of the design requirements, then we know that the “IP Tree” of version 10 has a top-level IP in Percipient with all of the hierarchy and low-level IPs. All IP contents as files and versions are cataloged. Verification records detail all the tests and results that passed with version 10. This list can be output from Percipient as a PDF document using a standard format like DITA.

Conclusion
Work smarter, not harder. When it comes to designing electronic systems for FuSa markets you should consider using a tool like Percipient because it connects together requirements management, design management and verification management in a work flow that doesn’t slow down your engineering staff. You get traceability automatically with Percipient, so both design engineers and verification engineers are working toward a common goal by using a single source of truth.

Read the complete White Paper online here.

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