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IEDM 2019 Press Lunch Exposed!

IEDM 2019 Press Lunch Exposed!
by Daniel Nenni on 12-10-2019 at 6:00 am

One of the many benefits of blogging for SemiWiki is the free conference passes and buffet lunches, absolutely. IEDM is one of the more prestigious semiconductor conferences, now in its 65th year, is being held at the Hilton Hotel in San Francisco’s famed Union Square this week. This year more than 1,910 semiconductor professionals registered to see the 238 papers out of 613 submissions. The press lunch is a traditional conference event but IEDM did a very nice job this year so I will start our IEDM coverage here.

The conference theme this year is Innovative Devices for an Era of Connected Intelligence which sounds harmless enough if used for the greater good. The evil applications however are daunting if you think about it which I do constantly. Upon check-in we were given flash drives with all of the papers which will be great reading for the holidays.

The IEDM Publicity Chairs Rihito Kuroda, Tohoku University and Dina Triyoso, TEL Technology Center, America, did a brief overview of the conference followed by a Q&A session. The other conference chairs lunched with us as well which was great for networking.

From the presentation:

Reacurring themes
CMOS technology
3D Integration
Memories (NVM, MRAM, ReRAM, FeRAM)
Neuromorphic computing and devices
Novel materials and architectures
Power electronics
Negative capacitance devices – and applications

CMOS Technology
Session 3 – ALT – Monolithic 3D Integration and BEOL Transistors
Session 7 – MS – Physics of Ferroelectric and Negative Capacitance Devices
Session 11 – ALT – Gate-All-Around Device Technologies
Session 19 – ALT – BEOL and 3D Packaging Innovation
Session 29 – ALT – High Mobility Ge-Based Channel Devices
Session 36 – ALT – CMOS Platform Technologies

Memory Technology
Session 2 – MT– STT-MRAM
Session 15 – MT – Ferroelectrics
Session 22 – MT/EDT – Focus Session: Emerging AI Hardware
Session 28 – MT – Charge Based Memory and Emerging Memories
Session 35 – MT – Selectors and RRAM: Technology and Computing
Session 38 – MT – Memory for Neural Network
Related Session 7 – MS – Physics of Ferroelectric and Negative Capacitance Devices

Power Devices and Systems
Session 4 – PDS – Advances in GaN Power Devices and GaN Monolithic Integration
Session 12 – PDS – Advances in Silicon and Gallium Oxide Power Device Technologies
Session 20 – PDS – SiC Power Devices

We were not allowed to take pictures but I figured one of my lunch was okay. I get the no pictures thing to promote better content in the presentations but it is impossible to enforce and rampantly violated. The other issue brought up in the Q&A is the technical content. Several presentations by big name companies were flagged for empty content, ASML is a notorious offender. The conference organizers took our input gracefully but they should know IEDM is one of the best content conferences on the circuit.

Monday was memory day (MRAM), Don Draper will be covering that in detail. Scotten Jones has a handful of blogs in mind through the holidays so stay tuned to SemiWiki.com for semiconductor coverage by actual semiconductor professionals.

About IEDM
With a history stretching back more than 60 years, the IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems. IEDM is truly an international conference, with strong representation from speakers from around the globe.


As 2019 comes to an end everyone is starting to look at what 2020 holds

As 2019 comes to an end everyone is starting to look at what 2020 holds
by Mark Dyson on 12-09-2019 at 10:00 am

At the moment there are many encouraging signs based on the latest data. Let’s hope this trend continues into 2002 and 2020 is the year of recovery of the semiconductor market. However much depends on how the US China trade war pans out. Last week Trump blew hot and cold saying everything from the negotiations were going very well to saying that he thought there may not be an agreement until after the US presidential election next year. The next round of additional US tariffs are due to go in place on December 15th, so hopefully there will be enough progress to delay the imposition of these.

According to IHS Markit, global semiconductor sales dropped 14.2% in the first 3 quarters of 2019 compared to 2018, but there are signs of recovery even in the memory segment which has dragged down the sector so far. Intel retained it’s number 1 position with 16.3% revenue growth in Q3. For the full year IHS Markit estimate sales will recover slightly and only drop 12.4% compared to 2018.

For 2020, they estimate that NAND flash will grow 19%.  Strong growth in NAND flash and DRAM is forecast as momentum increases for 5G connectivity, artificial intelligence, deep learning, and virtual reality in mobile, data center and cloud-computer servers, automotive, and industrial markets in 2020.

SEMI reported that October global semiconductor sales rebounded in October with a 2.9% month on month increase with global sales of US$35.6billion, but this was still down 13.1% yoy.

Meanwhile the World Semiconductor Trade Statistics (WSTS) organization projects annual global sales will decrease 12.8 percent in 2019, before the market starts to recover with increases of 5.9 percent in 2020 and 6.3 percent in 2021.

SEMI also published it’s 3rd quarter global semiconductor equipment manufacturers billings data showing a 12% growth over Q2, but still down 6% compared to Q3 2018. Taiwan regained the worlds largest semiconductor market status by growing 21% from Q2, and up 34% from a year ago, buying $3.9billion of equipment. Taiwan was ranked third in semiconductor equipment purchases throughout 2018, behind South Korea and China before taking top slot in Q1, and 2nd in Q2 to China. TSMC capex spending accounted for $3.21billion of the total as it invested to support 7nm, 5nm and 3nm technologies.

In addition TSMC announced it plans to spend US$14~15billion on capital expenditure next year, more than half of this expenditure is going to be spent on expanding its 5nm technology to support 5G technology growth. TSMC see a much stronger than expected demand for 5nm & 7nm due to the rapid deployment of 5G around the world. TSMC also confirmed it is on schedule to start mass production of 3nm in 2022.

Taiwanese foundry UMC has announced that it has released 22nm technology for production.

Taiwan’s manufacturing index hit a 15 month high last month due to strong demand from the electronics sector driven by 5G applications.  The PMI increased from 52.7 in October to 54.9 in November with the sub index of new business orders climbed from 52.7 to 61.

In South Korea the outook is not so rosy with export orders of semiconductors decreasing 31% to US$7.4billion in November, the 12th straight month of decline. However market analysts are hopefully of a recovery soon as the Chinese PMI rebounded to 51.8 in November.

Huawei CEO Ren Zhengfei has said it plans to shift it’s US based research centre to Canada. He also said he wants to build some new factory capacity in Europe to build 5G networking equipment.

According to Bloomberg, Chinese semiconductor companies are stockpiling US semiconductor chips in case the trade war worsens and US cuts off access to US technology. In past 3 years Chinese purchases of IC’s has risen strongly, and in the last 2 months imports have been the highest since the start of 2017.

Elsewhere in China Xiaomi and Oppo both announced that they will use Qualcomms latest 5G Snapdragon 865 chip for the flagship smartphones to be released in Q1 next year.

According to the EETimes, ChangXin Memory is emerging as Chinas leading DRAM manufacturer, and is currently running 20,000 wafers per month at its Fab in Hefei. It is currently using 19nm technology to produce LPDDR4, DDR4 8Gbit DRAM products. It has plans to double it’s production in Q2 2020.

In company news, AMS has announced it has succeeded in it’s 2nd bid for Osram having managed to acquire above the required 55% of shares for it’s €41/share bid for the company which values the company at €4.5billion.

Also STMicrolectronics has announced it has acquired the remaining 45% of Swedish silicon carbide wafer manufacturer Norstel AB. Norstel develops and manufactures 150mm silicon carbide (SiC) bare and epitaxial wafers.


Bob Swan says Intel 7nm equals TSMC 5nm!

Bob Swan says Intel 7nm equals TSMC 5nm!
by Daniel Nenni on 12-09-2019 at 6:00 am

Bob Swan is really starting to grow on me. Admittedly, I am generally not a fan of CFOs taking CEO roles at semiconductor companies but thus far Bob is doing a great job. This comes from my outside-looking-in observations and from the people I know inside Intel, absolutely.

Bob did a fireside chat with Credit Suisse at their 23rd annual technical conference which is now up on the Intel website HERE. It is 51 minutes and definitely worth a listen while sorting laundry or getting a mani pedi.

The media really latched onto Bob’s comments about destroying the Intel idea of keeping the 90% CPU market share and focusing on growing other market segments. Dozens of articles hit the internet by people who have no idea what they are talking about so don’t waste your time.

The most interesting comments to me were in relation to TSMC. According to Bob Swan Intel 7nm is equivalent to TSMC 5nm, which I agree with, I just do not remember an Intel CEO ever saying such a thing. He also said that Intel 5nm will be equivalent to TSMC’s 3nm to which I am not so sure. Making a FinFET to FinFET process equivalency statement is fine but from what I was told Intel will be using Nanosheets at 5nm.

Bob also talks about Intel’s transitions from 22nm to 14nm to 10nm in very simple terms. 22nm to 14nm had a 2.4x density target which as we now know was a very difficult transition. From 14nm to 10nm Intel targeted a 2.7x density target which led to even more manufacturing challenges.  Intel 7nm with EUV will be back to a 2.0x scaling target.

Remember, Intel was on a two year process cadence until 14nm. Intel 22nm was launched in 2011, 14nm came 3 years later (2014), and 10nm 5 years after that. Intel 10nm was officially launched in 2019 and Intel 7nm is scheduled for late 2021 which I have no doubt they will hit given the above targets.

TSMC on the other hand delivered 16nm in 2015, 10nm in 2017, and 7nm in 2018. TSMC will deliver 5nm in 2020 and 3nm (also a FinFET based technology) is scheduled for 2022. You can expect 5nm+ to fill in the gap year just as 7nm+ did in 2019. Remember, TSMC is on the Apple iProducts schedule so they have to be in HVM early in the year versus late for Apple to deliver systems in Q4.  Intel just has to ship chips.

Bottom line: TSMC is still about a year ahead of Intel on process technology and I do not see that changing anytime soon, my opinion.

I am at IEDM 2019 this week with SemiWiki bloggers Scott Jones and Don Draper (new blogger) so stay tuned. TSMC is giving a paper on 5nm and of course the chatter in the hallways has even more content.

TSMC to Unveil a Leading-Edge 5nm CMOS Technology Platform: TSMC researchers will describe a 5nm CMOS process optimized for both mobile and high-performance computing. It offers nearly twice the logic density (1.84x) and a 15% speed gain or 30% power reduction over the company’s 7nm process. It incorporates extensive use of EUV lithography to replace immersion lithography at key points in the manufacturing process. As a result, the total mask count is reduced vs. the 7nm technology. TSMC’s 5nm platform also features high channel mobility FinFETs and high-density SRAM cells. The SRAM can be optimized for low-power or high-performance applications, and the researchers say the high-density version (0.021µm2) is the highest-density SRAM ever reported. In a test circuit, a PAM4 transmitter (used in highspeed data communications) built with the 5nm CMOS process demonstrated speeds of 130 Gb/s with 0.96pJ/bit energy efficiency. The researchers say high-volume production is targeted for 1H20. (Paper #36.7, “5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and HighMobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications,” G. Yeap et al., TSMC)

Other TSMC presentations at IEDM 2019

Road map from IEDM:

Note: Intel’s slide with ASML’s animations overlayed, as shown in the slide deck distributed by ASML. Note by Anandtech: “After some emailing back and forth, we can confirm that the slide that Intel’s partner ASML presented at the IEDM conference is actually an altered version of what Intel presented for the September 2019 source. ASML added animations to the slide such that the bottom row of dates correspond to specific nodes, however at the time we didn’t spot these animations (neither did it seem did the rest of the press). It should be noted that the correlation that ASML made to exact node names isn’t so much a stretch of the imagination to piece together, however it has been requested that we also add the original Intel slide to provide context to what Intel is saying compared to what was presented by ASML. Some of the wording in the article has changed to reflect this. Our analysis is still relevant.” Please see the full article in Anandtech for all the details: LINK

Related Blog


Put Uber out of Our Misery

Put Uber out of Our Misery
by Roger C. Lanctot on 12-06-2019 at 2:00 pm

The time may have finally arrived to put app-based transportation options out of commission. The latest report of 3,000 rapes and sexual assaults committed on or by Uber drivers in 2018 highlights a serious and possibly growing shortcoming of gig-type ride-hailing and delivery services: the weakness of driver background checks and the ability of some non-approved drivers to log in as Uber drivers.

The warning signs have been flashing for several years with occasional headlines relating to particularly egregious incidents in far flung cities around the world. But London’s recent decision to not renew Uber’s license – due to 14,000 drives being given by uninsured drivers – specifically reflected on the ability of some Uber drivers to fake their identities when using the app.

Shortly before the London announcement, one of Uber’s commercial insurance providers, James River, dropped the company from its portfolio – with a lengthy explanation during its subsequent earnings call (after taking a hit to profitability). James River’s chief executive officer, Adam Abrams, attributed an extraordinary loss in JR’s latest quarter to Uber and various changes in Uber’s business model.

Abrams did not specify the nature or source of the lack of profitability from the Uber account, saying only that “the risk associated with this (changing) model shifted as the company expanded into new regions, added tens of thousands of drivers and evolved beyond just ride hailing.”

Abrams further noted additional complications from the passage, in California, of Assembly Bill 5, which James River believes will adversely “alter the claims profile for rideshare companies.”

Given the fact that one of the largest sources of operational cost for Uber and its competitors is insurance, one can expect some significant reappraisals ahead for these operators. The always tenuous app-based approach to ad hoc transportation has been simultaneously attractive for its low cost and nerve racking for its dependence on amateur drivers.

To be clear, the risks are serious and significant for both driver and passenger in this ad hoc approach to fulfilling transportation needs. Drivers are enticed by the opportunity to be their own boss and work when they want. Passengers glory in an app-based discounted taxi experience with no need for cash or credit card.

But I have yet to take a ride with Lyft or Uber without hearing half a dozen stories about past misunderstandings or disputes with argumentative or drunk passengers that inevitably involve the police, if all involved are fortunate. This is to say nothing of the male and female drivers getting propositioned by male and female passengers – I am sure the reverse occurs equally frequently.

Suffice to say it’s a hot mess. Suffice is to say I have never heard the same sketchy stories from professional taxi drivers. (I will try not to dwell on my Lyft driver in Las Vegas who showed me the two firearms he carries with him at all times.)

As it becomes increasingly clear to insurers, regulators, and passengers that ride hailing app drivers may not be who they are supposed to be according to the app (can hold true for passengers as well), pressure will grow for either greater regulation, a fundamental change in the business model, or outright sanctions. Cheap taxi rides sounds like a great time until someone gets hurt and it appears that thousands of people may have indeed been hurt.


WEBINAR: Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability

WEBINAR: Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability
by Daniel Nenni on 12-06-2019 at 6:00 am

The symbol for a PowerMOS device in a converter circuit schematic looks simple enough. However, it belies a great deal of hidden complexity. A single device is actually a huge array of parallel intrinsic devices connected together to act as a single high power device. While their gate lengths are small, as with many other MOS devices, the effective gate width (W) can reach up to many meters. Rows and rows of intrinsic devices need to be connected so that the high current for the device is distributed among these with minimal and uniform resistance. The total resistance of the complex internal metal structures and the connected intrinsic devices determine power loss during device operation, having a large effect on circuit efficiency. Inefficient circuits, depending on their application, can require more cooling, cost more to operate or may suffer from shortened battery life.

WEBINAR: Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability

In order to optimize resistance from the device source to drain terminals (Rdson), you need a way to measure it. Unlike top level IC routing, metal structures in PowerMOS devices feature all angle geometry, wide metal, large via arrays and multiple parallel current paths. Extracting this kind of metal structure requires a solver-based extractor that can work with high accuracy on large complex geometry.

To help PowerMOS and converter circuit designers better understand how to accomplish this, Magwel is offering a free webinar on their Power Transistor Modeler (PTM®) which is being used on some of the largest Power MOS devices in production today to predict Rdson and power per layer, and to flag electromigration (EM) violations. The webinar will discuss the types of devices that PTM can be used with. It will also go over the set up and talk about performance and accuracy.

Magwel is a leader in developing tools for analyzing PowerMOS devices using solver-based technology. The PTM family also has tools for analyzing electrothermal properties of PowerMOS devices during their operation, taking into consideration the thermal properties of the die, package and board, and for co-simulation of PowerMOS transient switching behavior in circuit level SPICE simulations.

Sign up for this interesting look into how many leading Power Converter design companies ensure that their PowerMOS devices are optimized for power, performance and reliability. Information and registration for this webinar can also be found at the Magwel website.

About Magwel
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com


New Generation of FPGA Based Distributed Accelerator Cards Offer High Performance and Adaptability

New Generation of FPGA Based Distributed Accelerator Cards Offer High Performance and Adaptability
by Tom Simon on 12-05-2019 at 10:00 am

Achronix FPGA used on BittWare Accelerator Card

We have learned from nature that two characteristics are helpful for success, diversity and adaptability. The same has been shown to be true for computing systems. Things have come a long way from when CPU centric computing was the only choice. Much heavy lifting these days is done by GPUs, ASICs, and FPGAs, with CPUs in a support and coordination role. This is happening in applications such as networking, big data, machine learning and elsewhere. Naturally, edge and cloud data center operators now have numerous choices about which hardware to use to fill their racks. When buying hardware they must anticipate the kinds of workloads that will be handled and even where they will be run. A wrong choice can mean wasted money and resources. What’s needed is processing that is adaptable, can scale and meet diverse and changing workloads.

An emerging trend to address these new workloads is use of distributed accelerator cards. In many cases they fit the power dissipation requirements for their target data centers. They offer scalability to meet rapidly growing demand. They also can incorporate high bandwidth connectivity to ensure that throughput is not limited. Accelerator cards can be fitted with a wide variety of computing engines. However, FPGAs seem to have many desirable characteristics, making them more appealing.

FPGAs are extremely adaptable because they can be reprogrammed as workloads change. They offer extremely high parallelism, which is often necessary for the tasks they are applied to. So, it might seem that the problem is solved – that’s all there is to it. However, the specific architecture of the FPGA and the details of the accelerator card it is placed on make a big difference.

In a recent white paper, Achronix makes the case that there are several aspects of the FPGA and accelerator card architecture that determine how well an accelerator card can perform in demanding applications. They point to the features in the VectorPath S7t-VG6 accelerator card recently released by Achronix and BittWare that uses the Achronix Speedster 7t FPGA. BittWare, a Molex company, has a long history of producing FPGA based accelerator cards. This particular card comes well equipped with 8GB of GDDR6 memory that can operate at 4 Tbps. It also has 4 GB of DDR4. It offers 400GbE and 200GbE Ethernet, as well as PCIe Gen3 x16 that can be upgraded to Gen4 and Gen5.

However, there are some really interesting features in the Speedster 7t that give this accelerator card a significant edge. It contains machine learning processors (MLP) that are optimized for machine learning applications. The MLPs can perform up to 32 multiply/accumulate operations per cycle. Another interesting addition is a 2D Network on Chip (NoC) that supports data movement at 2GHz between the external IO interfaces, FPGA fabric, external GDDR6 memory interfaces and MLPs. A big advantage of this is elimination of the need to use precious FPGA gates to manage data flow to and from high speed interfaces. The NoC handles this, freeing up more of the FPGA core for application related uses. There are also direct clock and GPIO interfaces, as well as OCuLink, to provide the ability to combine accelerator cards or interface with legacy equipment.

For customers who want a turnkey server solution, BittWare even has ready-to-go servers with up to 16 VectorPath PCIe cards on Dell or HPE servers with development software to allow customers to rapidly deploy this new technology. The white paper also hints strongly at a forthcoming IP offering of the Speedster 7t FPGA fabric, which would allow customers to build their own ASIC based accelerators.

The Achronix white paper makes interesting reading. It includes a summary of the accelerator board market, and its future growth potential. It also dives into the specifics of the BittWare offering and the details of the Acchronix Speedster 7t FPGA. I suggest going to the Achronix website to download this interesting document.


Rwanda is Building Africa’s Very Own Silicon Valley – Known as Kigali Innovation City (KIC)

Rwanda is Building Africa’s Very Own Silicon Valley – Known as Kigali Innovation City (KIC)
by Nicky Verd on 12-05-2019 at 6:00 am

A multi-billion dollar project inspired by America’s Silicon Valley for the production and development of technological advancement is being built in Rwanda’s capital, Kigali.

Kigali Innovation City

This is an innovative effort, the first of its kind on the continent. The aim is to build a critical mass of talent, research and innovative ideas that will transform the continent. The government of Rwanda plans to attract both domestic and foreign universities, technology companies, biotech firms, agriculture, healthcare and financial services; infrastructure including commercial and retail real estate.

According to Paula Ingabire, Rwanda’s Minister of ICT and Innovation, the KIC project has set itself the objectives of creating more than 50,000 jobs, generating $150 million in ICT exports per year and attracting more than $300 million in foreign direct investment.

The project started in 2018 and its said to cost $2 Billion US Dollars. I believe this is the kind of initiative the rest of African leaders/governments should emulate instead of promising jobs that no longer exist to the masses as a means to secure more votes.

Times are changing, and so should the approach to solving economic/social ills. The new era being ushered in by Industry 4.0 demands that people be given the right resources/infrastructure, and in so doing, they’ll create their own employment/livelihoods. As mentioned in my new book  Disrupt Yourself Or Be Disrupted, “You can do more today with your life having just an internet connection and that’s an opportunity our parents and grandparents never had.”

And so, Rwanda is committed to becoming the gateway to a technologically developed Africa and it is realizing this with a consistent development strategy that is a sight to behold. Rwanda is one of the world’s fastest-growing economies and leads the African continent in technological advancement and infrastructural development.

Rwanda is yet again preparing to build a $5 billion US Dollar model green city in Kigali from January 2020. This will also be the first in Africa – to focus on green technologies and innovations for green and climate-resilient urbanization.

Many African nations complain about the negative impact on their development resulting from the legacy of colonialism which positioned Africa to be perpetually at the mercy of the Western World however Rwanda has chosen the noble and daring act of rewriting the script of her future. Rwanda is consciously positioning herself for the Fourth Industrial Revolution(4IR) and genuinely giving the future generations tools to succeed in an era of exponential technologies.

In the 21 years since the 1994 genocide, Rwanda has come a long way. Despite a near-total lack of natural resources, the country continues to rise, making it one of the fastest-growing economies in the world. One key to this turnaround is technology. It seems that President Paul Kagame; also known as the “digital president” is positioning the country for an extraordinary leapfrog in the Fourth Industrial Revolution.

“We want technology to sort of permeate all the professions, all the jobs,” says Jean Philbert Nsengimana, Rwanda’s Minister of Youth and Information Technology.

It’s really interesting to note that Rwanda has a Minister of Youth and Information Technology. This means the country is paying attention to its greatest asset – the youths!

Hopefully, the rest of the continent is watching and learning from Rwanda – a purposeful Government and leadership abreast with what is trending, positioning itself to be a reference point for economic advancement and innovation through cutting edge technology

In my new book, Disrupt Yourself Or Be Disrupted, I mentioned that “Africa’s hopeful transformation lies in viewing entrepreneurship as a viable career path, not only as a last resort for joblessness. As the Fourth Industrial Revolution takes centre stage, Africa needs more entrepreneurs, innovators, start-ups, disruptors, inventors, pioneers and thought leaders and we cannot afford to be reckless about what will transform our continent.”

The time for disruption is now! The Fourth Industrial Revolution is Africa’s greatest opportunity to leapfrog and compete on a global scale.

“The Fourth Industrial Revolution is not about technology; It is about a new era, new ways of thinking and new ways of doing business” ~Nicky Verd

We have a continent to build! We are the heroes we’ve been waiting for. Wakanda is Real!

Get My New Book “Disrupt Yourself Or Be Disrupted” – A book born out of an authentic passion to ignite human potential in an era of Artificial Intelligence(AI). You cannot out-work, out-learn or out-efficient the machines but you can out-human them!

Available on Amazon


Intersection of Technologies

Intersection of Technologies
by gskahlon on 12-04-2019 at 10:00 am

Monitoring brain activities and translating the signals into commands to control devices is truly a ‘Cool Idea’. Nurio is the latest winner of Protolabs’ Cool Idea award – a $250k grant towards manufacturing services to rapid prototype and accelerate the product to the market. (Click here to learn more about Cool Idea Award)

What amazes me the most is the close intersection of different hardware and software technologies that have enabled this and similar devices:

Integrated Chip (IC) miniaturization – As smart phones continue to push the form factor of ICs (thanks to Moore’s law), we are able to fit more functionality in our pocket. This has led to an ecosystem of devices that can be re-purposed for new innovative application – Brain computing interface (BCI) being one of them.

Moore’s Law Graphic

Computing Power – Instead of having a separate computer to crunch the massive amount of data from the device, we can use the super computer in our pocket (smart phone)

Here is one of my favorite fact – Apple recently released their new iPhone with an A13 chip. This chip has 8.5 billion transistors. In comparison, the entire cluster of 117 servers for Toy Story (1995) had roughly 1 billion CPU transistors. (Image below. source: podcast from @a16z). So you have 8.5 times the processing power in your pocket then what Pixar had to make the first Toy Story movie. 🤯

Steve Jobs Toy Story CPUs

Artificial Intelligence (AI) – The hardest part with this amount of data is finding the signal from the noise. However now with self learning systems, we are able to process tons of data without any pre-processing from humans.

Protolab’s digital platform

Digital Manufacturing – Protolab’s digital platform allows innovators to iterate their design, build prototype in days to get user feedback, get expertise advice to select material and reduce cost to control product entry price point for increased market adoption. They are also able to scale production with demand. This could be done within few weeks to months! Without digital manufacturing, this speed does not exist and entrepreneur are stuck in long product development cycle while other technologies continue to progresses potentially risking their product obsolete by the time they bring it to market.

Digital Manufacturing

Being a tech geek, it is beautiful to see when innovators are able to perfectly bring all these different technologies together to build devices to advance the human race.


Arm Inches Closer to Supercomputing

Arm Inches Closer to Supercomputing
by Bernard Murphy on 12-04-2019 at 6:00 am

Summit supercomputer

When it comes to Arm, we think mostly of phones and the “things” in the IoT. We know they’re in a lot of other places too, such as communications infrastructure but that’s a kind of diffuse image – “yeah, they’re everywhere”. We like easy-to-understand targets: phones, IoT devices, we get those. More recently Arm started to talk about servers – those mega-compute monsters, stacked aisle by aisle in datacenters. Here in our view they were taking on an established giant – Intel. And we thought – OK, this should be interesting.

First moves were promising: Qualcomm was going to build servers, Cavium/Marvell, Ampere, Fujitsu and others jumped in. Then Qualcomm jumped back out. Turned out performance didn’t get anywhere near Xeon and (AMD) Epyc performance. We smiled smugly – I told you so. No way an Arm-based system can compete with real servers.

We didn’t feel quite so smug when AWS (Amazon) announced that A1 instances were now available for cloud compute. These are built on Arm-based Graviton processors, developed in AWS. Still, we argued, these are only half the speed of Xeon instances. Half the power also, but who cares about that? So we’re still right, these instances are just for penny-pinching cloud users who can’t afford the premium service.

The challenge for many of us in the semiconductor/systems world is that we see compute in terms of the tasks we know best – giant simulations, finite element analyses, that sort of thing, where needs are all about raw compute performance and I/O bandwidth. But the needs of the real world far outweigh our specialized applications. Most users care about video streaming, gaming, searching and of course AI inferencing (still bigger on the cloud than at the edge per McKinsey).

When it comes to those kinds of application, it turns out that raw performance isn’t the right metric, even for premium users. The correct metric is some function of performance and cost, and isn’t necessarily uniform across different parts of the application. If you’re serving videos at YouTube or Netflix volumes, even as Google or Netflix, you still want to do so profitably. Arm instances can be more cost-effective than Intel/AMD in such functions.

So Arm found a foothold in servers; how do they build on that? They have a roadmap to faster cores, a progression from the Cosmos platform (on which the Graviton processor was based), into the Neoverse platforms, starting with N1, each with a ~30% improvement in performance. AWS just released a forward look into their next generation A2 instances, based on N1, with (according to Arm) a 40% improvement in price performance.

They’re also pushing towards an even more challenging objective: supercomputing. Sandia labs is already underway on their experimental Astra roadmap, using the Marvell/Cavium Thunder X platform – Arm-based. An interesting start, but then where are all the other exascale Arm-based computers? By their nature there aren’t going to be a lot of these around, but still, you might have expected some chatter along these lines.

Now Arm is priming the pump more in this direction through a partnership with NVIDIA. NVIDIA GPUs are already in the current fastest supercomputer in the world, the Summit at Oak Ridge National Labs. They announced earlier in the year that they are teaming with Arm and Arm’s ecosystem partners, to accelerate development of GPU-accelerated Arm-based servers, and to broaden adoption of the CUDA-X libraries and development tools. Cray and HPE are also involved in defining a reference platform.

You can see a picture emerging here, building more footholds in the cloud and in supercomputing, establishing that Arm has a role to play in both domains I’m pretty sure they’re never going to be the central faster-than-anything-on-the-planet part of computation, but clouds and supercomputers have much more diverse needs than can be satisfied by mainstream servers alone. You want the right engines at the right price-point for each task – top-of the-line to compute really fast where that’s what you need, Arm-managed GPUs for massive machine-learning training or inferencing, Arm-powered engines for smart storage and software-defined networking, and application-optimized engines for web-serving and other functions where performance per dollar is a better metric than raw performance.

You can get more info from Arm’s announcement at the SC ’19 conference.


Webinar on coping with the complexities of 3D NAND design

Webinar on coping with the complexities of 3D NAND design
by admin on 12-03-2019 at 10:00 am

In order to beat Moore’s Law NAND Flash memories have moved from a planar topology to 3D construction. This allows for increased memory sized in much the same way a multistory building provides more building square footage on the same size building lot. Just like in building construction, adding a third dimension to the mix increases complexity in almost every way. Some 3D NAND designs go up to 64 devices high. Observing the problems encountered is a bit like watching a 3D chess game. The only way to understand all the read and write behaviors along with issues like program disturb errors that cause a shift in the threshold voltage of adjacent memory cells, is to use advanced modeling methods to simulate what is happening at the device level.

Silvaco recently presented a webinar on the topic of optimizing the select gate transistor in 3D NAND memory cells. The presenter, Dr. Jin Cho, did an excellent job of providing an overview of the construction and operation of 3D NAND Flash memories. He started by describing the topology of 3D NAND ICs, and then he covered some of their fabrication related issues. Among these are bowing that may occur during the high aspect ratio etch of the channel. The staircase region at the end also presents challenges during its construction. Finally, there is film deformation that can occur after the slit etch.

Role of select gate transistor on Erase

Dr. Cho talked about the large top and bottom select gate transistors, and the dummy gates that are required to prevent coupling to the active gates. Together they consume a lot of the column height, limiting space for the active gates. However, the best way to precisely know the optimal topology is to perform detailed TCAD modeling and simulation. For the purposes of the webinar Dr. Cho constructed a full 3D structure for simulation. It included implantation and diffusion. He omitted oxidation and nitridation. To properly model disturb phenomena he included at least 4 cell strings. For the TCAD device simulation he used the FN tunneling model for the write/erase operations, band to band tunneling model for the gate-induced-drain-leakage (GIDL) characteristics, and trap assistant leakage model for leakage current simulation.

Silvaco offers a cell mode simulation for the circular shape of the channel region. Without this, using voxels, a choice must be made between slow but accurate results with  ~1nm resolution, or fast but inaccurate results resolution at ~5nm. Cell mode means no tradeoffs with high precision shape and fast computation times. He emphasized that this approach fits well with 3D NAND simulation needs.

The webinar then covered the details of the cell characteristics. After this the simulation for worst case read D0 and D1 conditions are discussed illustrating how the entire bit line contributes to cell behavior. The program operation was analyzed as well to set the stage for talking about program disturb. In 3D NAND there are three cases for program disturb – X, Y, XY. The net result of Dr Cho’s detailed analysis presented in the webinar is that using dummy gates strongly improves program disturb behavior. Also, it is shown that increasing the channel in the bottom select transistor reduces leakage and increases GIDL which has beneficial effects on erase speed.

The webinar, which can be easily viewed in replay, goes into much more depth than can be provided here, and is easily worth viewing if you are interested in the details of 3D NAND performance optimization. I suggest going to the Silvaco website to view the replay in its entirety.