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DRC+, DFM, CMP, Variablility

DRC+, DFM, CMP, Variablility
by Daniel Payne on 02-10-2011 at 12:42 pm
Categories: Arm, EDA, GlobalFoundries, Siemens EDA

When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.

(United States Patent 6661699. Inventor: Walker, Darryl Gene)

DRC+
Today with the dominant fab-light model most IC designers need to work with a foundry to receive DRC decks plus DFM rules and guidelines.
Because DRC complexity have exploded to over 1,000 rules at the 65nm node and below, we must consider new techniques like 2D pattern-matching to speed up the checking.

DFM
Design For Manufacturing now covers multiple EDA tools, even Place & Route. The width of interconnect is now dependent on adjacent wires in two dimensions:

CMP
Chemical Mechanical Polishing is commonly used to make IC layouts more planar, which improves yield by keeping the layers parallel to the substrate. There are IC layout rules to ensure that CMP will work properly.

(IC cross-section. Left: Without CMP, Right: With CMP)
Variability
Drawing a transistor gate as a rectangle isn’t how it really ends up in silicon. By providing feedback to the circuit designer on how the non-ideal transistor will perform, it gives a more accurate way to simulate circuit performance.

On March 10 in Santa Clara at the EDA Tech Forum you can meet and learn from experts in these topics of: DRC+, DFM, CMP, Variabiity

This is an all-day seminar, and best of all the price is free. Just visit the site and register online to reserve your spot.

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Keynote Address at the 16th Asia and South Pacific Design Automation Conference

Keynote Address at the 16th Asia and South Pacific Design Automation Conference
by Daniel Nenni on 02-06-2011 at 6:23 pm
Categories: EDA

"Managing increasing complexity through higher-level of abstraction: What the past has taught us about the future" Dr. Ajoy Bose, Atrenta CEO

Here is the abstract:
Time to market and design complexity challenges are well-known; we have all seen the statistics and predictions. A well-defined strategy to address these challenges seems less clear. Strategies to optimize the chip implementation flow, including approaches such as transistor-level optimization abound. While these techniques contribute to the solution, they all miss the primary force of design evolution. Over the past 30 years or so, it has been proven time and again that moving design abstraction to the next higher level is required if design technology is to advance. In this keynote presentation, a new EDA model will be presented, examples of past trends will be identified, and an assessment will be made on what these trends mean in the context of the current challenges before us. A snapshot of the future will be presented which will contain some non-intuitive predictions.

The talk basically looks at semiconductor design and EDA from a historical perspective and highlights that things always move to a higher level of abstraction to address complexity. IP was the most relevant example used as it continues to have a profound impact on the semiconductor design manufacturing ecosystem. You will be hard pressed to find a modern semiconductor design, in production today, without a reusable block, whether commercial or proprietary.

In fact, commercial semiconductor IP revenue jumped 30%+ in 2010, according to EDAC, and soft (abstracted) IP is a significant part of that number. Interestingly, semiconductor IP growth tracks nicely with semiconductor industry growth (30%+) and not EDA revenue growth (0%). Take a look at the SIP and EDA business models and you will see why (semiconductor IP is success based and EDA is not).

The talk also focused on platform based design and IP reuse as critical items to tame complexity and spiraling design cost. Ajoy then talked about a "new breed" of EDA company – called "5th generation EDA" to address these requirements. Check out the Atrenta newsletter HERE, it is a company you definitely want to watch!

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TSMC Raises The Semiconductor Bar With 450mm!

TSMC Raises The Semiconductor Bar With 450mm!
by Daniel Nenni on 02-03-2011 at 2:34 pm
Categories: Foundries, TSMC

During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!

According to Morris Chang:

“For 2011, we expect the overall semiconductor market excluding memory to grow by about 7%.”

I still say 7% is low and hold to my double digit prediction for semiconductor growth in 2011. New phones, tablets, and communications products will continue to drive semiconductors this year and next.

“We expect the foundry market to grow by about 15%, and we believe TSMC will grow more than 20% in U.S. dollars.”

On the previous conference call Morris Chang predicted 14% growth for TSMC in 2011. In my follow-up blogs I predicted 20%+ 2011 growth for TSMC. Morris and I are now aligned so my prediction stands, TSMC will again post incredible numbers in 2011.

“I want to say a few words about the 450-millimeter wafer manufacturing. Our first 450-millimeter pilot line is planned at our Fab12 Phase VI, starting with 20-nanometer technology. The timing of pilot line will be around 2013, 2014. Our first 450-millimeter production line is planned in around 2015, 2016,” said Morris Change, chief executive officer and chairman of TSMC

This is déjà vu of the 200mm to 300mm transition. There was endless debate and lots of 300mm doubters until TSMC put a stake in the ground and started building the first 300mm fab. TSMC, Intel, Toshiba, and Samsung all publicly support the transition to 450mm citing both important technological advancements as well as significant capacity increases to meet the needs of future smartphone and tablet users around the world. One 450mm wafer should yield more than twice as much compared to today’s 300mm, and well over four times the number from yesterday’s 200mm.

Unfortunately, once scheduled for a 2012 launch, the transition to 450mm wafers has been delayed due to both doubters and the financial meltdown. In 2009, the semiconductor equipment manufacturers, the enablers of 450mm wafers, lost more than $1B and released 30%-40% of their workforces. But with the current semiconductor industry upswing with foundries like TSMC and UMC operating at maximum capacity, 450mm semiconductor manufacturing is now in sight.

GlobalFoundries is the last public 450mm foundry doubter. According to Thomas Sonderman, Vice President of manufacturing systems and technology at GlobalFoundries:

“The rush to 450mm suggests a lack of ideas for improving fab productivity. At GlobalFoundries, we see a tremendous amount of headroom left in the 300mm process. We are tapping our expertise in lean manufacturing to extend the lifecycle of the industry’s current 300mm ….”

In my opinion this is one of the main drivers for TSMC and 450mm, the GlobalFoundries challenge. It has definitely raised the innovation bar for TSMC and they have reacted accordingly. TSMC will build a 450mm fab and the semiconductor equipment manufactures will accommodate their most valued customer, believe it. Look for the FabClub (GlobalFoundries, Samsung, and IBM) to announce 450mm fabs in the coming months as they have no other choice if they want to compete with TSMC.

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DesignCon 2011 Trip Reports!

DesignCon 2011 Trip Reports!
by Daniel Payne on 02-01-2011 at 1:38 pm
Categories: EDA

Cadence at DesignCon 2011

I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.

Silicon Realization Trends and Challenges:

Silicon Realization – end to end digital flow. No more foucs on just point tools, instead we’re organized end to end flow based. Top 3 of best tool innovations at DesignCon (nominated).

Challenges (2) – Japanese key customers confirm the needs. How to get faster ARM cores, .8 to 1GHz.

Low Power, Mixed Signal – more automation (power shutoff, dynamic voltage scaling), tool interoperability

Adv tech – 3D, 20nm. How to make mobile video? There are node Migration risks.

3. Traditional tools are breaking, convergence issues (Physical synthesis), The 3D tool flow is very different from previous tool flows. Abstraction models at chip and package levels are new.

4. Intent-abstraction-convergence. Supports 28nm flow. Faster P&R (2x). New power intent architect (graphical UI), shipped in December.

Abstraction (patented) – gate level netlist analysis with logic and physical, compress db size of 80%, stores more efficiently. Renesas paper has numbers on db size. Hierarchical modeling of IP for power budget.

Convergence – Physical synthesis, ECO flow improvements to reduce the rework back into RTL. Promote an all-Cadence tool flow.

Litho hot spots, how to fix? In the past simulation approaches to litho with long run times. InDesign DFM from Clearshap a few years ago. DRC+ is a new technique with pattern-based, see Global Foundries press release. DFM and Litho is not an afterthought, using DRC+ and InDesign together.

Q: How does this compare to Mentor’s approach of DFM in the loop?
A: No comment on Mentor.

IC (Virtuoso), Package (Allegro) – all play together for 3D design.

Mixed-signal – how to do timing? Build macros. Tool now on the fly can traverse digital and do STA, mixed-signal optimization is done on the fly. Analog is still transistor-level optimization.

5. How to design 3D and analyze. 3D config file ties all the domains together. Beyond just 2 to 3 die stack, expect 7 stacks. Concurrent design now possible. Allegro shows the 3D view for 3D design. Interposer example has multiple routing levels in it. Foundries have new design rules (TSMC, Global Foundries) for 3D.

Thermal plot showing 2D and 3D views of gradients. Thermal results fed back to timing.
Q: How does this compare to Gradient DA or Apache DA?
A: No comment on competition.

6. ARM relationship, they used a Cadence flow. Out of box scripts, use Cadence services to increase the CPU core speeds.

8. Customer feedback

Q: Summary – can I still use OpenDoor partners?
A: Yes, We have a framework with OA, and CPF standards.

3D white paper is available.

DRC+ paper with Global Foundries

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Semiconductor Quidditch @ DesignCon 2011!

Semiconductor Quidditch @ DesignCon 2011!
by Daniel Nenni on 01-26-2011 at 10:09 pm
Categories: EDA, Events

Process Design Kit (PDK) development is one of the most entertaining things to watch in the semiconductor design world. It is kind of like the Golden Snitch in the game of Quidditch. No matter how rough EDA vendors play the game, no matter what the score is, it’s the vendor that “gets” the Golden PDK Snitch that wins the semiconductor process node. Vendor specific PDKs allow an EDA company to dominate a given market segment. Today, analog design PDKs are dominated by the Cadence Virtuoso franchise. Virtuoso maintains an 80%+ market share by locking customers into Cadence proprietary PDK technology, specifically, the Cadence PCell (parameterized cell) and the Skill scripting language.

PDKs for Analog IC Design – A Stakeholder Discussion
Speaker:Daniel Nenni (Moderator) (Moderator, SemiWiki), Mass Sivilotti (Chief Scientist, Tanner EDA), Yaron Kretchmer (Senior Manager, SJ Backend CAD, Altera), Tom Quan (Design Methodology & Service Marketing (DMSM), TSMC), John Stabenow (Group Director, Custom/Analog Product Management, Cadence Design Systems), Ed Lechner (Synopsys), Samir Chaudhry (TowerJazz Semiconductor)
Date/Time:Wednesday (February 2, 2011) 3:45pm — 5:00pm
Location (room):Ballroom F
Track:Special Events
Formats:75-Minute Technical Panel
Audience level:Introductory

PDK’s are THE communication link between semiconductor design and manufacturing. For every process node there will be multiple PDKs to support the different design types (Analog, Digital, etc…), different tool vendors and formats. Multiply that by dozens of process variations and you get millions of dollars in overhead expense passed onto the consumers of electronic devices, or more specifically, passed on to the parents of those consumers!

Presentation Abstract:
Process Design Kits (PDKs) are an essential component of the Analog Designers’ toolkit. Recent industry initiatives aimed at defining PDK standards and reducing the PDK maintenance overhead have been largely focused on process nodes that are biased towards leading-edge digital designs. The result is that Analog Designers are at risk of having the standards and process rules not meet their requirements. This panel discussion will outline and explore some of the key challenges facing Analog Designers related to PDKs. Opinions, perspectives and proposed mitigation strategies will be expressed by representatives from key stakeholder groups: Designers, EDA Tool Vendors, and Foundries.

This is your chance to be heard and interact with both sides of the PDK equation: Foundries, EDA Vendors, and even a power PDK customer, Yaron Kretchmer (Altera). Trust me on this one, adding Yaron to this panel is like starting your family BBQ with rocket fuel. There will be no slides, the panelists will make short position statements and we will take questions from the audience. Here are the position statements from TSMC, Cadence, TowerJazz, Tanner, and Synopsys:


 “Three key attributes of PDK: (1) completeness, (2) robustness, and (3) availability. For analog design, completeness means having the right devices/components in the PDk for transistor-level design, and basic building blocks, such as current mirrors, diff pairs, etc. to speed up the design. Robustness means high quality, i.e. fully-qualified/validated by foundries to work with a set of pre-qualified design tools. Availability means the right PDK for the right process node is available when you need it for the next design. The PDK also must be interoperable between several EDA analog design tools/solutions, so designers can pick and choose the best-in-class design tools without sacrificing design quality and productivity or having to wait for the right PDK to be available.”


“EDA suppliers know that accuracy is the #1 necessity for the analog designer. The analog designer needs a tool set that can accurately reflect the probable realities of the silicon. Each vendor takes a different approach, both in the front end design and the back end design, to achieving this goal. It can be enhancing the “by hand” needs of the designers all the way to automation and optimization, and all EDA suppliers seek to differentiate their offerings. This is why high precision, high quality PDK’s will be unique to every vendor, and will be honed to fit like hand and glove with the software tools used for creation and implementation of the design.”


“Analog-intensive, mixed-signal (AIMS) ICs are defined as chips with a large analog content and a small digital content, and are designed for applications ranging from precision analog to high-performance radio frequency (RF) transceivers in communication systems. Over the last decade, the technology needs of AIMS ICs have diverged from those of digital ICs. The AIMS IC technology migration towards advanced nodes (sub-130-nanometer) has been slow. Instead, the need for higher performance analog components, such as SiGe bipolars, high-voltage metal-oxide semiconductor field-effect transistors (MOSFETs) and high-performance passives, coupled with the need for lower development costs, has necessitated the use of specialty process technologies at mature nodes. An often overlooked consideration by design teams while evaluating AIMS technology platforms relates to design automation. Design enablement tools, including silicon-verified device models and flexible design environments, allow IC design teams to test, modify and improve the functionality and yield of new products long before the first prototype is manufactured. To reduce time-to-market and prototyping costs, best-in-class design automation tools are essential.”


“The perfect storm of increasing analog content, decreasing process line-width, and shortening product design cycles has focused attention on a new bottleneck: analog design. Analog PDKs hold out the promise of both broadening the community of engineers doing analog design, and improving their productivity. It broadens the community by opening up high-performance design to a class of users who never previously considered themselves to be Analog Designers and are now facing analog-like design challenges. It is simultaneously benefiting “card-carrying” Analog Designers – as it provides silicon-proven standard models that aid productivity. Delivering on this promise requires that we overcome the challenge of accommodating diversity in design methodologies, foundry capabilities and EDA tool functionality. This is the manifold challenge we face in making sure PDKs allow for tool innovation. A good example is Tanner’s High Performance Device Generation tool. If we limit a PDK to the set of cells designed by the foundry, we limit the style and performance of the design. Extending the definition of PDK to allow silicon-qualified models for devices such as those in HiPer DevGen would bring tremendous value to both the Foundries and their customers.”

“Synopsys believes that applying standards to PDKs benefits all designers working at the transistor level. This spans custom digital, mainstream analog, high-precision analog and even RF. Lack of standards within the PDK domain have been a consistent impediment to designer productivity, EDA tool innovation, design reuse and design migration. Analog designers have told us they cannot take advantage of new EDA tools because the PDKs are proprietary and incompatible. They’ve also said migrating their designs is painful because of PDK incompatibilities. However, they have not expressed any concern regarding PDK standards negatively impacting their livelihood or restricting their creative needs. For this reason, Synopsys is investing in PDK standards – to help address these analog design issues.”

“The abstract for this panel session, suggests that analog design and advanced process nodes are mutually exclusive. This is not the case. Synopsys has partnered with leading foundries and semiconductor companies to implement PDKs on leading-edge process nodes because this is a natural transition point where new PDKs are being developed, new design starts are being kicked off and new flows are being defined on OpenAccess. Some of the toughest analog design challenges are emerging in these advanced processes. We know this because Synopsys has a large team designing complex, high-performance analog and mixed-signal IP on process technologies ranging from 180-nm down to 28-nm using interoperable PDKs based on IPL standards (iPDKs). We have also collaborated with foundries, IDMs and fabless companies to develop iPDKs at 40nm and below with accurate DFM capabilities is painful, if not impossible, to address using legacy PDK languages and techniques. Lastly, we have customers using standards-based iPDKs on older nodes for analog design with no loss of capability or functionality. Historically, analog design has been slow to change, but it’s already happening. The demonstrated benefits of iPDK standards far outweigh the speculative risks that often accompany change.”

I hope to see you there!

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IP-SoC trip report (part II): system level mantra

IP-SoC trip report (part II): system level mantra
by Eric Esteve on 01-24-2011 at 4:45 am
Categories: Uncategorized

“IP Innovation is moving from component level to system level”. This mantra was heard during the conference, from various speakers: during the keynote talk by Ganesh R. from Gartner and presentation “Integration-Optimized IP from Cadence” by Ranga Srinivasan, also during discussion around coffee (or a glass of wine, but this was in the evening).
I guess everybody will agree on the principle, somehow it’s like moving from LSI to VLSI 30 or 40 years ago. Cadence’ presentation interest was to clearly state the problem the chip maker involved in SoC design are facing. First, the IP integration costs are the most rising, between Software, Hardware and IP, as it can be seen on Figure 1. In fact, this IP Integration cost has doubled from 2005 to 2010 to reach $5B, and will again doubled to reach $10B in 2014. To make it clear, this is the total cost of ownership for a certain IP, not only the License cost. Within five years (in 2015), it will represent 25% of the total cost to develop a SoC.

Then, it clearly makes sense: first to invest into this fast growing market (like Synopsys is doing for almost 10 years now, and Cadence more recently), second to come with a solution attractive enough to catch more customers. If you dream about coming with the new fantastic CPU core, expecting to get (even) 10% of ARM’ market share, it’s better to give up now! A better starting point would be to look at functions which are common components that are not unique to the design, which you can find in many SoC.
According with another slide presented at IP-SoC, the common functions are: memory subsystem, High speed Interface, Wireless and Low speed Interface subsystems. In term of SoC complexity (gate count) these functions represent the most important part of the chip, when compared with the components which are unique to a SoC, the differentiators which are customer specific.

This is a well known status, and the reason why the IP market is growing (when the ASIC/ASSP design starts are declining) is that reuse is becoming mandatory, when the SoC are getting more and more complexes and the time to market (TTM) tighter. The adoption rate for (internal or external) IP is growing, because it is the only way to keep the design cycle within realistic timeframe (12 to 18 months). If you take the example of the SoC for Set Top Box, a consumer product under a very high TTM pressure, these IC can integrate up to 80 different IP, digital and mixed signal components. In this case, we can imagine that external sourcing has reach a limit in volume of functions externally sourced. Then, what could be the next step? Why not moving up in the food chain, or in the value associated with an IP?

Let’s take as an example one of the High Speed Interface (PCIe, HDMI or USB 3.0 in the above figure). The Interface is made of two H/W components; the PHY and the Controller. To be completely functional, you need to add the S/W components: the design and verification constraints, and the drivers. If you provide all of these, you have moved from a “component IP” provider to an “IP stack” provider. The design team will now integrate the complete Interface function. In fact, this trend is becoming a reality and explains the success of the IP vendors able to provide an integrated solution (PHY plus Controller) like Synopsys for the Interface IP market in general. Or Silicon Image for the HDMI and SATA market, as they can also provide the S/W stack, thanks to their parallel ASSP product lines. So, if this model is successful, why stop at the “IP stack”? Cadence, in the presentation made at IP-SoC, is going further:


Using the same SoC as an example, the next move would be to propose an “IP Subsystem”, all the High Speed Interface (PCIe, HDMI and so on) integrated together, all the Low Speed Interface integrated together…and so on. The ultimate step being to procure an “IP Platform”, integrating all the common components tied together. If you present it this way, it looks very logical and almost irrefutable.

So, why do I feel not totally convinced?
Is it because you also can introduce differentiation in these so called “common functions”? For example, certain IDM consider that using an internally designed PHY to support the high speed Interface function is one of their differentiators (I could name three of them in the wireless handset segment only). What about the differentiation based on the use of the latest DDRn specification to offer the best memory bandwidth on the market? I am sure we could find many other examples in which part of the SoC differentiation is coming from these common functions… On the other hand, which is important for the vendor will be to find enough customers being satisfied to use this “IP platform”.

But which IP platform? We can guess the need would be to use segment specific platform, if not, within a segment, an application specific platform. In this case, you will move the design completion issue for TTM from the chip maker to the IP platform vendor. This means that the “IP vendor” will have to be better in term of design efficiency (cycle time, first time right, power consumption, timing closure, area) than his customer currently are. It looks to be a drastic change of business model, as the IP vendor is almost becoming an IP integrator. How many of the IP vendors currently on the market (the latest count made on Design&Reuse web site gives 468!) are ready for such a move?

On one hand, I am convinced that the trend for the IP vendors is to move from IP component to IP stack is real, and fit with a market demand. On the other hand, I am not sure that the market is expecting to benefit from an application specific IP platform. This would require a drastic change in term of organization, most of the design team workload moving from the customer to the vendor. It could be attractive for start-up to use this service, as it is already the case with Value Chain Producer (eSilicon, Verisilicon, GUC and more).

What is YOUR opinion? Do you think there will be a limit between “IP component” and “IP platform”, an optimum where the market will stabilize? Will this limit being IP stack or IP subsystem? Or you rather think that the FPGA is the limit: when you provide an application specific IP platform, just add a fast customizable area… and you have (re) created the modern FPGA? Do not hesitate to share if you are a designer or not, working for an IP vendor, a Fabless or an IDM!

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TSMC Versus The FabClub!

TSMC Versus The FabClub!
by Daniel Nenni on 01-23-2011 at 11:00 pm
Categories: Foundries, TSMC


The Common Platform Technology Forum last week was not well attended, less than half than the GlobalFoundries Conference. It was deja vu of previous CP forums but there were a couple of surprises to go with the disappointment. The lunch line was long, but fortunately I was escorted to the press lunch featuring VIP’s from Samsung, IBM and GlobalFoundries. Yes, I still blog for food.

While I originally thought bringing back Common Platform from the dead was a good idea, attending the Forum definitely changed my mind. According to the presentations, Common Platform WAS wildly successful, but clearly it was not. Chartered Semiconductor WAS Common Platform and Chartered WAS purchased by GlobalFoundries for pennies on the total investment dollar, right?

I would have rather them said, “Look, Common Platform has changed and this is why it WILL be successful from this day forward”. A little humility goes a long way, it also shows respect for the intelligence of the audience. My opinion now is that Common Platform should be laid to rest, dead is dead, no coming back. Only Zombies come back from the dead and no one wants a Common Zombie Platform.

The surprises were twofold:

(1) The FabClub will move to Gate-Last technology for 20nm and beyond. This is HUGE! Gate-Last and Gate-First refer to the point at which a metal gate electrode is dropped onto the wafer, before or after the high-temperature heating process. I spoke with Dr. Shang-Yi Chiang, Vice President of TSMC R&D, and asked why Gate-Last versus Gate-First for 28nm? TSMC actually had parallel 28nm projects: Gate-First, Gate-Last, and Poly-Gate. The winner was the Gate-Last 28nm implementation coupled with Restricted Design Rules (RDRs) due to scalability, performance, and yield. Dr Chang also stated that there is no density penalty using RDRs. When GFI starts yielding we will know for sure which implementation is best at 28nm but it looks like Shang-Yi was right. TSMC has 28nm Silicon with Altera, Nvidia, Xilinx, and AMD/ATI. The only silicon announced from GFI is ARM test chips.

(2) The FabClub fabs (IBM, GFI, Samsung) are GDSII compatible but not mask compatible. This may be ignorance on my part, but I assumed you could move designs across foundries without millions of dollars in mask and other costs. GDS II compatible means design rule compatible, they can use the same DRC decks.

The underlying theme I got from the forum was cost (yawn). The cost of future semiconductor research, development, and manufacturing will be too much for one foundry (TSMC) and will require a FabClub. Even if it was true it’s boring. An even better forum theme, one which I personally endorsed, would have been:

“Common Platform is bringing the collaborative IDM semiconductor design and manufacturing culture to the merchant foundry business!” Daniel Nenni

Samsung, IBM, and AMD are born and bred IDMs, GFI is a foundry. Take the best of both worlds and deliver. It’s a winner, believe it. A distinct advantage GlobalFoundries has over the competition and FabClub partners is communication. These guys have raised the bar! My advice is for IBM and Samsung to step aside and let GlobalFoundries lead the way.

I’m in Taiwan, this week is the TSMC fiscal year end conference call with Morris Chang. Expect really good news: 12″ fabs are full, TSMC will hire more than 6,500 new employees in 2011, TSMC increased R&D expenses 50% and set an $8 billion+ CAPEX. Very big numbers considering semiconductor analysts are fortunetelling single digit semiconductor industry growth in 2011! FOOLS!

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iPDK is the way to go for AMS designs

iPDK is the way to go for AMS designs
by Daniel Payne on 01-19-2011 at 3:47 pm
Categories: EDA, Tanner EDA

294 towerjazz logo1 jpg

I just read the press release from TowerJazz and Tanner EDA about how an AMS designer can use schematic symbols and layout generators in Tanner EDA tools for the TowerJazz 0.18um node. This is made possible because of the growing iPDK (Interoperable Process Design Kits) movement.

In the old days each foundry would have to staff up their CAD groups and create PDKs for all of the leading EDA tools (Cadence, Mentor, Synopsys, Magma, Tanner EDA, etc.). Now with iPDK the foundries can spend less time in getting their symbols and layout generators into each EDA vendor tool. Even the EDA vendors have an efficiency benefit once they adopt iPDK.
Beyond just getting schematic symbols for S-Edit and generators for L-Edit you also get a Power Management AMS Flow, including a reference design for a Band Gap circuit. This is certainly going to save analog IC designers a week of effort.
I like the tag line for Tanner EDA on Twitter: Making EDA Affordable

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SemiWiki Top Influencers get Android Tablets!

SemiWiki Top Influencers get Android Tablets!
by Daniel Nenni on 01-18-2011 at 5:00 am
Categories: General

The most impressive devices at CES this year by far were the Android tablets, I absolutely want one. It will not replace my laptop but my laptop will no longer leave the house (my laptop AC adapter weighs more than a tablet!) My iPod will be for walks and the gym, I won’t buy another digital camera, and no e-reader for me.

SemiWiki is a cloud based social media platform that enables mass collaboration using Web 2.0 technologies (blogging, forums, polls, and wikis) in order to enable new channels of communication within the semiconductor design ecosystem. Today the SemiWiki forums include:

  • Main Forum (industry level)
  • AMS Design
  • Digital Design
  • 3D IC
  • Design IP

Top Influencers will share in the success of SemiWiki, each getting afree Android Tablet.

Out of the 10+ tablets I demo’d at CES, the Motorola Xoom was the only one running Android 3.0, which is a tablet specific OS, previous Android versions were for phones. The Xoom specs I gleamed at CES include:

  • ·Operating system: Google’s Android 3.0 (Honeycomb)
  • ·3G coming in 1st quarter 2011; upgrades to 4G in the second quarter
  • ·Dual (ARM) 1GHZ core Tegra2 processor
  • ·Front and back-facing camera
  • ·HD widescreen (specs not disclosed)
  • ·HD camcorder with 1080 playback
  • ·Adobe Flash Player 10.1 fully-integrated support
  • ·Web cam
  • ·E-reader
  • ·Accelerometer and gyroscope built in for gaming
  • ·Google maps and GPS built-in
  • ·Weight is less than 2 lbs (my guess)
  • ·8-10 hours battery life (Motorola guys claim)

Top Influencers on SemiWiki will be measured and rewarded. Research clearly shows that people who share knowledge and personal experience via blogs, forums, and wikis, can influence 40-60% of all visitors to a specific course of action. More and more, people will get product information and direction from independent top influencers rather than getting it from a vendor or other biased sources.

SemiWiki Top Influencer points can be earned in different ways:

  • Number of wiki edits
  • Number of forum posts
  • Number of unique views on your posts
  • Number of replies to your posts
  • Member ratings of your posts
  • Reputation points (awarded by members)
  • Polls (both voting and commenting)
  • New user referrals (BIG POINTS! Refer semiconductor friends and co-workers!)
  • Infraction points (negative points for unprofessional conduct)

Winners will be revealed at the Design Automation Conference (DAC) June 5-12 2011. SemiWiki is a global community and Android Tablets may have export restrictions but we will do our best to make things right. Stay tuned for more details.

Currently the Motorola Xoom looks like the best Android Tablet for SemiWiki Top Influencers, but the final decision will be collaborative. Look for polls on the subject closer to award time.

This reward is a token of our appreciation for being a part of the Semiconductor Wikipedia Project! If, for whatever reason, you would like to opt out of the Top Influencer program send an email to admin@semiwiki.com. SemWiki staff and bloggers will closely monitor the program for fairness and verify the results.

SemiWiki brings technology and technologists closer together than ever before, closing the gap between pre-sales expectations and post-sales experience. Thank you again for participating in the success of the SemiWiki Project!

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Aart de Geus ( Synopsys ) for Governor!

Aart de Geus ( Synopsys ) for Governor!
by Daniel Nenni on 01-17-2011 at 7:22 pm
Categories: EDA, Synopsys

Seriously, I would vote for Aart, he would make a great California Governor. You will probably not meet a more fiscally responsible CEO. Synopsys is one of the best run companies in Silicon Valley and was recently rated in the top 25 on social media site glassdoor.com. Aart ( SNPS ) has a 92% approval rate, Wally ( MENT ) 80%, Lip-Bu ( CDNS ) 56%, and Rajeev (LAVA ) 45%. He’s also an accomplished Jazz musician, a well-known philanthropist and political activist. So you have to ask yourself what challenges are left for Aart in EDA? Well, none really. So Aart, start kissing babies and let’s get the campaign rolling because CALIFORNIANEEDS YOU!

Synopsys has 23 new hires, 3 promotions or changes, 9 recent departures, and 11 new job opportunities

The EDAC CEO Panel video is up, you can see it HERE. I’m on segments #21 and #57, also watch the 2010 panel video HERE for perspective, it makes me look better. The CEO slide presentations are up as well. Unfortunately Aart’s comment during his introduction was caught and is being misinterpreted (I have been getting “Why does Aart not like you?” emails). I was kidding and so was Aart, he’s a class act. There is a discussion in the SemiWikigeneral forum on the EDAC CEO Panel so watch the video and take your shots at me HERE.

All-in-all it was a very good moderating experience. The best comment I heard that evening was “You were way better than John Cooley!” which truly is a compliment. John and I are friends, his contribution to EDA is well documented. John should also run for office, but probably not for Governor, maybe Sanitation Commissioner or something in Homeland Security.

Public speaking jobs are now pouring in. I will be moderating a panel next month at DesignCon on “PDKs for Analog IC Design – A Stakeholder Discussion”. I actually know what PDK stands for so you won’t want to miss this one. In March I will moderate a panel at EDATech Forum which is my favorite type of conference (free). It doesn’t matter what topic they pick for me, I can assure you it will be well worth the price of admission.

This week I will be at the Common Platform Technology Forum. If you see a guy that looks like Robin Williams on steroids that would be me:

Tomorrow’s Technology – Delivered Today
The Common PlatformAlliance of IBM, Samsung and GLOBALFOUNDRIES invites you join us at our technology forum on Tuesday, January 18. This free, daylong event will feature the Common Platform’s innovative collaboration to deliver industry-leading technology that breaks new ground in performance and power efficiency for the 32/28nm technology nodes and beyond.
The technology forum features keynotes from industry leaders and presentations from senior members of the Common Platform partners. Topics include:

  • Technical advancements of the innovative 32/28nm low-power high-k metal gate (HKMG) process technology optimized for the next generation of communications and smart mobile devices
  • Technology innovations in SoC enablement solutions, materials science, process technology and manufacturing
  • Proven design and manufacturing solutions from the alliance and its ecosystem partners
  • The invention process and technology roadmap to 20nm and beyond

A key part of the forum will focus on collaboration for technology delivery, highlighting the rich and broad ecosystem of design enablement and implementation partners through a Partner Pavilion featuring leading EDA, IP, library, mask, back-end and design services companies.