CadenceLIVE ran a session recently in Europe which I thought would be interesting to check out, especially around automotive needs. The live sessions were too early/late for me (middle of the night) and sadly the talks I really wanted to hear weren’t recorded. Instead, I dug around for updates on automotive electronics in Europe. ST, NXP and Infineon remain strong in automotive chip, spanning ADAS, drivetrain, infotainment, car networks and electrification. More interesting for my purposes are the Tier 1s. Bosch, Continental and ZF Friedrichshafen rank in the top 5 in the world. Some of these are edging into chip design of one kind or another on their own behalf. Then major OEMs active in ADAS and autonomy – VW/Audi, Volvo, BMW and others. All have significantly invested in Israel for automotive safety – hence my topic.
Automotive development in Israel
Israel is well-established in tech; this is not news. All the majors have development there: Intel, Alibaba, Amazon, AMD, Apple, NVIDIA, Qualcomm, Marvell, Cisco, just picking a few off a long list. Some well-known names in automotive are Mobileye and Waze, both Israeli companies, acquired by Intel and Google respectively. And Argus, also Israeli, acquired by Continental. What may be slight less visible is automaker activity in Israel. GM, VW, Mercedes, Ford and Bosch all have offices in Israel, for advanced electronics and software development. Volvo recently joined this group though the CEVT innovation center based in Sweden. And ZF Friedrichshafen has strategic collaborations in Israel. This country seems pretty important in automotive tech plans for almost everyone.
Veriest talk on verification for safety
Another area of strength for Israel, well known at least in our neck of the woods, is functional verification. After all, Verisity and ‘e’ were born there. So it shouldn’t be a surprise that Veriest (an Israeli design and verification services company I’ve mentioned before) hosted a talk at CadenceLIVE Europe title ‘Is your design functionally safe?”. Per the Cadence stats, this was one of the best attended presentations at the show, unsurprising given all of the above. Perhaps also because they work with a number of the Tier 1 companies. I watched the replay and I have to admit the speaker (Mihajlo Katona) did a really good job. A very disciplined, nuts and bolts walk-through on validating effectiveness of functional safety mitigation techniques. The talk was based on testing memories and logic in an AI processor using soft error injection.
Verifying mitigation techniques
Mihajlo drilled down into ECC for memories in the processors. He outlined the ECC agent model for checking and a constrained random model for injecting permanent faults and transient faults. Their model also contains a prediction unit to compare if the hardware model correctly detects an injected error or not. He mentioned a practical detail I hadn’t considered – if an error is detected, the hardware will likely trigger an interrupt to the main system which will take a little time to process. Then there should be a recovery flow in the hardware. The Veriest verification needed to check that capability functions properly.
For logic verification he assumed BIST, an ISO 26262 recommended mechanism. I guess because in-operation testing is an expected capability in support of fail-operational behavior, also in support of 15-year lifetimes. Here Mihajlo talked about the best way to inject faults (permanent and transient), which should be agreed in discussion with the design team.
A very detailed overview, worth watching. You can register to watch the replay HERE. Once in (you may need to register), look under verification sessions for “Is your design functionally safe?”.Share this post via: