Webinar: 5 Expectations for the Sensor Market in 2026

Webinar: 5 Expectations for the Sensor Market in 2026
by Admin on 09-29-2025 at 11:45 pm

November 5, 2025 – 11:00 AM EST

November 6, 2025 – 10:00 AM JST/KST

Discover the 5 Critical Sensor Market Trends Reshaping Semiconductors in 2026

From 8K smartphones to AI at the edge—explore the next generation of image sensor innovation.

The image sensor industry is shifting from traditional pixel scaling to functionality-driven… Read More

Webinar: 5 Expectations for the Memory Market in 2026

Webinar: 5 Expectations for the Memory Market in 2026
by Admin on 09-29-2025 at 11:43 pm

October 29, 2025 – 11:00 AM EST

October 30, 2025 – 10:00 AM JST/KST

Discover the 5 Critical Memory Market Trends Reshaping Semiconductors in 2026

AI workloads, HBM4 adoption, and 3D NAND scaling—what’s next for the memory industry in 2026.

The memory semiconductor industry is entering a critical inflection point. Explosive… Read More

Webinar: 5 Expectations for the Power Market in 2026

Webinar: 5 Expectations for the Power Market in 2026
by Admin on 09-29-2025 at 11:41 pm

October 22, 2025 – 11:00 AM EST

October 23, 2025 – 10:00 AM JST/KST

Discover the 5 Critical Power Market Trends Reshaping Semiconductors in 2026

Wide-bandgap disruption, PMIC innovation, and datacenter power demand, what’s next for power semiconductors.

The rise of AI datacenters is driving unprecedented demand for … Read More

Webinar: 5 Expectations for the AI Market in 2026

Webinar: 5 Expectations for the AI Market in 2026
by Admin on 09-29-2025 at 11:39 pm

October 15, 2025 – 11:00 AM EST

October 16, 2025 – 10:00 AM JST/KST

Discover the 5 Critical AI Market Trends Reshaping Semiconductors in 2026

From datacenter accelerators to 2nm process technology, learn what’s next for AI and the semiconductor industry.

The acceleration of artificial intelligence (AI) adoption is fueling

Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis

Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis
by Admin on 09-24-2025 at 4:37 pm

The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL,

Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System

Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System
by Admin on 09-23-2025 at 3:34 pm

As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines… Read More

Webinar: IP Design Considerations for Real-Time Edge AI Systems

Webinar: IP Design Considerations for Real-Time Edge AI Systems
by Admin on 09-22-2025 at 5:07 pm

*Work Email Required*

Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support… Read More

September 11, 2025September 16, 2025

Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs

Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs
by Mike Gianfagna on 09-11-2025 at 10:00 am
Categories: Easy-Logic, EDA, Events

An engineering change order, or ECO in the context of ASIC design is a way to modify or patch a design after layout without needing to re-implement the design from its starting point. There are many reasons to use an ECO strategy. Some examples include correcting errors that are found in post-synthesis verification, optimizing … Read More

September 4, 2025September 16, 2025

WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design

WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
by Daniel Nenni on 09-04-2025 at 8:00 am
Categories: Easy-Logic, EDA, Events

This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.

The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More

Webinar: Pushing more power with CoolGaN™: design, layout and thermal management

Webinar: Pushing more power with CoolGaN™: design, layout and thermal management
by Admin on 08-27-2025 at 8:15 pm

Webinar date: 22.10.2025 | 9 AM CEST | 5 PM CEST

Join our webinar and learn about the fundamentals of Gallium Nitride (GaN) technology and its applications in power systems.

You will gain a deep understanding of gate drive circuit design, layout steps, and thermal management guidelines for GaN transistors and applications in high-switching