Sidenserecently conducted a webinar on what they call the Smart Connected Universe. They consider the Smart Connected Universe as something that includes a collection of market segments that are both smart and connected. This casts a big net, and includes what many are calling IoT, but goes further into medical, automotive and… Read More
Tag: webinar
Webinar: Choosing IP for your next IoT Design
My favorite IoT device is a cycle-computer from CatEyeand it has GPS for tracking my bike routes, and an LCD display that shows me speed, cadence, heart rate and time. After each ride I connect my CatEye device to a USB connector, upload my data to Strava.com, and then see how I’m doing versus other cyclists and my own personal… Read More
Using NoCs to Reduce Power
Earlier this week I moderated a webinar at Sonics entitled NoC 102: Using SonicsGN to Address Low Power Requirements. Drew Wingard, the CTO of Sonics, presented it. It goes without saying that power is a major concern in SoC design, not just with chips for battery powered devices but also tethered devices. A major cost of ownership… Read More
NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers
At the end of last year, I moderated a Sonics webinar to introduce the concept of a network-on-chip or NoC. It was called NoC 101 and the replay is still available here.
Well it is a new year and time for chapter 2. I will be moderating a webinar next Wednesday February 4th at 10am pacific time. Once again the webinar itself will be delivered… Read More
eSilicon Try IP Before You Buy
I’ve written before about eSilicon’s IP Marketplace. This is the latest in several steps to automate more and more of the interface between eSilicon and its customers: MPW quotes, production quotes, tracking orders through manufacturing, and now IP quotes. There is a phrase in software development called “eating… Read More
Benefits of Using Schematic Driven Layout
Most IC designs are developed by a team of professionals, often separated into distinct groups like front-end and back-end, logical and physical designers. Circuit designers use tools like schematic capture at the transistor-level to create a topology, then begin simulating the netlist with a SPICE simulator. Layout designers… Read More
How to Optimize for Power at RTL
Last week I was traveling in Munich attending the MunEDA User Group meetingso I missed a live webinar on the topic of optimizing for power at RTL. I finally got caught up in my email this week and had time to view this 47 minute webinar, presented by Guillaume Boilletof Atrenta. He recommended using a combination of automatic, semi-automatic… Read More
IC Place and Route for AMS Designs
High-capacity IC place and route (P&R) tools can cost $200K and more to own from the big three vendors (Cadence, Synopsys, Mentor), but what about IC designs that are primarily Big Analog and Little Digital? In the EDA world we often have multiple choices for tools, and there are affordable alternatives to place and route out… Read More
Leakage Current TCAD Calibration in a-Si TFTs
Two weeks ago I blogged about amorphous silicon and how that material is well-suited for designing TFTs. Today I’m following up after watching the archived webinarpresented by Nam-Kyun Tak of Silvaco. After clicking on that link you’ll be brought to a brief sign-up page and then can watch the archived webinar in your… Read More
NoC 101, a Sonics Webinar
One of the things that I’ve been telling the people at Sonics when they will listen is that they should do a bit more basic education on Networks on Chip (NoC). Sure, the people who actually use Sonics’s products care about deep details such as security and power management, but there is a whole host of designers who have… Read More