So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.… Read More


TSMC’s DFM Announcement

TSMC’s DFM Announcement
by glforte on 10-14-2010 at 4:00 pm

If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources… Read More


So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.… Read More


TSMC’s DFM Announcement

TSMC’s DFM Announcement
by glforte on 10-14-2010 at 4:00 pm

If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources… Read More


The New Semiconductor Economy

The New Semiconductor Economy
by Daniel Nenni on 07-04-2010 at 1:29 pm

Bill Wiseman of McKinsey & Company presented “Waking up to the new normal, the world economy after the great recession” at a recent ITAC GSA Conference. Bill supports my previous semiconductor financial predictions in great and graphical detail.

In the United States: unemployment claims are up, home sales are down without… Read More


TSMC versus GlobalFoundries: Semiconductor Design Enablement!

TSMC versus GlobalFoundries: Semiconductor Design Enablement!
by Daniel Nenni on 06-01-2010 at 9:00 pm


As mentioned in previous blogs, design enablement is a key enabler to fabless semiconductor design and manufacture, without question. The purpose of this blog (in 500 words) is to compare and contrast two very different design enablement strategies and engage the semiconductor community in a meaningful discussion.

The GlobalFoundry… Read More


450mm Semiconductor Manufacturing Debate

450mm Semiconductor Manufacturing Debate
by Daniel Nenni on 05-23-2010 at 2:39 pm


This blog posting is sponsored by EVA airlines, as I’m in the EVA executive lounge eating free food (I blog for food). “Fly EVA, the lesser of evils for Taiwan air travel!” EVA Air has a perfect safety record in 9 years of operation, China Air on the other hand has the worst safety record in the industry!

This blog was inspired by one of … Read More


2010 Semiconductor Foundry Update: Consolidation!

2010 Semiconductor Foundry Update: Consolidation!
by Daniel Nenni on 05-16-2010 at 6:46 pm

It has been an interesting month in the semiconductor business. Record revenues, profits, aggressive expansion plans, something we have not seen before and may not see again. Let’s start in Taiwan then move to Silicon Valley, Upstate New York, China, and Korea, with a look at: financials, capacity, and consolidation.

TSMC and… Read More


TSMC Earthquake Damage Redo

TSMC Earthquake Damage Redo
by Daniel Nenni on 04-14-2010 at 10:54 pm

As you may know I enjoy poking fun at the current state of semiconductor design and manufacture media; sloppy reporting, editors with little or no actual semiconductor experience taking corporate marketing spins on news/events and passing it along as fact.

Last week it was the EETimes parroting the Samsung foundry business pressRead More


Moore’s Law and 28nm Yield

Moore’s Law and 28nm Yield
by Daniel Nenni on 01-24-2010 at 10:44 pm

This blog is a follow-up to my second most viewed page Moore’s Law and 40nm Yield, with a strong recommendation of how to design for yield at the advanced nodes (32/28/22nm) with Verify High-Sigma design technology.

Case in point: Circuit blocks such as complex standard cells or memory bit cells are repeated thousands or even millions… Read More