TSMC warns soft phone/crypto & flat capex!
Does this impact DRAM?
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TSMC Adds Negative Semiconductor News
Tag: tsmc
Cleaning Trends for Advanced Nodes
I was invited to give a talk at the Business of Cleans Conference held by Linx Consulting in Boston on April 9th. I am not a cleans expert but rather was invited more to give an overview talk on process technology trends and the impact on cleans. In this write up I will discuss my presentation. I discussed each of the three main leading-edge… Read More
Leading Edge Logic Landscape 2018
The most viewed blogs I write for SemiWiki are consistently blogs comparing the four leading edge logic producers, GLOBALFOUNDRIES (GF), Intel, Samsung (SS) and TSMC. Since the last time I compared the leading edge new data has become available and several new processes have been introduced. In this blog I will update the current… Read More
Robust Reliability Verification – A Critical Addition To Baseline Checks
Design process retargeting is acommon recurrence based on scaling orBOM(Bill-Of-Material) cost improvement needs. This occursnot only with the availability of foundry process refresh to a more advanced node,but also to any new derivative process node tailored towards matching design complexity, power profile or reliability… Read More
LithoVision 2018 The Evolving Semiconductor Technology Landscape and What it Means for Lithography
I was invited to present at Nikon’s LithoVision event held the day before the SPIE Advanced Lithography Conference in San Jose. The following is a write up of the talk I gave. In this talk I discuss the three main segments in the semiconductor industry, NAND, DRAM and Logic and how technology transitions will affect lithography.… Read More
Machine Learning And Design Into 2018 – A Quick Recap
How could we differentiate between deep learning and machine learning as there are many ways of describing them? A simple definition of these software terms can be found here. Let’s look into Artificial Intelligence (AI), which was coined back in 1956. The term AI can be defined as human intelligence exhibited by machines.… Read More
IEDM 2017 – Controlling Threshold Voltage with Work Function Metals
As I have said many times, IEDM is one of the premier conferences for semiconductor technology. On Sunday before the formal conference started I took the “Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS” short course. The second module in the course was “Multi-Vt Engineering… Read More
TSMC 5nm and EUV Update 2018
The TSMC Q4 2017 earnings call transcript is up and I found it to be quite interesting for several reasons. First and foremost, this is the last call Chairman Dr. Morris Chang will participate in which signifies the end of a world changing era for me and the fabless semiconductor ecosystem, absolutely. TSMC announced his retirement… Read More
Moore’s Law Drives Foundries and IP Providers
2017 was a banner year for semiconductor sales as they topped $400B for the first time, an increase of some 20%, there is happiness in Silicon Valley, Taiwan, South Korea, and well, everywhere. With the foundries pushing to ever-smaller process dimensions and even going back to mature nodes and offering more variations that are… Read More
ISS 2018 – The Impact of EUV on the Semiconductor Supply Chain
I was invited to give a talk at the ISS conference on the Impact of EUV on the Semiconductor Supply Chain. The ISS conference is an annual gathering of semiconductor executives to review technology and global trends. In this article I will walk through my presentation and conclusions.… Read More