The TSMC OIP Technical Paper Abstracts are up!

The TSMC OIP Technical Paper Abstracts are up!
by Daniel Nenni on 08-25-2013 at 8:10 pm

The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers’ design challenges and success stories of best practice in TSMC’s design ecosystem.

More than 90% of the attendees last year said “this… Read More


Mentor CEO Wally Rhines U2U Keynote

Mentor CEO Wally Rhines U2U Keynote
by Daniel Nenni on 04-26-2013 at 2:00 pm

You will never meet a more approachable CEO in the semiconductor ecosystem than Dr. Walden C. Rhines. The first time I met Wally was way back when I blogged for food and he invited me over for lunch. Even better, a year or two later I was having dinner with a friend at the DBL Tree in San Jose. Wally was waiting for his flight home so he joined… Read More


Mentor @ the TSMC Open Innovation Platform Forum

Mentor @ the TSMC Open Innovation Platform Forum
by glforte on 01-16-2013 at 6:16 pm

At TSMC’s Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described below with links to downloadable pdf presentation files.

Finding and Fixing Double Patterning Errors in
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Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design Paper

Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design Paper
by Daniel Nenni on 10-12-2012 at 8:00 am

Silicon Creations will be presenting a paper with Berkeley Design Automation at the TSMC Open Innovation Platform (OIP) Ecosystem Forum next week where TSMC’s design ecosystem member companies and customers share real-case solutions for design challenges within TSMC’s design ecosystem:

This presentation will describe Read More


TSMC OIP Ecosystem Forum 2012

TSMC OIP Ecosystem Forum 2012
by Daniel Nenni on 10-07-2012 at 7:11 pm

The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers’ design challenges and success stories of best practice in TSMC’s design ecosystem.


More than 90% of the attendees last year said “this… Read More


Exclusive Sneak Peek: Cadence at TSMC OIP Ecosystem Forum 2012

Exclusive Sneak Peek: Cadence at TSMC OIP Ecosystem Forum 2012
by Daniel Nenni on 10-05-2012 at 8:37 am

The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers’ design challenges and success stories of best practice in TSMC’s design ecosystem. More than 90% of the attendees last year said “this… Read More


Re-defining Semiconductor Collaboration!

Re-defining Semiconductor Collaboration!
by Daniel Nenni on 07-22-2012 at 7:00 pm

GlobalFoundries did a nice response to my “How has 20nm Changed the Semiconductor Ecosystem?” and redefined the word collaboration. Our industry is plagued with sound bites and acronyms so let us agree on a semiconductor ecosystem definition of collaboration.

Mojy Chianis senior vice president, design enablement at… Read More


What Will 2012 Bring The Semiconductor Ecosystem?

What Will 2012 Bring The Semiconductor Ecosystem?
by Daniel Nenni on 12-18-2011 at 4:30 pm

During my annual holiday meal with one of my favorite EDA icons some rather bold predictions were made. On his side it was more of what he would LIKE to see happen, on my side it was more of what will HAVE to happen for the semiconductor ecosystem to thrive in the coming years.

Mike Gianfagna (Viva Italia!) spent 15+ years with RCA/GE Semiconductor… Read More


iLVS: Improving LVS Usability at Advanced Nodes

iLVS: Improving LVS Usability at Advanced Nodes
by glforte on 12-13-2011 at 4:54 pm

LVS Challenges at Advanced Nodes

Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. As the number of layers and layer derivations increases the complexity of devices, especially Layout Dependent… Read More


Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes

Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes
by glforte on 12-07-2011 at 3:52 pm

Preventing electrical circuit failure is a growing concern for IC designers today. Certain types of failures such as electrostatic discharge (ESD) events, have well established best practices and design rules that circuit designers should be following. Other issues have emerged more recently, such as how to check circuits… Read More