Key Takeaways from the TSMC Technology Symposium Part 2

Key Takeaways from the TSMC Technology Symposium Part 2
by Tom Dillinger on 03-22-2016 at 4:00 pm

In Part 1, we reviewed four of the highlights of the recent TSMC Technology Symposium in San Jose. This article details the “Final Four” key takeaways from the TSMC presentations, and includes a few comments about the advanced technology research that TSMC is conducting.… Read More


Key Takeaways from the TSMC Technology Symposium Part 1

Key Takeaways from the TSMC Technology Symposium Part 1
by Tom Dillinger on 03-20-2016 at 7:00 am

TSMC recently held their annual Technology Symposium in San Jose, a full-day event with a detailed review of their semiconductor process and packaging technology roadmap, and (risk and high-volume manufacturing) production schedules.… Read More


DDR4 is a complex interface to verify — assistance needed!

DDR4 is a complex interface to verify — assistance needed!
by Tom Dillinger on 02-16-2016 at 7:00 am

The design of parallel interfaces is supposed to be (comparatively) easy — e.g., follow a few printed circuit board routing guidelines; pay attention to data/clock/strobe signal lengths and shielding; ensure good current return paths (avoid discontinuities); match the terminating resistances to the PCB trace impedance;… Read More


Top Ten Insights on the EDA and Semiconductor Industry

Top Ten Insights on the EDA and Semiconductor Industry
by Tom Dillinger on 02-11-2016 at 7:00 am

I recently had the opportunity to chat with Anirudh Devgan, senior vice president and general manager at Cadence, who leads the Digital and Signoff Group. We discussed recent product development initiatives at Cadence, and talked about future EDA and semiconductor market opportunities. His insights and comments were keen … Read More


Pathfinding to an Optimal Chip/Package/Board Implementation

Pathfinding to an Optimal Chip/Package/Board Implementation
by Tom Dillinger on 02-04-2016 at 4:00 pm

A new term has entered the vernacular of electronic design engineering — pathfinding. The complexity of the functionality to be integrated and the myriad of chip, package, and board technologies available make the implementation decision a daunting task. Pathfinding refers to the method by which the design space of technology… Read More


Expanding 3D EM Simulation Access to All

Expanding 3D EM Simulation Access to All
by Tom Dillinger on 02-03-2016 at 7:00 am

James Clerk Maxwell’s eponymous equations are the basis for simulating electromagnetic wave propagation. In school, EE majors tended to fall into two camps: (a) those that thoroughly enjoyed their fields and waves classes, who liked doing surface integrals, and who were adept at demonstrating the “right hand rule”, and (b) … Read More


HSPICE – 35 and looking good!

HSPICE – 35 and looking good!
by Tom Dillinger on 02-01-2016 at 12:00 pm

A maturetool. A legacytool. A tool that’s a little long in the tooth. We have all used these terms to refer to an EDA product that has not been able to keep up with technical challenges of model complexity, performance, or new features required by current SoC and system design requirements.… Read More


The “Era of the Photon” is here!

The “Era of the Photon” is here!
by Tom Dillinger on 01-02-2016 at 12:00 pm

The 50 year anniversary of the publication of Moore’s Law was recently celebrated, highlighting the tremendous advances in the Microelectronics Eraof the period in human history known as the Information Age. However, the technical and economic challenges currently faced by the microelectronics industry are bringing into… Read More


A Synergistic Chip-Package-System Analysis Methodology

A Synergistic Chip-Package-System Analysis Methodology
by Tom Dillinger on 12-23-2015 at 4:00 pm

Looking back, 2015 was a significant year for mergers and acquisitions in the EDA industry. The Semiwiki team maintains a chronology of major transactions here.

As I was reviewing this compendium, one of the entries that stands out is the acquisition of Apache Design Solutions by Ansys, Inc. a couple of years ago.

At that time, there… Read More


A (R)evolution in Hardware-based Simulation Acceleration

A (R)evolution in Hardware-based Simulation Acceleration
by Tom Dillinger on 11-16-2015 at 9:45 am

The most exciting products in our industry are those that are both evolutionary and revolutionary. Cadence has just announced an update to their hardware simulation acceleration platform – Palladium Z1 – which continues the evolution of the unique capabilities of processor-based acceleration, plus a revolutionary approach… Read More