UCIe Specification Streamlines Multi-Die System Design with Chiplets

UCIe Specification Streamlines Multi-Die System Design with Chiplets
by Dave Bursky on 09-26-2022 at 10:00 am

protocol stack 1

Over the last few years, the design of application-specific ICs as well as high-performance CPUs and other complex ICs has hit a proverbial wall. This wall is built from several issues: first, chip sizes have grown so large that they can fill the entire mask reticle and that could limit future growth. Second, the large chip size impacts… Read More


Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC

Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC
by Daniel Nenni on 09-20-2022 at 10:00 am

Ansys chip package board

Over its 40+ year history, electronic design automation (EDA) has seen many companies rise, fall, and merge. In the beginning, in the 1980s, the industry was dominated by what came to be known as the big three — Daisy Systems, Mentor Graphics, and Valid Logic (the infamous “DMV”). The Big 3 has morphed over the years, eventually settling… Read More


Samsung Foundry Forum & SAFE™ Forum 2022

Samsung Foundry Forum & SAFE™ Forum 2022
by Daniel Nenni on 09-16-2022 at 6:00 am

SFF SAFE GLOBAL Banner 400 400

It has been an exciting time in the semiconductor industry and the excitement is far from over. Years 2022 and 2023 will be more challenging in many different ways and live activities have just begun. The cornerstones to the semiconductor industry are the foundries so I look forward to the live foundry events coming up in October,… Read More


WEBINAR: Intel Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs

WEBINAR: Intel Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
by Synopsys on 08-30-2022 at 10:00 am

Synopsys Fusion Compiler

Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are

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An EDA AI Master Class by Synopsys CEO Aart de Geus

An EDA AI Master Class by Synopsys CEO Aart de Geus
by Daniel Nenni on 08-19-2022 at 8:00 am

Aart de Geus White House

I consider Dr. Aart de Geus one of the founding fathers of EDA and one of the most interesting people in the semiconductor industry. So it is not a surprise that Aart was chosen to attend the CHIPs Act signing at the White House.

Here is his current corporate bio:

Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys… Read More


ARC Processor Summit 2022 Your embedded edge starts here!

ARC Processor Summit 2022 Your embedded edge starts here!
by Synopsys on 08-15-2022 at 10:00 am

ARC Summit 2022

As embedded systems continue to become more complex and integrate greater functionality, SoC developers are faced with the challenge of developing more powerful, yet more energy-efficient devices. The processors used in these embedded applications must be efficient to deliver high levels of performance within limited power… Read More


DSP IP for High Performance Sensor Fusion on an Embedded Budget

DSP IP for High Performance Sensor Fusion on an Embedded Budget
by Kalar Rajendiran on 08-04-2022 at 6:00 am

VPX Vector DSP Core Data Types

Whether we realize it or not, everyday applications we use depend on data gathered by sensors. We can bet that pretty much every application uses at least a couple of different types of sensors, if not more. That is because different types of sensors are better suited to collect data depending on the application, the environment … Read More


Memory Security Relies on Ultra High-Performance AES-XTS Encryption/Decryption

Memory Security Relies on Ultra High-Performance AES-XTS Encryption/Decryption
by Kalar Rajendiran on 07-11-2022 at 10:00 am

dwtb q222 security aes xts fig1.jpg.imgw .850.x

A recent SemiWiki post covered the topic of protecting high-speed interfaces in data centers using security IP. That post was based on a presentation made by Dana Neustadter at IP-Soc Silicon Valley 2022 conference. Dana’s talk was an overview of various interfaces and Synopsys’ security IP for protecting those interfaces. … Read More


Interface IP in 2021: $1.3B, 22% growth and $3B in 2026

Interface IP in 2021: $1.3B, 22% growth and $3B in 2026
by Eric Esteve on 07-10-2022 at 10:00 am

IP 2017 2026

If you want to remember the key points for Interface IP in 2021, just consider $1.3B, 22%, $3B. Interface IP category has generated $1 billion 300 million in 2021, or 22.7% year to year growth, thanks to high runner protocols PCIe, DDR memory controller and Ethernet/SerDes. Even more impressive is the forecast, as IPnest predict… Read More


Casting Light on OpenLight’s Open Silicon Photonics Platform

Casting Light on OpenLight’s Open Silicon Photonics Platform
by Kalar Rajendiran on 06-20-2022 at 6:00 am

The Growing Silicon Photonics Market

For many decades now, modern optical technology has been deployed in networking infrastructure, for long haul and medium haul links to support internet communications. The foundation of this technology is photonics, which is the science of generation, manipulation and detection of light for performing functions otherwise… Read More