CTO Interview: Jeff Galloway of Silicon Creations

CTO Interview: Jeff Galloway of Silicon Creations
by Daniel Nenni on 02-27-2017 at 7:00 am

It is clear that IP companies play an important role in modern semiconductor design, in fact, I would say that they are imperative. Founded in 2006, Silicon Creations is one of those imperative IP companies that provide silicon proven IP to customers big and small around the world. To follow-up on our conversation with Silicon Creations… Read More


DesignCon 2017 and Mentor Graphics

DesignCon 2017 and Mentor Graphics
by Daniel Nenni on 01-17-2017 at 7:00 am

It’s hard to believe but this is DesignCon #22 and being a Silicon Valley conference I have attended my fair share of them. This year it seems like high speed communications will take the lead followed by the latest on PCB design tools, power and signal integrity, jitter and crosstalk, test and measurement tools, parallel … Read More


Analog Bits and TSMC!

Analog Bits and TSMC!
by Daniel Nenni on 01-10-2017 at 12:00 pm

TSMC Wafer

As a long time semiconductor IP professional I can tell you for a fact that it is one of the most challenging segments of semiconductor design. Given the growing criticality of semiconductor IP, the challenges of being a leading edge IP provider are increasing and may be at a breaking point. The question now is: What does it take to … Read More


CEO Interview: Randy Caplan of Silicon Creations

CEO Interview: Randy Caplan of Silicon Creations
by Daniel Nenni on 12-05-2016 at 7:00 am

For the next installment in our series of semiconductor CEO interviews we meet with Randy Caplan from Silicon Creations. Randy has helped build the company from a small startup to one of the world’s leading providers of interface and clocking IP. Almost every new chip developed these days has a requirement for PLLs and SerDes. Since… Read More


Always-On IoT – FDSOI’s Always Better? What About Wafers? (Questions from Shanghai)

Always-On IoT – FDSOI’s Always Better? What About Wafers? (Questions from Shanghai)
by Adele Hars on 11-03-2016 at 7:00 am

Mahesh Tirupattur, EVP at low-power SERDES pioneer Analog Bits lead off the panel discussion at the recent FD-SOI Forum in Shanghai with the assertion that for anything “always on” in IoT, FD-SOI’s always better. They had a great experience porting their SERDES IP to 28nm FD-SOI (which they detailed last spring – see the ppt hereRead More


The IP Paradox: Sales are growing despite Semi Consolidation

The IP Paradox: Sales are growing despite Semi Consolidation
by Eric Esteve on 10-29-2016 at 7:00 am

IPnest is launching the “Interface IP Survey” since 2009, and we did it last September again. To build the survey as accurately as possible, I have followed the “divide and conquer” strategy. Interface protocols are varied, ranging from PCI Express, USB, or Ethernet, to memory controller (DDR3, DDR4, LPDDR3, LPDDR4 and more) … Read More


Interface IP year 2015: Winners and Losers

Interface IP year 2015: Winners and Losers
by Eric Esteve on 01-06-2016 at 1:00 pm

The global Interface IP market is still growing in 2015, no doubt about it. It’s interesting to zoom in the various protocols to check their respective behavior. Which protocol generates an IP business growing more than the average market? Which protocol generates a disappointing IP business? In other words, which are the winners… Read More


How Well is HSPICE Tracking Current Design Trends?

How Well is HSPICE Tracking Current Design Trends?
by Tom Simon on 02-11-2015 at 10:00 pm

For about 5 years now Synopsys has held an HSPICE SIG event in conjunction with DesignCon. It features a small vendor faire with companies that partner with Synopsys on HSPICE flows. They also have a dinner with industry/customer speakers and provide an update on HSPICE development. Lastly there is a Q&A where customers get… Read More


Don’t Mess with SerDes!

Don’t Mess with SerDes!
by Eric Esteve on 12-01-2014 at 2:23 am

SerDes stands for Serializer/Deserializer, and SerDes is a serious piece of design, requiring an extremely experienced team of analog engineers (below 10 years’ experience, you’re still a quasi-beginner). Better to rely on an analog guru to draw the SerDes architecture and manage the team! Why does SerDes is becoming more and… Read More


SerDes: Four Wires Are Better Than Two

SerDes: Four Wires Are Better Than Two
by Daniel Nenni on 04-06-2014 at 8:00 pm

Kandou Bus SA has recently been proposing the technique ENRZ (Ensemble Non Return to Zero) for use as the next generation interconnect standard for the 56 Gb/s generation of interconnect interfaces at the OIF (Optical Interconnect Forum). ENRZ is technique where three bits are orthogonally modulated over four correlated wires.… Read More