SilabTech Awarded 2013 Best Start-up in India

SilabTech Awarded 2013 Best Start-up in India
by Eric Esteve on 01-20-2014 at 8:32 am

This is obviously great news for SilabTech, and this is the type of news which will change the perception that we (non-Indian) have of the Semiconductor industry in India. About 15-20 years ago, the India Embedded/VLSI industry was perceived as low cost design resource pool, a good place where to implement design center. The hidden… Read More


What’s new in the “Interface IP Survey” ?

What’s new in the “Interface IP Survey” ?
by Eric Esteve on 11-26-2013 at 9:27 am

The reader will find many updates in the “Interface IP Survey” from IPNEST, released in October 2013. Good question, as the IP market is a very fast moving one and the protocol based Interface IP, is moving even faster… exhibiting 20% growth rate in 2012, expected to grow with 10% CAGR between 2012 and 2017 to reach $700M. … Read More


Rare earth syndrome: PHY IP analogy

Rare earth syndrome: PHY IP analogy
by Eric Esteve on 04-03-2013 at 10:34 am

If you ask to IP vendors selling functions, PHY or Controller, supporting Interface based protocols which part is the master piece, the controller IP only vendors will answer: certainly my digital block, look how complex it has to be to support the transport and logical part of the protocol! Just think about the PCI Express gen-3Read More


Signal integrity: more than just SerDes analysis

Signal integrity: more than just SerDes analysis
by Don Dingee on 03-29-2013 at 1:00 am

When Cadence acquired Sigrity in 2012, two motives were involved: get more competitive in state of the art signal integrity analysis, and grab a foothold into the other vendor’s PCB flows in an area that is developing as a real sore spot for digital designers.

Just as the days where PCB tape-out meant actually using tape are over, … Read More


Modeling TSV, IBIS-AMI and SERDES with HSPICE

Modeling TSV, IBIS-AMI and SERDES with HSPICE
by Daniel Payne on 02-21-2013 at 8:10 pm

The HSPICE circuit simulator has been around for decades and is widely used by IC designers worldwide, so I watched the HSPICE SIG by video today and summarize what happened. Engineers from Micron, Altera and AMD presented on how they are using HSPICE to model TSVs, IBiS-AMI models and SERDES, respectively.… Read More


Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs

Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs
by Eric Esteve on 02-01-2013 at 8:25 am

ASIC design service companies are an essential piece of the SC ecosystem, as well as Silicon Foundries, EDA and IP vendors. Their customers range from pure fabless with no ASIC design resources, who need a third party to turn a concept into a real product (IC) and then market and sale it, to large IDM temporarily lacking design resource… Read More


Such a small piece of Silicon, so strategic PHY IP

Such a small piece of Silicon, so strategic PHY IP
by Eric Esteve on 04-30-2012 at 6:05 am

How could I talk about the various Interface protocols (PCIe, USB, MIPI, DDRn…) from an IP perspective and miss the PHY IP! Especially these days, where the PHY IP market has been seriously shaken, as we will see in this post, and will probably continue to be shaken… but we will have to wait and look at the M&A news during the next … Read More


Altera and Xilinx Eyeing 28nm FPGA Dominance

Altera and Xilinx Eyeing 28nm FPGA Dominance
by Ed McKernan on 08-11-2011 at 7:00 am

28nm FPGAs are finally hitting the market and the next round in the battle between Altera and Xilinx is heating up. At 40nm, Altera beat Xilinx out the door by a year and as a consequence won a lot of new sockets in the high end Communications market. In the past year, Altera has closed the revenue and market share gap with Xilinx. This … Read More


65nm to 45nm SerDes IP Migration Success Story

65nm to 45nm SerDes IP Migration Success Story
by Daniel Nenni on 05-25-2011 at 3:43 pm

The problem:To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintainedRead More