For about 5 years now Synopsys has held an HSPICE SIG event in conjunction with DesignCon. It features a small vendor faire with companies that partner with Synopsys on HSPICE flows. They also have a dinner with industry/customer speakers and provide an update on HSPICE development. Lastly there is a Q&A where customers get… Read More
Tag: serdes
Don’t Mess with SerDes!
SerDes stands for Serializer/Deserializer, and SerDes is a serious piece of design, requiring an extremely experienced team of analog engineers (below 10 years’ experience, you’re still a quasi-beginner). Better to rely on an analog guru to draw the SerDes architecture and manage the team! Why does SerDes is becoming more and… Read More
SerDes: Four Wires Are Better Than Two
Kandou Bus SA has recently been proposing the technique ENRZ (Ensemble Non Return to Zero) for use as the next generation interconnect standard for the 56 Gb/s generation of interconnect interfaces at the OIF (Optical Interconnect Forum). ENRZ is technique where three bits are orthogonally modulated over four correlated wires.… Read More
ISSCC 2014 SerDes Presentation
For those of you who missed the IEEE International Solid-State Circuits Conference last month some of the presentations are now hitting the company websites. The theme of this year’s conference was SILICON SYSTEMS BRIDGING THE CLOUD:… Read More
A Brief History of Kandou Bus
Kandou Bus uses a novel form of spatial coding to transmit data between wired chips. The main idea is to introduce correlations between the signals sent on the interface, and choose the correlations judiciously to lower the power consumption, increase the speed, and lower the footprint. It is a generalization of differential … Read More
High Quality PHY IPs Require Careful Management of Design Data and Processes
In last few years IP design has grown significantly compared to the rest of the semiconductor industry. There are newer IP start-ups opening across the world, particularly in India and China. Amid this rush, I wanted to understand the actual dynamics pushing this business and whether all of these IPs follow quality standards. … Read More
SilabTech Awarded 2013 Best Start-up in India
This is obviously great news for SilabTech, and this is the type of news which will change the perception that we (non-Indian) have of the Semiconductor industry in India. About 15-20 years ago, the India Embedded/VLSI industry was perceived as low cost design resource pool, a good place where to implement design center. The hidden… Read More
What’s new in the “Interface IP Survey” ?
The reader will find many updates in the “Interface IP Survey” from IPNEST, released in October 2013. Good question, as the IP market is a very fast moving one and the protocol based Interface IP, is moving even faster… exhibiting 20% growth rate in 2012, expected to grow with 10% CAGR between 2012 and 2017 to reach $700M. … Read More
Rare earth syndrome: PHY IP analogy
If you ask to IP vendors selling functions, PHY or Controller, supporting Interface based protocols which part is the master piece, the controller IP only vendors will answer: certainly my digital block, look how complex it has to be to support the transport and logical part of the protocol! Just think about the PCI Express gen-3… Read More
Signal integrity: more than just SerDes analysis
When Cadence acquired Sigrity in 2012, two motives were involved: get more competitive in state of the art signal integrity analysis, and grab a foothold into the other vendor’s PCB flows in an area that is developing as a real sore spot for digital designers.
Just as the days where PCB tape-out meant actually using tape are over, … Read More
