56G and 112G SerDes Where the rubber meets the road

56G and 112G SerDes Where the rubber meets the road
by Tom Simon on 12-11-2018 at 12:00 pm

No matter how high the processing capability of a chip, its overall performance is limited by IO speed. This is very similar to a car with low performance tires, a powerful engine will not be able to transfer its energy to the ground effectively. There is quite literally a race going on between core processing and IO speeds for transferring… Read More


RISC-V End to End Solutions for HPC and Networking

RISC-V End to End Solutions for HPC and Networking
by Daniel Nenni on 11-30-2018 at 12:00 pm

Semiconductor IP is one of the more exciting and most viewed topics we cover on SemiWiki, it has been that way since we began in 2011 and that trend will continue indefinitely, my opinion.

Semiconductor IP: Total Blogs: 640: Total Views: 3253751: Average: 5084

Based on the design starts we track, Cloud Computing is a leading semiconductor… Read More


Playing the Long Game with 56G SerDes

Playing the Long Game with 56G SerDes
by Daniel Nenni on 11-02-2018 at 12:00 pm

IP has always been a hot topic on SemiWiki with quite a bit of our readers doing the “make versus buy” analysis. SerDes is one of the more difficult “makes” so it is mostly a “buy” analysis made by networking class ASIC architects and a handful of other applications that demand high performance and throughput. Based on the recent traffic… Read More


Custom SoC Platform Solutions for AI Applications at the TSMC OIP

Custom SoC Platform Solutions for AI Applications at the TSMC OIP
by Daniel Nenni on 09-27-2018 at 12:00 pm

The TSMC OIP event is next week and again it is packed with a wide range of technical presentations from TSMC, top semiconductor, EDA, and IP companies, plus long time TSMC partner and ASIC provider Open-Silicon, a SiFive Company. You can see the full agenda HERE.

AI is revolutionizing and transforming virtually every industry… Read More


eSilicon and SiFive partner for Next-Generation SerDes IP

eSilicon and SiFive partner for Next-Generation SerDes IP
by Daniel Nenni on 08-10-2018 at 12:00 pm

While writing “Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices” it was very clear to me that ARM was an IP phenomenon that I did not believe would ever be repeated. Clearly I was wrong as we now have RISC-V with an incredible adoption rate, a full fledged ecosystem, and top tier implementers… Read More


Deep learning fueling the AI revolution with Interlaken IP Subsystem

Deep learning fueling the AI revolution with Interlaken IP Subsystem
by Daniel Nenni on 07-30-2018 at 7:00 am

AI is revolutionizing and transforming virtually every industry in the digital world. Advances in computing power and deep learning have enabled AI to reach a tipping point toward major disruption and rapid advancement. However, these applications require much higher performance and bandwidth requiring new kinds of IP and… Read More


7nm Networking Platform Delivers Data Center ASICs

7nm Networking Platform Delivers Data Center ASICs
by Daniel Nenni on 06-26-2018 at 7:00 am

We all know IP is critical for advanced ASIC design. Well-designed and carefully tested IP blocks and subsystems are the lifeblood of any advanced chip project. Those IP suppliers who can measure up to the need, especially at advanced process nodes, will do well, absolutely.

It is interesting to note that eSilicon now has a very … Read More


What does a Deep Learning Chip Look Like

What does a Deep Learning Chip Look Like
by Daniel Nenni on 02-16-2018 at 12:00 pm

There’s been a lot of discussion of late about deep learning technology and its impact on many markets and products. A lot of the technology under discussion is basically hardware implementations of neural networks, a concept that’s been around for a while.

What’s new is the compute power that advanced semiconductor technology… Read More


High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory

High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory
by Mitch Heins on 02-07-2018 at 10:00 am


High Bandwidth Memory (HBM) systems have been successfully used for some time now in the network switching and high-performance computing (HPC) spaces. Now, adding fuel to the HBM fire, there is another market that shares similar system requirements as HPC and that is Artificial Intelligence (AI), especially AI systems doing… Read More


Safety qualification for leading edge IP elements – presentation at REUSE 2017 in Santa Clara

Safety qualification for leading edge IP elements – presentation at REUSE 2017 in Santa Clara
by Tom Simon on 12-06-2017 at 12:00 pm

To ensure the reliability of automotive electronics, standards like AEC-Q100 and ISO 26262 have helped tremendously. They have created rational and explicit steps for developing and testing the electronic systems that go into our cars. These are not some abstract future requirement for fully autonomous cars, rather they are… Read More