Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors–errors that can… Read More
Tag: semiconductor
New ERC Tools Catch Design Errors
A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.By Matthew Hogan
Today’s IC designs are complex. They contain vast arrays of features and functionality in … Read More
TSMC Raises The Semiconductor Bar With 450mm!
During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!
According to Morris Chang:
“For… Read More
Getting to the 32nm/28nm Common Platform node with Mentor IC Tools
Last week I talked with two experts at Mentor about the challenges of getting IC designs into the 32nm/28nm node on the Common Platform (IBM, GLOBALFOUNDRIES and Samsung). Global Foundries issued a press release talking about how the four major EDA companies have worked together to qualify EDA tools for this node.
Sudhakar Jilla,… Read More
The Future of Semiconductor Design!
Is EDA still an appropriate term for what we do? What applications will drive future semiconductor design innovation? Will further consolidation be required for EDA to thrive again? They are all good questions, questions that will hopefully be properly addressed at the EDAC CEO Forecast and Industry Vision event next week but… Read More
Semiconductor and EDA Forecasts 2011 / 2012
Of course these are rolling forecasts which means they change every month, until they get them right. The missing forecaster here is Mike Cowen, developer of the Cowan LRA Model which forecasts global semiconductor sales. Mike has 2011 at a hilarious 2.3%! Below are the mid year market forecasts which were revised significantly… Read More
Mentor – Cadence Merger and the Federal Trade Commission
More consolidation is coming to EDA and so is the Federal Trade Commission. Corporate raider Carl Ichan owns 15% of Mentor Graphics and now owns 1% of Cadence. Ichan buddy multi billionaire George Soros, a long time CDNS investor, just purchased more than 76 million convertible notes of MENT.You do the math…
Unfortunately the FTC… Read More
Tanner EDA Then and Now
Looking back at an early issue of a Tanner Research newsletter, “Tanner Tools News”, from the mid-1990s, the theme at that time was growth, just as it is again now for Tanner EDA. At that time we were averaging 66% revenue growth per year, enjoying rapid growth as a small start-up. Fast-forward to current day, where we… Read More
Computational Lithography, Scaling’s Best Friend
By Joseph Sawicki, Vice President & General Manager, Design to Silicon Division
It is one of the more amazing stories in the continued march of Moore’s Law over the past four nodes. Previously scaling was enabled solely though changes in the physical domain, whether through decreasing the wavelength of light, increasing … Read More
Steve Jobs’ 5 Minute Anti Open Systems Rant!
First of all it was not a rant, it was a clearly scripted rebuttal to the competitive pressures Apple is feeling from Android (here). As I blogged before, Apple is the Open Standards Antichrist and is trying to monopolize the trillion dollar mobile internet ecosystem with a CLOSED platform. According to Steve Jobs, “Open systems… Read More