DAC is a great place to gather information about products and technologies. However it can be difficult to chase down the information you need because you may need to cover a lot of ground to hear or talk to the people with the right knowledge. Fortunately there are a few places you can go to learn about a number of products at one place.… Read More
Tag: oip
TSMC 10nm Readiness and 3DIC
At the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!
Around the turn of the millennium Suk actually… Read More
TSMC’s OIP: Everything You Need for 16FF+ SoCs
Doing a modern SoC design is all about assembling IP and adding a small amount of unique IC design for differentiation (plus, usually, lots of software). If you re designing in a mature process then there is not a lot of difficulty finding IP for almost anything. But if you are designing in a process that has not yet reached high-volume… Read More
TSMC Gets Ready for IoT
With all the talk about 14/16nm and 10nm it is important to realize that older processes are still important. Eventually 16nm may end up being cheaper than 28nm but for the time being 28nm seems to be a sort of sweet spot, not just cheaper than every process that came before it (which was true for every new node) but also cheaper than every… Read More
Cliff Hou at TSMC OIP
I attended Cliff Hou’s keynote at TSMC OIP Forum earlier this month. OIP is a huge undertaking. It currently has over 100 ecosystem partners, 10 technology generations, 7600+ IPs, 60+ EDA tools, 7000+ tech files and 150+ PDKs.
Most of Cliff’s presentation gave details on where TSMC are with the various processes. … Read More
Mentor at TSMC OIP, 16nm, and 10nm
On Tuesday, September 30, TSMC hosts another Open Innovation Platform Ecosystem forum at the San Jose Convention Center. Have you registered? This year includes 30 technical sessions from TSMC’s ecosystem partners, divided into three separate tracks. I’ll be hanging out in the EDA track, listening to various takes on 16nm FinFET… Read More
TSMC OIP: Registration Open
It’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s design challenges.… Read More
TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC
What is TSMC doing at DAC?
The biggest event is presumably Cliff Hou’s DAC keynote on Monday at 3.25pm Industry Opportunities in the Sub-10nm Era. And he also wrote the foreword to Fabless, the book that Dan Nenni and I have written and where you can get a signed copy on Tuesday evening at the reception.
There is an IP workshop … Read More
TSMC OIP presentations available!
Are you a TSMC customer or partner? If so, you’ll want to take a look at these presentations from the 2013 TSMC Open Innovation Platform conference:
- Design Reliability with Calibre YE-SmartFill and Calibre PERC (Broadcom & Mentor Graphics)
New methodologies were developed for 28nm designs using Calibre SmartFill and Calibre
ESD at TSMC: IP Providers Will Need to Use Mentor to Check
I met with Tom Quan of TSMC and Michael Beuler-Garcia of Mentor last week. Weirdly, Mentor’s newish buildings are the old Avant! buildings where I worked for a few weeks after selling Compass Design Automation to them. Odd sort of déja vu. Historically, TSMC has operated with EDA companies in a fairly structured way: TSMC … Read More