Chip and I/O Modeling for System-level Power Noise Analysis and Optimization

Chip and I/O Modeling for System-level Power Noise Analysis and Optimization
by Daniel Payne on 05-14-2013 at 4:13 pm

Cornelia Golovanovworks at LSI Corp in Pennsylvania and is an EMI expert that provides EDA tool and methodology advise to design groups. She earned a PhD in microelectronics and radioelectricity from the Institut national polytechnique de Grenoble, and joined Lucent out of school 12 years ago. We had a chance to talk by phone about… Read More