An Update on In-Line Wafer Inspection Technology

An Update on In-Line Wafer Inspection Technology
by Tom Dillinger on 06-06-2022 at 6:00 am

inspection overview

From initial process technology development (TD) to high volume manufacturing (HVM) status for a new node, one of the key support functions to improve and maintain yield is the in-line wafer inspection technology.  Actually, there are multiple inspection technologies commonly employed, with tradeoffs in pixel resolution,… Read More


0.55 High-NA Lithography Update

0.55 High-NA Lithography Update
by Tom Dillinger on 05-31-2022 at 6:00 am

mask infrastructure 0 55

At the recent SPIE Advanced Lithography + Patterning Conference, Mark Phillips from Intel gave an insightful update on the status of the introduction of the 0.55 high numerical aperture extreme ultraviolet lithography technology.  Mark went so far as to assert that the development progress toward high-NA EUV would support … Read More


The New Normal for Semiconductor Manufacturing

The New Normal for Semiconductor Manufacturing
by Daniel Nenni on 05-27-2022 at 6:00 am

200mm 300mm Semiconductor Capacity

One of the recent live events I attended was the 2022 GSA Silicon Leadership Summit on May 12th at the Santa Clara Convention Center (my favorite location). This was the first GSA live event in two years so it was a must attend gathering. This event targets semiconductor ecosystem executives (200+ people attended) so there were many… Read More


Intel to present Intel 4 process at the VLSI Technology Symposium

Intel to present Intel 4 process at the VLSI Technology Symposium
by Scotten Jones on 05-20-2022 at 8:00 am

VLSI Symposium 2022 SemiWiki 1

The VLSI Symposium on Technology & Circuits will be held in Hawaii from June 12th to June 17th. You can register for the conference here.

The tip sheet for the conference has been released and one thing that caught my eye is some data from the Intel 4 paper that Intel will be presenting at the conference.

Intel’s old roadmap had 14nm,… Read More


Semiconductor Crash Update

Semiconductor Crash Update
by Daniel Nenni on 05-12-2022 at 10:00 am

Semiconductors are Capturing Electronics

Earlier this year semiconductor oracle Malcom Penn did his 2022 forecast which I covered here: Are We Headed for a Semiconductor Crash? The big difference with this update is the black economic clouds that are looming which may again highlight Malcolm’s forecasting prowess. I spent an hour with Malcolm and company on his Zoom cast… Read More


The Lost Opportunity for 450mm

The Lost Opportunity for 450mm
by Scotten Jones on 04-15-2022 at 6:00 am

450mm Wafer SemiWiki


I spent several days this week at the SEMI International Strategy Symposium (ISS). One of the talks was “Can the Semiconductor Industry Reach $1T by 2030” given by Bob Johnson of Gartner. His conclusion was, that $1 trillion dollars is an aggressive forecast for 2030 but certainly we should reach $1 trillion dollars in the next 10… Read More


Intel and the EUV Shortage

Intel and the EUV Shortage
by Scotten Jones on 04-13-2022 at 10:00 am

Slide1

In my “The EUV Divide and Intel Foundry Services” article available here, I discussed the looming EUV shortage. Two days ago, Intel announced their first EUV tool installed at their new Fab 34 in Ireland is a tool they moved from Oregon. This is another indication of the scarcity of EUV tools.

I have been tracking EUV system production… Read More


Can Intel Catch TSMC in 2025?

Can Intel Catch TSMC in 2025?
by Scotten Jones on 04-11-2022 at 6:00 am

Slide6

At the ISS conference held from April 4th through 6th I presented on who I thought would have the leading logic technology in 2025. The following is a write up of that presentation.

ISS was a virtual conference in 2021 and I presented on who currently had logic leadership and declared TSMC the clear leader. Following that conference,… Read More


Intel Best Practices for Formal Verification

Intel Best Practices for Formal Verification
by Daniel Nenni on 04-07-2022 at 6:00 am

formal dynamic verification comparison

Dynamic event-based simulation of RTL models has traditionally been the workhorse verification methodology.  A team of verification engineers interprets the architectural specification to write testbenches for various elements of the design hierarchy.  Test environments at lower levels are typically exercised then … Read More


The EUV Divide and Intel Foundry Services

The EUV Divide and Intel Foundry Services
by Scotten Jones on 03-23-2022 at 10:00 am

Intel IDM 2.0 Process Roadmap
The EUV Divide

I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.

If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production… Read More