I cut my teeth in silicon IC design at Texas Instruments during the early 1980’s working on what would eventually become the ASIC and Fabless IC industries that enabled the explosive growth of the electronics industry over the last three decades. Of late I’ve become involved in the silicon photonics space and I am getting an incredible… Read More
Tag: imec
SPIE – Interview with Greg Mcintyre of IMEC
One of the things I really like about major technical conferences is the opportunity to meet with people for networking and interviews. On Wednesday at the Advanced Lithography Conference I had the opportunity to interview Greg Mcinttyre, the director of advanced patterning at IMEC.
IMEC researchers are the first author on 32… Read More
ASML and IMEC EUV Progress
Day 1 of the SPIE conference featured a number of customer updates on the status of their EUV programs. On Tuesday morning we got to hear ASML’s update on their work.… Read More
5nm Chips? Yes, but When?
For any invention, technical proof of concept or prototyping happens years ahead of the invention being infused into actual products. When we talk about 5nm chip manufacturing, a test chip was already prototyped in last October, thanks to Cadence and Imec. Details about this chip can be found in a blog at Semiwiki (link is given … Read More
Coventor ASML IMEC: The last half nanometer
On Tuesday evening December 8[SUP]th[/SUP] at IEDM, Coventor held a panel discussion entitled the “The last half nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels… Read More
IEDM Blogs – Part 7 – IMEC Technology Forum – Part 2
On Sunday evening December 6[SUP]th[/SUP] before IEDM, IMEC held the IMEC Technology Forum (ITF). In part 1 of this blog I discussed the introduction and the first two presentations given by An Steegen and Mark Rodder. In this blog I will discuss the final two presentations. Part 1 can be accessed here.… Read More
IEDM Blogs – Part 6 – IMEC Technology Forum – Part 1
On Sunday evening December 6[SUP]th[/SUP] before IEDM, IMEC held the IMEC Technology Forum (ITF). The ITF was held at the Belgium ambassador’s residence, a really beautiful setting for a meeting.
The ITF began with a brief welcome by the Belgium ambassador followed by a brief introduction to IMEC. IMEC is a research institute … Read More
IEDM Blogs – Part 4 – IMEC InGaAs Channel for 3D NAND
At IEDM IMEC presented “MOCVD In[SUB]1-x[/SUB]Ga[SUB]x[/SUB]As high mobility channel for 3-D NAND Memory” authored by E. Capogreco, J. G. Lisoni, A. Arreghini, A. Subirats, B. Kunert, W. Guo, T. Maurice, C.-L. Tan, R. Degraeve, K. De Meyer, G. Van den bosch, and J. Van Houdt.
On December 15[SUP]th[/SUP] I had the opportunity … Read More
IEDM 2015 Blogs – Part 1 – Overview
The International Electron Devices Meeting (IEDM) is one of, if not the premier conference for semiconductor process technology. The 2015 meeting just finished up on Wednesday, December 9th.
This year’s meeting was held from Saturday, December 5[SUP]th[/SUP] through Wednesday, December 9[SUP]th[/SUP] in Washington DC.… Read More
IMEC and Cadence Disclose 5nm Test Chip
Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.
First off Vassilios really… Read More