At IEDM 2019, TSMC revealed two versions of 5nm standard cell layouts: a 5.5-track DUV-patterned version and a 6-track EUV-patterned version [1]. Although the metal pitches were not explicitly stated, later analyses of a 5nm product, namely, Apple’s A15 Bionic chip, revealed a cell height of 210 nm [2]. For the 6-track … Read More
Tag: IEDM 2019
TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020
Technological leadership has long been key to TSMC’s success and they are following up their leadership development of 5nm with the world’s smallest SRAM cell at 0.021um 2 with circuit design details of their write assist techniques necessary to achieve the full potential of this revolutionary technology. In addition to their… Read More
STT MRAM Highlights from IEDM 2019
IEDM 2019 had the theme: “Innovative Devices for an Era of Connected Intelligence” of which MRAM is a leading contributor. Following a very informative Plenary Session, Monday afternoon led off with Session 2: Memory Technology – STT-MRAM. This session has seven important STT-MRAM papers describing the progress of this … Read More
IEDM 2019 Press Lunch Exposed!
One of the many benefits of blogging for SemiWiki is the free conference passes and buffet lunches, absolutely. IEDM is one of the more prestigious semiconductor conferences, now in its 65th year, is being held at the Hilton Hotel in San Francisco’s famed Union Square this week. This year more than 1,910 semiconductor professionals… Read More
Bob Swan says Intel 7nm equals TSMC 5nm!
Bob Swan is really starting to grow on me. Admittedly, I am generally not a fan of CFOs taking CEO roles at semiconductor companies but thus far Bob is doing a great job. This comes from my outside-looking-in observations and from the people I know inside Intel, absolutely.
Bob did a fireside chat with Credit Suisse at their 23rd annual… Read More
My Top Three Reasons to Attend IEDM 2019
The International Electron Devices Meeting is a premier event to learn about the latest in semiconductor process technology. Held every year in early December is San Francisco this years conference will be held from Decembers 7th through December 11th. You can learn more about the conference at their web site here.
This is a must… Read More