In this tutorial we will see how to design a VHDL block. We will start with a very simple block and we will gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see:
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Tag: fpga
Did My FPGA Just Fail?
Designing DRAMs at Intel back in the 1970s I first learned about Soft Errors and the curious effect of higher failure rates of DRAM chips in Denver, Colorado with a higher altitude than Aloha, OR. With the rapid growth of FPGA-based designs in 2016, we are still asking the same questions about the reliability of our chips used for safety-critical… Read More
Score 1 for IDMs vs Fabless Intel King of the Photonics Hill in Data Centers
For those of you waiting with baited breath to see the Fabless community with the likes of Broadcom or Qualcomm challenge Intel in the data center space, you were just dealt a significant blow. Intel debuted their long awaited silicon photonics modules for what they called “lightning-fast” connectivity in data centers. Intel … Read More
Xilinx is Killing Altera!
At a recent outing with FPGA friends from days gone by, the long running Xilinx vs Altera debate has come to an end. The bottom line is that Xilinx has used the FUD (fear, uncertainty, and doubt) of the Intel acquisition quite effectively against Altera and is racking up 20nm and 16nm design wins at an alarming rate. It will be a while … Read More
Fast Track to a reconfigurable ASIC design
Licensing IP can be a pain, especially when the vendor’s business model has front-loaded costs to get started. Without an easy way to evaluate IP, justifying a purchase may be tough. With more mid-volume starts coming for the IoT, wearables, automotive, and other application segments, it’s a growing concern. Flex… Read More
Mentor Extends Verification Offering!
With verification consuming more and more of the design cycle and the increasingly complex industry standard interfaces that are now common place, Verification IP (VIP) is again a trending topic. Back in my IP days the age old question was: Is it better to use VIP from the IP vendor? Because you know it will work, right? Or is it better… Read More
FPGA tools for more predictive needs in critical
“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when?… Read More
5nm Chips? Yes, but When?
For any invention, technical proof of concept or prototyping happens years ahead of the invention being infused into actual products. When we talk about 5nm chip manufacturing, a test chip was already prototyped in last October, thanks to Cadence and Imec. Details about this chip can be found in a blog at Semiwiki (link is given … Read More
The Twists and Turns of Xilinx vs Altera!
The battle between Xilinx and Altera continues to be one of the more interesting stories to cover. It really is the semiconductor version of a reality TV show. In the beginning it was two fabless companies partnered with rival foundries going head-to-head controlling a single market that touches a variety of industries.
Then things… Read More
HLS with ARM and FPGA Technologies Boosts SoC Performance
The way SoC size and complexity are increasing; new ways of development and verification are also evolving with innovative automated tools and environment for SoC development and optimization. IP based SoC development methodology has proved to be the most efficient for large SoCs. This needs collaboration among multiple players… Read More