A New Class of Accelerator Debuts

A New Class of Accelerator Debuts
by Bernard Murphy on 07-22-2024 at 6:00 am

Chimera GPNPU Block diagram

I generally like to start my blogs with an application-centric viewpoint; what end-application is going to become faster, lower power or whatever because of this innovation? But sometimes an announcement defies such an easy classification because it is broadly useful. That’s the case for a recent release from Quadric, based… Read More


Elevating Your SoC for Reconfigurable Computing – EFLX® eFPGA and InferX™ DSP and AI

Elevating Your SoC for Reconfigurable Computing – EFLX® eFPGA and InferX™ DSP and AI
by Kalar Rajendiran on 05-28-2024 at 10:00 am

Use Case eFPGA Complementing Signal Processing

Field-Programmable Gate Arrays (FPGAs) have long been celebrated for their unmatched flexibility and programmability compared to Application-Specific Integrated Circuits (ASICs). And the introduction of Embedded FPGAs (eFPGAs) took these advantages to new heights. eFPGAs offer on-the-fly reconfiguration capabilities,… Read More


Synopsys Design IP for Modern SoCs and Multi-Die Systems

Synopsys Design IP for Modern SoCs and Multi-Die Systems
by Kalar Rajendiran on 04-11-2024 at 10:00 am

Synopsys IP Scale, a Sustainable Advantage

Semiconductor intellectual property (IP) plays a critical role in modern system-on-chip (SoC) designs. That’s not surprising given that modern SoCs are highly complex designs that leverage already proven building blocks such as processors, interfaces, foundational IP, on-chip bus fabrics, security IP, and others. This… Read More


A Modeling, Simulation, Exploration and Collaborative Platform to Develop Electronics and SoCs

A Modeling, Simulation, Exploration and Collaborative Platform to Develop Electronics and SoCs
by Daniel Payne on 03-26-2024 at 10:00 am

Demo Chiplet System with CPU, DSP, GPU, IO, AI

During the GOMACTech conference held in South Carolina last week I had a Zoom call with Deepak Shankar, Founder and VP Technology at Mirabilis Design Inc. to ask questions and view a live demo of VisualSim – a modeling, simulation, exploration and collaborative platform to develop electronics and SoCs. What makes VisualSim so … Read More


2024 Outlook with Steve Roddy of Quadric

2024 Outlook with Steve Roddy of Quadric
by Daniel Nenni on 01-29-2024 at 10:00 am

Man on Llama

Quadric Inc. is the leading licensor of general-purpose neural processor IP (GPNPU) that runs both machine learning inference workloads and classic DSP and control algorithms.  Quadric’s unified hardware and software architecture is optimized for on-device ML inference. I have know Steve Roddy for many years, he is a high … Read More


Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing

Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing
by Kalar Rajendiran on 11-21-2023 at 10:00 am

CEVA Comprehensive Edge AI Portfolio

The surge in Edge AI applications has propelled the need for architectures that balance performance, power efficiency, and flexibility. Architectural choices play a pivotal role in determining the success of AI processing at the edge, with trade-offs often necessary to meet the unique demands of diverse workloads. There are… Read More


Accelerating Development for Audio and Vision AI Pipelines

Accelerating Development for Audio and Vision AI Pipelines
by Bernard Murphy on 11-15-2023 at 6:00 am

AI pipeline min

I wrote previously that the debate over which CPU rules the world (Arm versus RISC-V) somewhat misses the forest for the trees in modern systems. This is nowhere more obvious that in intelligent audio and vision: smart doorbells, speakers, voice activated remotes, intelligent earbuds, automotive collision avoidance, self-parking,… Read More


Cadence Tensilica Spins Next Upgrade to LX Architecture

Cadence Tensilica Spins Next Upgrade to LX Architecture
by Bernard Murphy on 09-21-2023 at 6:00 am

Xtensa LX8 processor

When considering SoC architectures it is easy to become trapped in simple narratives. These assume the center of compute revolves around a central core or core cluster, typically Arm, more recently perhaps a RISC-V option. Throw in an accelerator or two and the rest is detail. But for today’s competitive products that view is a … Read More


Inference Efficiency in Performance, Power, Area, Scalability

Inference Efficiency in Performance, Power, Area, Scalability
by Bernard Murphy on 09-19-2023 at 6:00 am

AI graphic

Support for AI at the edge has prompted a good deal of innovation in accelerators, initially in CNNs, evolving to DNNs and RNNs (convolutional neural nets, deep neural nets, and recurrent neural nets). Most recently, the transformer technology behind the craze in large language models is proving to have important relevance at… Read More


Next-Gen AI Engine for Intelligent Vision Applications

Next-Gen AI Engine for Intelligent Vision Applications
by Kalar Rajendiran on 08-14-2023 at 10:00 am

Synopsys ARC MetaWare NN SDK

Artificial Intelligence (AI) has witnessed explosive growth in applications across various industries, ranging from autonomous vehicles and natural language processing to computer vision and robotics. The AI embedded semiconductor market is projected to reach $800 billion by year 2030. Compare this with just $48 billion… Read More