Agile IC: All You Gotta Do To Join Is…

Agile IC: All You Gotta Do To Join Is…
by Paul McLellan on 04-24-2015 at 7:00 am

Back last October 1st was an announcement of Agile IC Methodology. As I said then:Today Sonics has launched the Agile IC Methodology along with several collaborators. The initial phase is to create a LinkedIn group to start the discussion.

See also Agile IC Development

At that point there was just an idea and a LinkedIn group. The… Read More


Networking at 52nd DAC in SFO

Networking at 52nd DAC in SFO
by Daniel Payne on 04-19-2015 at 7:00 pm

Yes, the 52nd DAC(Design Automation Conference) is a technical conference plus exhibition with wonderful keynote speakers and agenda, however there is a certain serendipity that occurs by just meeting people, face to face at the many networking opportunities. The best way to kick off your DAC experience is by attending the Sunday… Read More


Successful Venture of an Indian Global VIP Company

Successful Venture of an Indian Global VIP Company
by Pawan Fangaria on 04-17-2015 at 10:00 am

It’s rare that we find a truly Indian-based company operating globally in the semiconductor space. Although the ‘gold rush’ towards IP development in the last decade initiated many IP start-ups in India, today we rarely find Indian IP company names which are shining in the global arena. The story of services companies is different,… Read More


Grenoble Comes to San Francisco

Grenoble Comes to San Francisco
by Paul McLellan on 04-14-2015 at 7:00 am

The headquarters of ST Microelectronics is officially in Switzerland, but in many ways the center of gravity is in the Grenoble area. You may have heard of Crolles where ST does process development, manufacturing and more, which is about ten miles north-east of the city. As a result, along with the CEA-LETI and Grenoble Institute… Read More


Safety Dominates Agenda in DAC’s Automotive Track

Safety Dominates Agenda in DAC’s Automotive Track
by Majeed Ahmad on 04-12-2015 at 4:00 pm

The connected car movement is in full bloom, making headlines in the trade media on how the cutting-edge electronics will transform the twenty-first century driving experience. However, a closer look at the Internet of cars juggernaut shows that safety and security of the networked vehicle are still a major stumbling block.… Read More


Security All Around in SoCs at DAC

Security All Around in SoCs at DAC
by Pawan Fangaria on 04-06-2015 at 12:00 am

Last month I was on my way to write a detailed article on important aspects to look at while designing an SoC. This was important in the new context of modern SoCs that go much beyond the traditional power, performance and area (PPA) requirements. I had about 12-13 parameters in my list that I couldn’t cover in one go, so I put the write-up… Read More


DAC Keynotes: Mark Your Calendar

DAC Keynotes: Mark Your Calendar
by Paul McLellan on 04-03-2015 at 7:00 am

DAC starts in San Francisco on June 8th. The kickoff keynote at 9.20am that morning is by Brian Otis of Google. He is a director at Google[x]. According to Wikipedia:Google X, stylized as Google[x], is a semi-secret facility run by Google dedicated to making major technological advancements. It is located about a half mile from Read More


SoCs More Vulnerable to ESD at Lower Nodes

SoCs More Vulnerable to ESD at Lower Nodes
by Pawan Fangaria on 03-11-2015 at 1:00 pm

Electro Static Discharge (ESD) has been a major cause of failures in electronic devices. As the electronic devices have moved towards high density SoCs accommodating ever increasing number of gates at lower process nodes, their vulnerability to ESD effects has only increased. Among the reasons for ESD failures in SoCs, device… Read More


DAC: March Update

DAC: March Update
by Paul McLellan on 03-02-2015 at 7:00 am

DAC is coming up. It is already March. If you are in the EDA industry then it is basically three months away, which sounds a lot until you actually have to get everything pulled together so that your booth is ready to go on Monday June 7[SUP]th[/SUP]. Exhibit hours have been extended and now run from 10am to 7pm (only until 6pm on Wednesday).… Read More


In-Design DFM Signoff for 14nm FinFET Designs

In-Design DFM Signoff for 14nm FinFET Designs
by Pawan Fangaria on 11-04-2014 at 4:00 pm

While FinFET yield controversy is going on, I see a lot being done to improve that yield by various means. One prime trend today, it must be, it’s worthwhile, is to pull up various signoffs as early as possible during the design cycle. And DFM signoff is a must with respect to yield of fabrication. This reminds me about my patents filed… Read More