Place & Route with FinFETs and Double Patterning

Place & Route with FinFETs and Double Patterning
by Paul McLellan on 09-29-2014 at 8:00 am

Place & route in the 16/14nm era requires a new approach since it is significantly more complex. Of course, every process generation is more complex than the one before and the designs are bigger. But modern processes have new problems. The two biggest changes are FinFETs and double patterning.

FinFETs, as I assume you know,… Read More


Temperature – The Fourth Aspect to Look at in SoC Design

Temperature – The Fourth Aspect to Look at in SoC Design
by Pawan Fangaria on 07-25-2014 at 2:00 pm

In my career in semiconductor industry, I can recall, in the beginning there was emphasis on design completion with automation as fast as possible. The primary considerations were area and speed of completion of a semiconductor design. Today, with unprecedented increase in multiple functions on the same chip and density of the… Read More


An Update on Calibre at DAC

An Update on Calibre at DAC
by Daniel Payne on 06-09-2014 at 12:00 pm

Even though I live just 7 miles away from the Mentor Graphics corporate office in Oregon, I visited their DAC suite in San Francisco last week to get an update on Calibrefrom Michael White. The Calibre tools are used during IC verification and sign-off by performing DRC (Design Rule Checking) and LVS (Layout Versus Schematic).… Read More


FinFET & Multi-patterning Need Special P&R Handling

FinFET & Multi-patterning Need Special P&R Handling
by Pawan Fangaria on 04-28-2014 at 1:00 pm

I think by now a lot has been said about the necessity of multi-patterning at advanced technology nodes with extremely low feature size such as 20nm, because lithography using 193nm wavelength of light makes printing and manufacturing of semiconductor design very difficult. The multi-patterning is a novel semiconductor manufacturing… Read More


Show Me How To Get Better DRC and LVS Results For My SoC Design

Show Me How To Get Better DRC and LVS Results For My SoC Design
by Daniel Payne on 04-14-2014 at 3:30 pm

Most IC engineers learn best by hands-on experience when another more experienced person can show us what to do. If you cannot find that experienced person, then the next best thing is a video from an expert. I was surprised to find out that video was so important today that the #2 most viewed web site on the Internet was www.youtube.comRead More


ESD at TSMC: IP Providers Will Need to Use Mentor to Check

ESD at TSMC: IP Providers Will Need to Use Mentor to Check
by Paul McLellan on 01-22-2014 at 1:24 pm

I met with Tom Quan of TSMC and Michael Beuler-Garcia of Mentor last week. Weirdly, Mentor’s newish buildings are the old Avant! buildings where I worked for a few weeks after selling Compass Design Automation to them. Odd sort of déja vu. Historically, TSMC has operated with EDA companies in a fairly structured way: TSMC … Read More


An easier way to deal with design rule waivers (video)

An easier way to deal with design rule waivers (video)
by Beth Martin on 10-26-2013 at 11:00 am

At advanced nodes, design rules are necessarily more complex and restrictive. Although most of the time you can find a way to live with them, sometimes it’s necessary to seek a waiver from the foundry for a particular design feature. This involves documenting the feature, the design rules in question and the conditions under which… Read More


Real Time Concurrent Layout Editing – It’s Possible

Real Time Concurrent Layout Editing – It’s Possible
by Pawan Fangaria on 09-03-2013 at 2:00 pm

Layout editing is a complex task, traditionally done manually by designers, and the layout design productivity largely depends on the designer’s skills and expertise. However, a good tool with features for ease of design is a must. Layout productivity has been an area of focus and various features are constantly being added in… Read More


Robust Design <- Robust Flow <- Robust Tools

Robust Design <- Robust Flow <- Robust Tools
by Pawan Fangaria on 08-10-2013 at 6:00 pm

I could have written the sequence of the title in reverse order, but no, design is the one which initiates the need of a particular flow and the flow needs support of EDA tools to satisfy that need. It’s okay if the design is small; some manual procedures and workarounds/scripts may be able to perform certain jobs. However, as the design… Read More


Best Practices for Using DRC, LVS and Parasitic Extraction – on YouTube

Best Practices for Using DRC, LVS and Parasitic Extraction – on YouTube
by Daniel Payne on 07-10-2013 at 1:21 pm

EDA companies produce a wealth of content to help IC engineers get the best out of their tools through several means:

  • Reference Manuals
  • User Guides
  • Tutorials
  • Workshops
  • Seminars
  • Training Classes
  • Phone Support
  • AE visits
Read More